CN119199487A - Chip testing method, device, electronic equipment and storage medium - Google Patents
Chip testing method, device, electronic equipment and storage medium Download PDFInfo
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G—PHYSICS
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- G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
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- G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
- G01B11/00—Measuring arrangements characterised by the use of optical techniques
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Abstract
本发明实施例公开了一种芯片测试方法、装置、电子设备及存储介质，涉及半导体测试技术领域，其中，所述方法包括：建立防呆检测机制，使用摄像设备水平移动的方式和防呆检测机制对晶圆片进行水平扫直得到水平的晶圆片，根据晶圆片的特征点位置、距离计算公式和摄像机的视觉识别功能得到晶圆片的圆心位置和直径，根据晶圆片中各芯片的尺寸和切割道尺寸、芯片之间的距离以及晶圆片的圆心位置和特征点位置，得到晶圆片的Map图，通过摄像机获取针尖偏移角度，根据针尖偏移角度对晶圆片进行旋转并根据针尖偏移角度更新Map图，根据Map图进行芯片测试。本发明解决了现有技术兼容性差，自动化程度低，生产效率和准确率低的问题。
The embodiment of the present invention discloses a chip testing method, device, electronic device and storage medium, which relates to the field of semiconductor testing technology, wherein the method includes: establishing a foolproof detection mechanism, using a camera device to move horizontally and the foolproof detection mechanism to horizontally scan a wafer to obtain a horizontal wafer, obtaining the center position and diameter of the wafer according to the characteristic point position of the wafer, the distance calculation formula and the visual recognition function of the camera, obtaining a map of the wafer according to the size of each chip in the wafer and the size of the cutting path, the distance between the chips and the center position and characteristic point position of the wafer, obtaining a needle tip offset angle through a camera, rotating the wafer according to the needle tip offset angle and updating the map according to the needle tip offset angle, and performing chip testing according to the map. The present invention solves the problems of poor compatibility, low automation, low production efficiency and low accuracy of the prior art.
Description
Technical Field
The present invention relates to the field of semiconductor testing technologies, and in particular, to a method and apparatus for testing a chip, an electronic device, and a storage medium.
Background
With the rapid development of semiconductor technology, the sizes and types of chips integrated on a wafer are more and more diversified. In the wafer test process, the MAP (test MAP) plays a crucial role, and can accurately position each chip, so that the test accuracy and efficiency are ensured.
However, in the conventional wafer chip test scheme, there are obvious limitations in design and application of the MAP, and the MAP is often only compatible with chips of one size, and when chips of multiple sizes exist on a wafer, the MAP needs to be built for each size of chip, which not only greatly reduces production efficiency, but also increases the risk of errors.
In addition, the existing MAP creation mode, such as manual creation or scan chip generation, has the problems of high time cost, low precision and the like, and particularly in the multi-SITE needle card test, because the needle tip angles of a single SITE needle card and a multi-SITE needle card are different, the traditional test scheme often needs to manually adjust the needle card position to align to the pricking test Pad position of the wafer chip, so that the operation is complex, errors are easily introduced, and the accuracy and the efficiency of the test are seriously affected.
Therefore, a chip testing method compatible with chips of multiple sizes, high in automation degree and high in accuracy of detecting needle marks is needed.
Disclosure of Invention
The embodiment of the invention provides a chip testing method for solving the problems that the prior art cannot be compatible with chips with multiple sizes, the degree of automation is low, and the production efficiency and the accuracy are low. The technical scheme is as follows:
According to one aspect of the invention, a chip testing method comprises the steps of establishing a foolproof detection mechanism, horizontally sweeping a wafer by using a horizontal moving mode of camera equipment and the foolproof detection mechanism to obtain a horizontal wafer, obtaining the circle center position and the diameter of the wafer according to the characteristic point position of the wafer, a distance calculation formula and a visual recognition function of a camera, obtaining a Map of the wafer according to the size and the cutting path size of each chip in the wafer, the distance between the chips and the circle center position and the characteristic point position of the wafer, obtaining a needle point offset angle through a camera, rotating the wafer according to the needle point offset angle, updating the Map according to the needle point offset angle, and testing the chips according to the Map.
In one embodiment, the wafer is horizontally scanned by using a horizontal movement mode of the camera device and the fool-proof detection mechanism, and the wafer with the horizontal obtained is realized by loading the wafer under the camera device through a bearing table, automatically acquiring the position of a chip through the camera device, calculating and adjusting the horizontal angle of the wafer by adopting two-point continuous positioning and slope angle, and verifying by using the fool-proof detection mechanism, wherein the wafer with the horizontal obtained is verified by verification.
In one embodiment, the slope angle calculation formula is:
;
The difference between the ordinate and the initial ordinate refers to the difference between the ordinate of the chip and the initial ordinate in the moving process, the difference between the abscissa and the initial abscissa of the chip in the moving process, the fool-proof detection mechanism is that horizontal sweeping is successful if the slope angle is smaller than or equal to a set angle, and horizontal sweeping is performed again if the slope angle is larger than the set angle.
In one embodiment, the circle center position and the diameter of the wafer are obtained according to the characteristic point position of the wafer, a distance calculation formula and the visual recognition function of the camera by constructing a two-dimensional coordinate system by taking the characteristic point of the wafer as an origin, and obtaining three edge point positions of the wafer through the distance calculation formula and the visual recognition function of the camera; and according to the size and the diameter of the wafer, checking whether the position is accurate or not, and if the position is inaccurate, recalculating the center position.
In one embodiment, according to the size and the size of the dicing channels of each chip in the wafer, the distance between the chips, the circle center position and the feature point position of the wafer, the Map of the wafer is obtained by the following steps:
;
;
Wherein X represents the abscissa of each chip, Y represents the ordinate of each chip, The abscissa of the feature point is indicated,The ordinate representing the feature point is indicated,Indicating the lateral length of the dicing lane,Indicating the longitudinal length of the cutting lane,Representing the lateral length of the chip,Representing the longitudinal length of the chip.
In one embodiment, the method further comprises the step of adding the horizontal coordinates of the chips in the wafer to the horizontal distance between the chips, adding the vertical coordinates of the chips to the vertical distance between the chips to obtain the position coordinates of the chips, and the Map comprises the position coordinates of the chips in the wafer.
In one embodiment, the wafer is rotated according to the needle point offset angle and the Map is updated according to the needle point offset angle by horizontally sweeping the wafer, rotating the wafer by the needle point offset angle through a machine rotating mechanism, and updating the Map according to the needle point offset angle according to the formula:
;;
Wherein, Indicating the needle tip offset angle.
According to one aspect of the invention, the chip testing device comprises a horizontal scanning module, a parameter calculation module, a Map graph construction module and a chip testing module, wherein the horizontal scanning module is used for establishing a foolproof detection mechanism, horizontally scanning a wafer by using a mode of horizontally moving a camera device and the foolproof detection mechanism to obtain a horizontal wafer, the parameter calculation module is used for obtaining the circle center position and the diameter of the wafer according to the characteristic point position of the wafer, a distance calculation formula and the visual recognition function of a camera, the Map graph construction module is used for obtaining a Map graph of the wafer according to the size and the cutting path size of each chip in the wafer, the distance between the chips and the circle center position and the characteristic point position of the wafer, and the chip testing module is used for obtaining a needle point offset angle through the camera, rotating the wafer according to the needle point offset angle, updating the Map graph according to the needle point offset angle and testing the chip graph.
According to one aspect of the invention, an electronic device comprises at least one processor and at least one memory, wherein the memory stores computer readable instructions, and the computer readable instructions are executed by one or more processors to cause the electronic device to implement a chip test method as described above.
According to one aspect of the invention, a storage medium has stored thereon computer readable instructions that are executed by one or more processors to implement a chip test method as described above.
The technical scheme provided by the invention has the beneficial effects that:
According to the technical scheme, the foolproof detection mechanism is firstly established, the wafer is horizontally straightened by using the horizontal movement mode of the camera equipment and the foolproof detection mechanism, so that the horizontal wafer is obtained, the circle center position and the diameter of the wafer are obtained according to the characteristic point position, the distance calculation formula and the visual recognition function of the camera of the wafer, the Map of the wafer is obtained according to the size of each chip and the size of a cutting channel in the wafer, the distance between the chips and the circle center position and the characteristic point position of the wafer, the needle point offset angle is obtained through the camera, the wafer is rotated according to the needle point offset angle and the Map is updated according to the needle point offset angle, the chip test is performed according to the Map, the high automation and the precision calculation of the wafer detection and the positioning are realized by combining the visual recognition technology and the precision calculation, the Map of the wafer is automatically generated, the complicated process of the traditional manual mapping is greatly simplified, the accuracy and the timeliness of the data processing are improved, the accurate rotation adjustment and the dynamic update of the Map according to the offset angle are effectively realized, the automatic error of the chip due to the position offset is avoided, the fact that the automatic error of the chip alignment is low in accuracy and the accuracy of the chip alignment are not guaranteed, the existing technology is low, and the accuracy of the chip alignment is not compatible is guaranteed, and the accuracy is low.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings that are required to be used in the description of the embodiments of the present invention will be briefly described below. It is evident that the drawings in the following description are only some embodiments of the invention and that other drawings may be obtained from these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart illustrating a method of chip testing according to an exemplary embodiment;
FIG. 2 is a flow chart of a method of chip testing shown in an exemplary embodiment;
FIG. 3 is a schematic diagram illustrating a horizontal sweep in a method of testing a chip according to another exemplary embodiment;
FIG. 4 is a schematic diagram of a Map of the wafer in the embodiment of FIG. 3;
FIG. 5 is a schematic view of the angular offset of the needle tip in the corresponding embodiment of FIG. 3;
FIG. 6 is a block diagram of a chip test apparatus, according to an example embodiment;
FIG. 7 is a hardware block diagram of an electronic device shown in accordance with an exemplary embodiment;
fig. 8 is a block diagram of an electronic device, according to an example embodiment.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the invention.
As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless expressly stated otherwise, as understood by those skilled in the art. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification of this disclosure, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. The term "and/or" as used herein includes all or any element and all combination of one or more of the associated listed items.
Therefore, the invention provides a chip testing method, which combines visual recognition technology and precise calculation to realize high automation and accuracy of wafer detection and positioning, and can effectively solve the problems that the prior art cannot be compatible with chips with multiple sizes, the degree of automation is low, and the production efficiency and the accuracy are low. The chip testing method in the embodiment of the invention can be applied to various scenes, such as chip testing and the like.
Referring to fig. 1, an embodiment of the present invention provides a method for testing a chip, which is suitable for an electronic device.
In the following method embodiments, for convenience of description, the execution subject of each step of the method is described as an electronic device, but this configuration is not particularly limited.
As shown in fig. 1, the method may include the steps of:
Step 110, a foolproof detection mechanism is established, and a horizontal movement mode of the camera equipment and the foolproof detection mechanism are used for horizontally sweeping the wafer to obtain a horizontal wafer.
In one possible implementation manner, a wafer is loaded under the image pickup device through the bearing table, the position of a chip is automatically acquired through the image pickup device, the horizontal angle of the wafer is calculated and adjusted by adopting two-point continuous positioning and slope angle, verification is performed by using the fool-proof detection mechanism, and the wafer is obtained horizontally after verification is passed.
In one possible implementation, the slope angle calculation formula is:
;
The difference between the ordinate and the initial ordinate refers to the difference between the ordinate of the chip and the initial abscissa in the moving process, the difference between the abscissa and the initial abscissa of the chip in the moving process, the fool-proof detection mechanism is that if the slope angle is smaller than or equal to the set angle, horizontal sweeping is successful, and if the slope angle is larger than the set angle, horizontal sweeping is performed again.
And 130, obtaining the circle center position and the diameter of the wafer according to the characteristic point position, the distance calculation formula and the visual recognition function of the camera of the wafer.
In one possible implementation manner, a two-dimensional coordinate system is constructed by taking the characteristic points of the wafer as the origin, three edge point positions of the wafer are obtained through a distance calculation formula and a visual recognition function of a camera, the circle center position and the diameter of the wafer are obtained through calculation according to the principle that the three points are round and the three edge point positions, whether the position is accurate or not is checked according to the size and the diameter of the wafer, and if the position is inaccurate, the circle center position is recalculated.
And step 150, obtaining a Map image of the wafer according to the sizes of the chips in the wafer, the sizes of the cutting channels, the distances among the chips, the circle center positions of the wafer and the characteristic point positions.
In one possible implementation, the specific calculation formula is as follows:
;
;
Wherein X represents the abscissa of each chip, Y represents the ordinate of each chip, The abscissa of the feature point is indicated,The ordinate representing the feature point is indicated,Indicating the lateral length of the dicing lane,Indicating the longitudinal length of the cutting lane,Representing the lateral length of the chip,Representing the longitudinal length of the chip.
In one possible implementation, the abscissa of each chip in the wafer is added to the lateral distance between each chip, and the ordinate of each chip is added to the longitudinal distance between each chip to obtain the position coordinates of each chip.
The Map comprises position coordinates of each chip in the wafer.
And 170, acquiring a needle point offset angle through a camera, rotating the wafer according to the needle point offset angle, updating a Map according to the needle point offset angle, and performing chip testing according to the Map.
In one possible implementation manner, the wafer is scanned horizontally, the wafer is rotated by the needle point offset angle through the machine rotating mechanism, and the Map is updated according to the needle point offset angle by the following formula:
;
;
Wherein, Indicating the needle tip offset angle.
Through the process, the embodiment of the invention firstly establishes the foolproof detection mechanism, horizontally scans the wafer by using the horizontal moving mode of the camera equipment and the foolproof detection mechanism to obtain the horizontal wafer, obtains the circle center position and the diameter of the wafer according to the characteristic point position, the distance calculation formula and the visual recognition function of the camera of the wafer, obtains the Map of the wafer according to the size and the cutting path size of each chip in the wafer, the distance between the chips and the circle center position and the characteristic point position of the wafer, obtains the Map of the wafer by the camera, acquires the needle point offset angle, rotates the wafer according to the needle point offset angle and updates the Map according to the needle point offset angle, performs chip testing according to the visual recognition technology and precise calculation, realizes the high automation and the precision of the detection and the positioning of the wafer, greatly simplifies the complicated process of the traditional manual mapping of the wafer Map and is compatible with the chips with multiple sizes, and improves the accuracy and the timeliness of the traditional manual mapping, and the accuracy of the Map is improved, the accuracy of the wafer is adjusted precisely according to the needle point offset angle, the accuracy and the accuracy of the Map is improved, the accuracy of the chip is not high in the accuracy and the accuracy of the measurement is ensured, the accuracy and the accuracy of the chip is guaranteed, the accuracy is low, the accuracy is due to the accuracy is guaranteed, and the accuracy is low in the accuracy is due to the accuracy and the accuracy is compared.
In an exemplary embodiment, the present invention provides a chip test method for performing chip testing.
As shown in fig. 2, the method specifically includes the following steps:
in step S001, the wafer is scanned horizontally.
Specifically, the wafer is loaded to the position right below the camera through the wafer carrying platform, then the position of the chip is automatically acquired through the camera to perform wafer scanning action, and the automatic horizontal scanning of the wafer is successfully realized by adopting two points and a continuous positioning direction.
In one possible implementation manner, the leftmost chip of the wafer is taken as a first point as a reference, the wafer moves leftwards after moving rightwards in a continuous moving manner, the slope angle of the wafer is calculated through a formula in the moving process, and the level of the wafer is adjusted through multiple verification calculations until the wafer level sweeping state is reached.
Further, the chip position is obtained through repeated back and forth movement, the accuracy of the rotation angle of the chip is calculated for a plurality of times by applying a formula again, the accuracy of the wafer level is guaranteed, and a foolproof detection mechanism is established to guarantee the accuracy and the accuracy of the wafer level sweeping.
Specifically, the fool-proof detection mechanism verifies that when the angle obtained by the calculation formula is smaller than 0.0001 degrees, the wafer sweeping level is successful, when the angle obtained by the calculation formula is larger than 0.0001 degrees, the secondary verification mechanism is started, the adjustment is performed again, and after the adjustment is completed, the slope angle verification is performed by using the formula to judge whether the slope angle verification meets the requirement.
Wherein, the angle of 0.0001 degree is an open window, and the self-input definition can be carried out according to the requirement.
And S002, forming the circle center and the characteristic point positions of the wafer.
Specifically, the wafer has a special feature point (the feature point can be located at any position of the wafer) and is mainly used for positioning in the procedures of yellow light development and the like in the front-end process, and in this step, the corresponding Map of the center position of the wafer and the distribution position of each chip on the wafer is constructed by using the feature point.
The feature point can be defined as being located at any position on the wafer, a two-dimensional coordinate system is constructed on the feature point, the edge position of the wafer corresponding to the feature point can be obtained through the calculation of a related formula and the visual recognition function of the camera on the basis of the two-dimensional coordinate system, and then the actual circle center position of the wafer can be obtained according to the principle of forming a circle by three points.
In step S003, all wafer chip size Map positions are calculated.
Specifically, the correct chip position is directly calculated by combining the circle center position and the feature point position of the step S002 through the size of the wafer, the size specification of the chip on the wafer and the size of the chip cutting channel. And the Map coordinate information positions of the actual positions of all the chips can be sequentially obtained through a calculation formula.
Further, calculating the size of each wafer chip based on the feature point locations on the wafer also generates a Map showing the locations of each chip on the wafer.
Step S004, generating Map images of the wafers with multiple sizes and single sizes.
Specifically, all chip positions can be directly calculated in a single-size wafer through a formula, under a multi-size wafer, the actual positions of the chips are calculated according to the first-size chip parameters preferentially, and Map coordinate information positions of the multi-size wafer are calculated according to the distances between different sizes of the chips.
Step S005, identifying the probe seat needle point angle and identifying the needle card needle point angle.
Specifically, during multi-SITE needle card testing, needle card needle point angle detection is firstly carried out, a needle point position angle is mainly obtained through a camera, and after the needle card offset angle is obtained, a wafer is rotated to the needle card offset angle through a machine platform Chuck disc rotating mechanism.
Further, since a certain deviation value exists in the position of the chip after rotation, the Map position of the chip needs to be calculated again to obtain the actual pricking position of the chip when the multi-SITE card test is performed.
Step S006, wafer Map mapping.
Specifically, map calculation of the wafer is performed by using unique characteristic point positions of the wafer, and the characteristic points are used as origin positions of the wafer, so that chip position calculation is performed in four directions, the actual positions of each chip can be obtained by taking a two-dimensional coordinate system as a reference, and finally Map calculation of the whole wafer chip and actual chip binding position calculation after the rotation angle of the needle card needle point is increased are completed, so that Map positions of the wafer chip are obtained.
Through the process, the efficiency and the precision of wafer testing are remarkably improved, the Map testing of chips with multiple sizes can be compatible, chips with all sizes are successfully integrated in the same Map through an algorithm formula, so that Map building time is greatly shortened, operation speed and productivity are improved, meanwhile, abnormal rate during Map building manually is reduced, automatic generation of Map diagrams is realized through the algorithm formula, the risk of manual intervention is greatly reduced in one-to-one correspondence with the wafer chips, in the process of automatically generating Map diagrams through the algorithm, the angle difference value of needle points of the needle cards can be detected in advance, the difference value is synchronously implanted into the Map diagrams, and in the process of testing, the system can automatically adjust the pricking and testing positions according to position information in the Map, so that the height consistency of pricking and testing needle marks is ensured, and the accuracy and the reliability of testing are improved.
In another exemplary embodiment, the present invention provides a chip test method for performing a chip test.
As shown in fig. 3, the wafer scanning operation is performed by automatically acquiring the positions of the chips by the camera. The automatic wafer scanning and leveling are realized by adopting two points and continuously positioned directions, and the moving process comprises the following steps:
;
Calculating the slope angle of the wafer, adjusting the wafer level through multiple verification calculation of the wafer, and establishing a foolproof detection mechanism to ensure the accuracy and precision of wafer sweeping. The fool-proof detection mechanism verifies that:
And (3) verifying a formula: ;
and when the angle obtained by the calculation formula is smaller than 0.0001 degree, the wafer sweeping level is successful, and when the angle obtained by the calculation formula is larger than 0.0001 degree, a secondary verification mechanism is started at the moment, the horizontal angle is finely adjusted again, and after the adjustment is completed, the slope angle is verified by using the formula to meet the requirement.
As shown in FIG. 4, each wafer has a special feature point, and the feature point position is used to construct a Map corresponding to the center position of the wafer and the distribution position of each chip on the wafer, where the feature point can be defined asThe characteristic point can be positioned at any position on the wafer, a two-dimensional coordinate system is constructed on the characteristic point, the position of the characteristic point can be calculated through a related formula and the visual recognition function of a camera to obtain the edge position of the wafer corresponding to the characteristic point, and then the actual circle center position of the wafer can be obtained according to the three-point circle forming principle。
Horizontal distance:;
Vertical distance: ;
The three edge point positions of the wafer can be calculated through the formula, and the circle center position of the wafer and the position of the characteristic point corresponding to the circle center can be directly calculated through the principle that the three points form the circle, so that the circle center and the characteristic point of the Map are calculated.
At the characteristic pointIn positions respectively to the leftIn the right directionAnd upward directionThree edge positions are set, and characteristic points are locatedMust be atIn this way, the center coordinates are derived by the formula of rounding three pointsAnd diameter d of the wafer, and according to the size specification of the wafer, for example, the diameter of an 8-inch wafer isThe test method for determining whether the wafer diameter corresponds to the wafer diameter of the actual size, which is derived by the formula, is as follows:
the distance between the two points of the circle center position and the right direction position is as follows: The diameter of the circle is When (when)Or (b)When the center position is inaccurate, the center position is deduced again by the formula, such as whenThe center position is accurate during this time.
Further, chip size X: Chip size Y: . Chip dicing street size X: chip dicing lane size Y: 。
the horizontal direction calculation formula: ;
the vertical direction calculation formula: ;
And the Map coordinate information positions of the actual positions of all the chips can be obtained sequentially through calculation according to the calculation formula, compared with the prior art, the Map establishing step is subtracted manually, and the working efficiency and the accuracy are improved.
Further, the positions of all chips can be directly calculated in a single-size wafer by the above formula, if the wafer is under a multi-size wafer, the actual position is calculated according to the first size chip parameter, and then the distance between different sizes is calculated,And obtaining the coordinates of all the chips with the dimensions, wherein the calculation formula is as follows:
the horizontal direction calculation formula: ;
the vertical direction calculation formula: ;
Therefore, map coordinate information positions of the wafers with multiple sizes are calculated, compared with the prior art, the prior art can only be compatible with the chip sizes with single sizes, and compared with the scheme, the Map coordinate information positions of the wafers with multiple sizes can be compatible with the chip sizes with multiple sizes, and the Map coordinate information positions of the wafers with multiple sizes are high in compatibility.
As shown in FIG. 5, during the multi-SITE card test, the angle of the needle tip of the card is detected first, and the position of the needle tip is obtained mainly by a camera to obtain the offset angle of the cardThen, the wafer rotation offset angle is carried out by a machine platform Chuck disk rotation mechanismAnd the wafer is cleaned horizontally before rotating, and then the wafer is rotated。
Further, since a certain deviation value exists in the position of the chip after rotation, the Map position of the chip needs to be calculated again, and the actual position of the chip after the rotation of the needle point angle is calculated mainly by the following formula:
The angle calculation formula θ: ;
after the rotation angle, the calculation formula of the deviation distance of the chip X direction is as follows: ;
after the rotation angle, the calculation formula of the deviation distance of the chip X direction is as follows: ;
finally, the actual pricking position of the chip when the multi-SITE pin card test is performed is obtained according to the following formula:
X direction: ;
Y direction: ;
Compared with the prior art, the proposal can realize automatic adjustment of the angle position of the needle card and automatically calculate the Map coordinate of the actual needle insertion position of each chip, thereby reducing the manual difference when the angle position of the needle card is manually adjusted and improving the automation degree of the machine.
Further, wafer Map estimation is performed using unique feature point positions unique to the wafer, and chip position estimation is performed in four directions using the feature points as the wafer origin positions.
Based on a two-dimensional coordinate system, the estimation mode is as follows:
The X positive direction is: .....;
The X positive direction is: .....;
the X negative direction is: .....;
the X negative direction is: .....。
the negative direction is mainly from the reverse movement of the origin, can be negative, the actual position can be positive, n represents the number of chips, thus the actual position of each chip can be obtained as ,) And finally, map calculation of the whole wafer chip and actual chip pricking position calculation after the rotation angle of the needle point of the needle card is increased are completed, so that Map positions of the wafer chip are obtained.
Through the process, the embodiment of the invention utilizes the camera equipment to horizontally move and scan the wafer, so that the detection coverage and efficiency are greatly improved, and the comprehensiveness and accuracy of the image data acquisition of the wafer are ensured. Through the application of the characteristic point position and the distance calculation formula, the circle center position and the diameter of the wafer can be accurately measured, a solid foundation is laid for subsequent operation, and a wafer Map is automatically generated according to the sizes of each chip and the cutting path on the wafer and the distance between the chips and the cutting path and by combining the circle center and the characteristic point position information, so that the complicated process of traditional manual mapping is greatly simplified, and the accuracy and timeliness of data processing are improved. In addition, the probe tip offset angle is captured in real time through the camera, and the wafer is accurately rotated and adjusted and the Map is dynamically updated according to the probe tip offset angle, so that the test error caused by position deviation is effectively avoided, the accurate alignment of chip test is ensured, the test flow is optimized, and the reliability and the yield of the wafer test are obviously improved.
The following is an embodiment of the device of the present invention, which may be used to perform a chip testing method according to the present invention. For details not disclosed in the device embodiments of the present invention, please refer to a method embodiment of a chip testing method according to the present invention.
Referring to fig. 6, a chip testing apparatus 800 is provided in an embodiment of the invention.
The apparatus 800 includes, but is not limited to, a horizontal swipe module 810, a parameter calculation module 830, a Map graph construction module 850, and a chip test module 870.
The horizontal sweeping module 810 is configured to establish a foolproof detection mechanism, and use a horizontal movement mode of the camera device and the foolproof detection mechanism to sweep the wafer horizontally to obtain a horizontal wafer.
And the parameter calculation module 830 is configured to obtain a center position and a diameter of the wafer according to the feature point position, the distance calculation formula, and the visual recognition function of the camera.
The Map construction module 850 is configured to obtain a Map of the wafer according to the sizes of the chips and the dicing streets in the wafer, the distances between the chips, the circle center position and the feature point position of the wafer.
The chip testing module 870 is configured to obtain a needle point offset angle through the camera, rotate the wafer according to the needle point offset angle, update a Map according to the needle point offset angle, and perform a chip test according to the Map.
It should be noted that, in the chip test provided in the above embodiment, only the division of the above functional modules is used as an example, and in practical application, the above functional allocation may be performed by different functional modules according to needs, that is, the internal structure of the chip test device may be divided into different functional modules to perform all or part of the functions described above.
In addition, the chip testing apparatus provided in the above embodiment and the embodiment of a chip testing method belong to the same concept, and the specific manner in which each module performs the operation has been described in detail in the method embodiment, which is not described herein again.
Fig. 7 shows a schematic structure of an electronic device according to an exemplary embodiment.
It should be noted that the electronic device is only an example adapted to the present invention, and should not be construed as providing any limitation on the scope of use of the present invention. Nor should the electronic device be construed as necessarily relying on or necessarily having one or more of the components of the exemplary electronic device 2000 illustrated in fig. 7.
The hardware configuration of the electronic device 2000 may vary widely depending on configuration or performance, as shown in fig. 7, the electronic device 2000 includes a power supply 210, an interface 230, at least one memory 250, and at least one central processing unit (CPU, central Processing Units) 270.
Specifically, the power supply 210 is configured to provide an operating voltage for each hardware device on the electronic device 2000.
The interface 230 includes at least one wired or wireless network interface 231 for interacting with external devices. Of course, in other examples of the adaptation of the present invention, the interface 230 may further include at least one serial-parallel conversion interface 233, at least one input-output interface 235, at least one USB interface 237, and the like, as shown in fig. 7, which is not particularly limited herein.
The memory 250 may be a carrier for storing resources, such as a read-only memory, a random access memory, a magnetic disk, or an optical disk, where the resources stored include an operating system 251, application programs 253, and data 255, and the storage mode may be transient storage or permanent storage.
The operating system 251 is used for managing and controlling various hardware devices and applications 253 on the electronic device 2000, so as to implement the operation and processing of the cpu 270 on the mass data 255 in the memory 250, which may be Windows server, mac OS XTM, unixTM, linuxTM, freeBSDTM, etc.
The application 253 is based on computer readable instructions on the operating system 251 to perform at least one specific task, which may include at least one module (not shown in fig. 7), each of which may include computer readable instructions for the electronic device 2000, respectively. For example, the chip test apparatus may be regarded as an application 253 deployed on the electronic device 2000.
The data 255 may be signal information or the like, and is stored in the memory 250.
The central processor 270 may include one or more of the above processors and is configured to communicate with the memory 250 via at least one communication bus to read computer readable instructions stored in the memory 250, thereby implementing operations and processing of the bulk data 255 in the memory 250. For example, a chip test method is accomplished by the central processor 270 reading a series of computer readable instructions stored in the memory 250.
Furthermore, the present invention can be realized by hardware circuitry or by a combination of hardware circuitry and software, and thus, the implementation of the present invention is not limited to any specific hardware circuitry, software, or combination of the two.
Referring to fig. 8, an electronic device 4000 is provided in an embodiment of the present invention, and the electronic device 400 may include a desktop computer, a notebook computer, a server, etc. having sensor recognition capability.
In fig. 8, the electronic device 4000 includes at least one processor 4001 and at least one memory 4003.
Among other things, data interaction between the processor 4001 and the memory 4003 may be achieved by at least one communication bus 4002. The communication bus 4002 may include a path for transferring data between the processor 4001 and the memory 4003. The communication bus 4002 may be a PCI (PERIPHERAL COMPONENT INTERCONNECT, peripheral component interconnect standard) bus or an EISA (Extended Industry Standard Architecture ) bus or the like. The communication bus 4002 can be divided into an address bus, a data bus, a control bus, and the like. For ease of illustration, only one thick line is shown in fig. 8, but not only one bus or one type of bus.
Optionally, the electronic device 4000 may further comprise a transceiver 4004, the transceiver 4004 may be used for data interaction between the electronic device and other electronic devices, such as transmission of data and/or reception of data, etc. It should be noted that, in practical applications, the transceiver 4004 is not limited to one, and the structure of the electronic device 4000 is not limited to the embodiment of the present invention.
The Processor 4001 may be a CPU (Central Processing Unit ), general purpose Processor, DSP (DIGITAL SIGNAL Processor, data signal Processor), ASIC (Application SPECIFIC INTEGRATED Circuit), FPGA (Field Programmable GATE ARRAY ) or other programmable logic device, transistor logic device, hardware component, or any combination thereof. Which may implement or perform the various exemplary logic blocks, modules and circuits described in connection with this disclosure. The processor 4001 may also be a combination that implements computing functionality, e.g., comprising one or more microprocessor combinations, a combination of a DSP and a microprocessor, etc.
Memory 4003 may be, but is not limited to, ROM (Read Only Memory) or other type of static storage device that can store static information and instructions, RAM (Random Access Memory ) or other type of dynamic storage device that can store information and instructions, EEPROM (ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY ), CD-ROM (Compact Disc Read Only Memory, compact disc Read Only Memory) or other optical disk storage, optical disk storage (including compact discs, laser discs, optical discs, digital versatile discs, blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store desired program instructions or code in the form of instructions or data structures and that can be accessed by electronic device 400.
The memory 4003 has computer readable instructions stored thereon, and the processor 4001 can read the computer readable instructions stored in the memory 4003 through the communication bus 4002.
The computer readable instructions are executed by the one or more processors 4001 to implement a method of chip testing in the various embodiments described above.
Furthermore, in an embodiment of the present invention, a storage medium having stored thereon computer readable instructions that are executed by one or more processors to implement a chip test method as described above is provided.
In an embodiment of the present invention, a computer program product is provided, the computer program product including computer readable instructions stored in a storage medium, one or more processors of an electronic device reading the computer readable instructions from the storage medium, loading and executing the computer readable instructions, causing the electronic device to implement a chip test method as described above.
Compared with the related art, the invention has the beneficial effects that:
1. According to the invention, a foolproof detection mechanism is firstly established, a horizontal movement mode of a camera device and the foolproof detection mechanism are used for horizontally sweeping the wafer to obtain a horizontal wafer, the circle center position and the diameter of the wafer are obtained according to the characteristic point position and the distance calculation formula of the wafer and the visual recognition function of a camera, the Map of the wafer is obtained according to the size and the cutting path size of each chip in the wafer, the distance between the chips and the circle center position and the characteristic point position of the wafer, the needle point offset angle is obtained through the camera, the wafer is rotated according to the needle point offset angle and the Map is updated according to the needle point offset angle, the chip test is performed according to the Map, the high automation and the precision of the wafer detection and the positioning are realized by combining the visual recognition technology and the precision calculation, the Map of the wafer can be automatically generated, the complicated process of the traditional manual mapping is greatly simplified, the accuracy and the timeliness of data processing are improved, the accurate rotation adjustment and the dynamic updating of the Map of the wafer are effectively avoided according to the needle point offset angle, the test error caused by the position deviation is effectively avoided, the chip test error due to the accuracy and the low production accuracy and the accuracy of the chip size are effectively ensured, the problem is not compatible, and the existing technology is low is solved, and the accuracy is low is compatible.
2. The Map testing method can be compatible with the Map testing of the chips with multiple sizes, and the chips with all sizes are all generated in the same Map through an algorithm formula, so that the Map establishing time is greatly shortened, the operation speed and the productivity are improved, and the abnormal rate when the Map is manually established is reduced.
3. The automatic Map generation method has the advantages that the Map can be automatically generated according to a related algorithm formula, the Map can be in one-to-one correspondence with chips on the wafer, the risk of manual intervention is reduced, the automation level of testing is improved, the needle mark detection precision is high, when the Map is automatically generated, the angle difference value of the needle point of the needle card is detected in advance, and the generated angle difference value is synchronously implanted into the Map, so that the high consistency of the needle point pricking position in the testing process is ensured, and the testing accuracy is improved.
4. The invention can improve the test efficiency, save time and labor cost, improve the overall test efficiency, reduce test errors caused by manual operation due to high degree of automation and high precision of needle mark detection, improve the test reliability, support multi-SITE test, and ensure the accuracy of multi-SITE test by including a needle point angle detection and adjustment mechanism for the multi-SITE needle card test.
5. The invention has wide application field, and is suitable for all semiconductor manufacturing enterprises needing wafer test, no matter what size and type of chips are produced.
It should be understood that, although the steps in the flowcharts of the figures are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited in order and may be performed in other orders, unless explicitly stated herein. Moreover, at least some of the steps in the flowcharts of the figures may include a plurality of sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, the order of their execution not necessarily being sequential, but may be performed in turn or alternately with other steps or at least a portion of the other steps or stages.
The foregoing is only a partial embodiment of the present invention, and it should be noted that it will be apparent to those skilled in the art that modifications and adaptations can be made without departing from the principles of the present invention, and such modifications and adaptations are intended to be comprehended within the scope of the present invention.
Claims (10)
1. A method of testing a chip, the method comprising:
Establishing a fool-proof detection mechanism, and horizontally sweeping the wafer by using a horizontal movement mode of the camera equipment and the fool-proof detection mechanism to obtain a horizontal wafer;
obtaining the circle center position and the diameter of the wafer according to the characteristic point position, the distance calculation formula and the visual recognition function of the camera of the wafer;
Obtaining a Map image of the wafer according to the sizes of chips and cutting channels in the wafer, the distance between the chips, the circle center position and the characteristic point position of the wafer;
And acquiring a needle point offset angle through a camera, rotating the wafer according to the needle point offset angle, updating the Map according to the needle point offset angle, and performing chip test according to the Map.
2. The method for testing a chip according to claim 1, wherein the horizontally sweeping the wafer using the horizontal movement of the camera device and the fool-proof detection mechanism to obtain the horizontal wafer comprises:
And loading the wafer under the image pickup equipment through the bearing table, automatically acquiring the position of the chip through the image pickup equipment, calculating and adjusting the horizontal angle of the wafer by adopting two-point continuous positioning and slope angle, and verifying by using the fool-proof detection mechanism, wherein the horizontal wafer is obtained after verification.
3. The chip testing method of claim 2, wherein the slope angle calculation formula is:
;
The difference between the ordinate and the initial ordinate refers to the difference between the abscissa and the initial abscissa of the chip in the moving process;
The fool-proof detection mechanism is used for carrying out horizontal sweeping successfully if the slope angle is smaller than or equal to a set angle, and carrying out horizontal sweeping again if the slope angle is larger than the set angle.
4. The method for testing a chip according to claim 1, wherein obtaining the center position and diameter of the wafer according to the feature point position, the distance calculation formula and the visual recognition function of the camera comprises:
constructing a two-dimensional coordinate system by taking the characteristic points of the wafer as the original points, and obtaining three edge point positions of the wafer through a distance calculation formula and a visual recognition function of a camera;
calculating the circle center position and the diameter of the wafer according to the principle of rounding three points and the positions of the three edge points;
And checking whether the position is accurate according to the size and the diameter of the wafer, and if the position is inaccurate, recalculating the circle center position.
5. The method for testing chips as defined in claim 1, wherein said obtaining Map of said wafer according to the sizes of chips and dicing streets in said wafer, the distances between said chips, and the positions of the center of circle and the positions of the feature points of said wafer comprises:
the specific calculation formula is as follows:
;
;
Wherein X represents the abscissa of each chip, Y represents the ordinate of each chip, The abscissa of the feature point is indicated,The ordinate representing the feature point is indicated,Indicating the lateral length of the dicing lane,Indicating the longitudinal length of the cutting lane,Representing the lateral length of the chip,Representing the longitudinal length of the chip.
6. The chip testing method of claim 5, wherein the method further comprises:
And adding the horizontal coordinates of the chips in the wafer with the horizontal distance between the chips, adding the vertical coordinates of the chips with the longitudinal distance between the chips to obtain the position coordinates of the chips, wherein the Map comprises the position coordinates of the chips in the wafer.
7. The method of claim 1, wherein rotating the wafer according to the tip-offset angle and updating the Map according to the tip-offset angle comprises:
The wafer is horizontally swept, the wafer is rotated by the needle point offset angle through a machine rotating mechanism, and the Map is updated according to the needle point offset angle by the following formula:
;
;
Wherein, Indicating the needle tip offset angle.
8. A chip testing apparatus, the apparatus comprising:
The horizontal sweeping module is used for establishing a foolproof detection mechanism, and horizontally sweeping the wafer by using a mode of horizontally moving the camera equipment and the foolproof detection mechanism to obtain a horizontal wafer;
the parameter calculation module is used for obtaining the circle center position and the diameter of the wafer according to the characteristic point position, the distance calculation formula and the visual recognition function of the camera of the wafer;
The Map image construction module is used for obtaining a Map image of the wafer according to the sizes of chips and cutting channels in the wafer, the distance between the chips, the circle center position and the feature point position of the wafer;
And the chip testing module is used for acquiring a needle point offset angle through a camera, rotating the wafer according to the needle point offset angle, updating the Map according to the needle point offset angle, and carrying out chip testing according to the Map.
9. An electronic device comprising at least one processor and at least one memory, wherein,
The memory has computer readable instructions stored thereon;
The computer readable instructions are executed by one or more of the processors to cause an electronic device to implement a chip testing method as claimed in any one of claims 1 to 7.
10. A storage medium having stored thereon computer readable instructions, wherein the computer readable instructions are executed by one or more processors to implement a chip test method as claimed in any one of claims 1 to 7.
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