CN119199484B - Fault sensitivity calculation method based on voltage glitch - Google Patents
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Abstract
本申请适用于芯片测试技术领域，尤其涉及一种基于电压毛刺的故障灵敏度计算方法，该方法包括：通过获取安全芯片的参数扫描信息，并基于参数扫描信息确定安全芯片的多个电压毛刺参数组合，提高测试效率和覆盖率；依据安全芯片的每个电压毛刺参数组合，控制毛刺注入装置对安全芯片进行毛刺注入，得到每个电压毛刺参数组合对应的故障发生次数，确保测试结果的精确性和可重复性；基于每个电压毛刺参数组合对应的故障发生次数，确定每个电压毛刺参数组合对应的故障灵敏度；根据每个电压毛刺参数组合对应的故障灵敏度，确定安全芯片的测试结果，快速识别出芯片易受攻击的参数组合和条件，为芯片设计优化和防护改进提供明确指导和数据支持。
The present application is applicable to the field of chip testing technology, and in particular to a method for calculating fault sensitivity based on voltage glitches, the method comprising: obtaining parameter scanning information of a security chip, and determining multiple voltage glitches parameter combinations of the security chip based on the parameter scanning information, so as to improve test efficiency and coverage; controlling a glitch injection device to inject glitches into the security chip according to each voltage glitches parameter combination of the security chip, and obtaining the number of fault occurrences corresponding to each voltage glitches parameter combination, so as to ensure the accuracy and repeatability of the test results; determining the fault sensitivity corresponding to each voltage glitches parameter combination based on the number of fault occurrences corresponding to each voltage glitches parameter combination; determining the test result of the security chip according to the fault sensitivity corresponding to each voltage glitches parameter combination, quickly identifying the parameter combinations and conditions under which the chip is vulnerable to attack, and providing clear guidance and data support for chip design optimization and protection improvement.
Description
Technical Field
The application belongs to the technical field of chip testing, and particularly relates to a fault sensitivity calculation method based on voltage burrs.
Background
With the increasing demand for information security, integrated circuits and security chips are widely used in various applications, such as smart cards, payment terminals, encryption devices, etc. However, these security chips face different types of physical attack threats, with voltage glitch (Voltage Fault Injection, VFI) attacks being a common fault injection attack approach. An attacker can briefly apply burrs to the power supply voltage of the chip during the working process of the chip to disturb the normal working of the chip, so as to try to cause the chip to produce error output or leak sensitive information during the execution process. The fault injection test based on the voltage burrs can help a design team to identify and improve potential weaknesses in design, and the anti-interference capability of the chip is improved by means of optimizing circuit layout, adding protection measures and the like.
The existing chip test method needs a large amount of test time and resources to cover all possible attack parameters, cannot meet the requirement of large-scale chip security evaluation, and lacks a systematic method to evaluate the comprehensive anti-attack capability of the chip under different voltage burrs, so that the most sensitive point of the chip is difficult to find in a limited test time, and the test efficiency is low, pertinence is lacking, and the test repeatability is poor.
Disclosure of Invention
The embodiment of the application provides a fault sensitivity calculation method based on voltage burrs, which can solve the problems of low test efficiency, lack of pertinence and poor test repeatability in the prior art because a large amount of test time and resources are required to cover all possible attack parameters.
In a first aspect, an embodiment of the present application provides a fault sensitivity calculation method based on voltage glitches, including:
acquiring parameter scanning information of a safety chip, and determining a plurality of voltage burr parameter combinations of the safety chip based on the parameter scanning information, wherein the parameter scanning information is a related parameter of preliminary voltage burrs obtained according to a voltage burr fault injection result;
Controlling a burr injection device to perform burr injection on the safety chip according to each voltage burr parameter combination of the safety chip to obtain the fault occurrence times corresponding to each voltage burr parameter combination;
Determining fault sensitivity corresponding to each voltage burr parameter combination based on the fault occurrence times corresponding to each voltage burr parameter combination;
And determining a test result of the safety chip according to the fault sensitivity corresponding to each voltage burr parameter combination.
The technical scheme provided by the embodiment of the application at least has the following technical effects:
According to the fault sensitivity calculation method based on the voltage glitches, provided by the embodiment of the application, the parameter scanning information of the safety chip is obtained, and the combination of a plurality of voltage glitches of the safety chip is determined based on the parameter scanning information, so that all possible glitch conditions are ensured to be covered in a limited time, and the test efficiency and the coverage rate are improved. And controlling the burr injection device to perform burr injection on the safety chip according to each voltage burr parameter combination of the safety chip to obtain the fault occurrence times corresponding to each voltage burr parameter combination, so as to ensure the accuracy and the repeatability of the test result. And determining the fault sensitivity corresponding to each voltage burr parameter combination based on the fault occurrence times corresponding to each voltage burr parameter combination. According to the fault sensitivity corresponding to each voltage burr parameter combination, the test result of the safety chip is determined, the parameter combination and the condition of the chip which is most vulnerable to attack are rapidly identified, the test efficiency is improved, the test repeatability and pertinence are enhanced, and clear guidance and data support are provided for chip design optimization and protection measure improvement.
In a second aspect, an embodiment of the present application provides a fault sensitivity calculation system based on voltage glitch, including:
The device comprises an acquisition unit, a detection unit and a control unit, wherein the acquisition unit is used for acquiring parameter scanning information of a safety chip and determining a plurality of voltage burr parameter combinations of the safety chip based on the parameter scanning information, wherein the parameter scanning information is related parameters of preliminary voltage burrs obtained according to the voltage burr fault injection result;
The injection unit is used for controlling the burr injection device to perform burr injection on the safety chip according to each voltage burr parameter combination of the safety chip to obtain the fault occurrence times corresponding to each voltage burr parameter combination;
the analysis unit is used for determining fault sensitivity corresponding to each voltage burr parameter combination based on the fault occurrence times corresponding to each voltage burr parameter combination;
and the result unit is used for determining the test result of the safety chip according to the fault sensitivity corresponding to each voltage burr parameter combination.
In a third aspect, an embodiment of the present application provides a fault sensitivity calculation device based on voltage glitches, including a memory, a processor and a computer program stored in the memory and executable on the processor, the processor implementing the method according to any of the preceding aspects when executing the computer program.
In a fourth aspect, embodiments of the present application provide a computer program product for, when run on a terminal device, causing the terminal device to perform the method of any of the above aspects.
It will be appreciated that the advantages of the second to fourth aspects may be seen from the relevant description of the above aspects, and will not be repeated here.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments or the description of the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic flow chart of a fault sensitivity calculation method based on voltage glitches according to an embodiment of the application;
FIG. 2 is a schematic diagram of an operation flow of a fault sensitivity calculation method based on voltage glitches according to an embodiment of the application;
FIG. 3 is a schematic diagram of a hardware acquisition device according to a fault sensitivity calculation method based on voltage glitches according to an embodiment of the present application;
FIG. 4 is a diagram showing the operation of steps in a fault sensitivity calculation method based on voltage glitches according to an embodiment of the present application;
FIG. 5 is a diagram showing the operation of steps in a fault sensitivity calculation method based on voltage glitches according to an embodiment of the present application;
FIG. 6 is a diagram showing the operation of steps in a fault sensitivity calculation method based on voltage glitches according to an embodiment of the present application;
FIG. 7 is a schematic diagram of a fault sensitivity calculation system based on voltage glitches according to an embodiment of the application;
Fig. 8 is a schematic structural diagram of a fault sensitivity calculating device based on voltage glitch according to an embodiment of the present application.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, techniques, etc., in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It should also be understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
As used in the present description and the appended claims, the term "if" may be interpreted as "when..once" or "in response to a determination" or "in response to detection" depending on the context. Similarly, the phrase "if a condition or event is determined" or "if a condition or event is detected" may be interpreted in the context to mean "upon determination" or "in response to determination" or "upon detection of a condition or event, or" in response to detection of a condition or event.
Furthermore, the terms "first," "second," "third," and the like in the description of the present specification and in the appended claims, are used for distinguishing between descriptions and not necessarily for indicating or implying a relative importance.
Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.
The existing chip test method needs a large amount of test time and resources to cover all possible attack parameters, cannot meet the requirement of large-scale chip security evaluation, and lacks a systematic method to evaluate the comprehensive anti-attack capability of the chip under different voltage burrs, so that the most sensitive point of the chip is difficult to find in a limited test time, and the test efficiency is low, pertinence is lacking, and the test repeatability is poor.
In order to solve the problems, the embodiment of the application provides a fault sensitivity calculation method based on voltage burrs. According to the method, the parameter scanning information of the safety chip is obtained, the combination of multiple voltage burr parameters of the safety chip is determined based on the parameter scanning information, all possible burr conditions are ensured to be covered in a limited time, and the testing efficiency and the coverage rate are improved. And controlling the burr injection device to perform burr injection on the safety chip according to each voltage burr parameter combination of the safety chip to obtain the fault occurrence times corresponding to each voltage burr parameter combination, so as to ensure the accuracy and the repeatability of the test result. And determining the fault sensitivity corresponding to each voltage burr parameter combination based on the fault occurrence times corresponding to each voltage burr parameter combination. According to the fault sensitivity corresponding to each voltage burr parameter combination, the test result of the safety chip is determined, the parameter combination and the condition of the chip which is most vulnerable to attack are rapidly identified, the test efficiency is improved, the test repeatability and pertinence are enhanced, and clear guidance and data support are provided for chip design optimization and protection measure improvement.
The fault sensitivity calculating method based on the voltage glitch provided by the embodiment of the application can be applied to the fault sensitivity calculating device based on the voltage glitch, and the fault sensitivity calculating device based on the voltage glitch is the execution main body of the fault sensitivity calculating method based on the voltage glitch provided by the embodiment of the application, and the embodiment of the application does not limit the specific type of the terminal device.
For example, the voltage glitch-based fault sensitivity computing device may include a processor, a communication device (e.g., serial interface, parallel interface, USB), a network device, a hardware acquisition device (e.g., oscilloscope, digital-to-analog converter, sensor), a glitch injection device (e.g., signal generator, pulse generator, coupled network), a memory, and so forth.
In order to better understand the fault sensitivity calculation method based on the voltage spike provided by the embodiment of the application, the specific implementation process of the fault sensitivity calculation method based on the voltage spike provided by the embodiment of the application is described in an exemplary manner.
Fig. 1 shows a schematic flow chart of a fault sensitivity calculation method based on voltage glitches, provided by an embodiment of the present application, and fig. 2 shows an operation flow chart of a fault sensitivity calculation method based on voltage glitches, provided by an embodiment of the present application, the fault sensitivity calculation method based on voltage glitches includes:
s100, acquiring parameter scanning information of the safety chip, and determining a plurality of voltage burr parameter combinations of the safety chip based on the parameter scanning information, wherein the parameter scanning information is related parameters of preliminary voltage burrs obtained according to voltage burr fault injection results.
It can be understood that the parameter scanning information refers to a series of data obtained by monitoring the operation states of the security chip under different working conditions in real time, and may be related parameters of the preliminary voltage glitch obtained according to the result of the voltage glitch fault injection. The parameter scan information may include parameters such as supply voltage, clock frequency, operating temperature, current consumption, and signal integrity. The parameter scanning information can be acquired by using test equipment such as an oscilloscope, a logic analyzer and the like, combining special software and hardware interfaces (such as JTAG and SPI), and acquiring the acquired data in a USB or network connection mode. Based on the collected parameter scan information, certain algorithmic signal processing algorithms (e.g., fourier transforms or wavelet transforms) may be applied to identify parameter feature data for the voltage spike that will serve as a basis for subsequent voltage spike parameter combinations. For example, applying a fourier transform may transform a time domain signal into a mathematical tool of frequency domain representation, and frequency components of the signal may be revealed to identify the most representative voltage spike features, generating all possible voltage spike parameter combinations, facilitating subsequent analysis and testing.
In one possible implementation, S100, acquiring parameter scan information of the security chip, and determining a plurality of voltage glitch parameter combinations of the security chip based on the parameter scan information includes:
s110, acquiring parameter scanning information of the security chip, and determining parameter characteristic data of the security chip based on the parameter scanning information.
It is understood that the parameter scan information may include parameters such as supply voltage, clock frequency, operating temperature, current consumption, and signal integrity. The parameter scanning information can be acquired by using hardware data acquisition equipment (refer to fig. 3) such as an oscilloscope, a logic analyzer and the like, combining special software and hardware interfaces (such as JTAG and SPI) to acquire the parameter scanning information in a USB or network connection mode. The parameter characteristic data, which refers to information describing statistical properties of the data set, may be derived from the parameter scan information. For example, a signal processing algorithm (such as a fourier transform or wavelet transform) may be used to analyze the frequency domain representation of the time domain signal. Fourier transform is a mathematical tool that converts a time domain signal into a frequency domain representation, revealing the frequency content of the signal. After extracting the parameter feature data, feature vectors can be constructed to capture statistical properties of parameters, such as mean, standard deviation, peak factors, and the like. The parameter characteristic data form a parameter characteristic data set, which is favorable for determining the performance of the security chip and lays a foundation for subsequent analysis.
S120, dividing a burr parameter level for the security chip based on the parameter characteristic data of the security chip to obtain a plurality of burr parameter layers.
It is appreciated that hierarchical cluster analysis (HIERARCHICAL CLUSTERING ANALYSIS) may be applied to the extracted parametric feature data to rank the parametric feature data. Hierarchical clustering is a method of grouping data by constructing a tree structure. In this process, an appropriate distance measure (e.g., euclidean distance) may be selected to calculate the similarity between the data points, and the data points are gradually combined in a bottom-up manner. Each level represents a group of similar voltage burr features, the burr parameter levels are beneficial to the subsequent voltage parameter combination construction, and a tree structure is formed so that different parameter levels can be conveniently selected for testing.
Optionally, S120, dividing the burr parameter level for the security chip based on the parameter feature data of the security chip, to obtain a plurality of burr parameter layers, including:
s121, parameter characteristic information of various parameters of the security chip is determined based on the parameter characteristic data of the security chip.
It can be appreciated that the parameter feature data can be directly extracted for analysis to determine parameter feature information of various parameters related to the security chip. The parameter characteristic information may include:
mean, standard deviation, description of mean and fluctuation of each parameter during the test
Distribution characteristics of parameters (e.g. normal distribution, biased distribution, etc.)
Outlier analysis-identifying and analyzing outlier parameter values to determine possible faults or outlier conditions.
S122, dividing a burr parameter level for each parameter of the security chip according to the parameter characteristic information of each parameter to obtain a plurality of burr initial parameter layers corresponding to each parameter.
It is understood that the mapping relationship between the scan parameters and the spur parameters may be established in advance. The mapping relation between the scanning parameters and the burr parameters can be realized through experimental data analysis and statistical modeling. For example, a formula or function is set that maps a particular scan parameter (e.g., voltage amplitude) to a corresponding spur parameter (e.g., spur amplitude and width). Based on the parameter characteristic information of various parameters of the security chip, corresponding burr parameters can be obtained through mapping by a mapping relation, and the burr parameters can be grouped by using a clustering algorithm (such as K-means or hierarchical clustering). The clustering algorithm classifies similar spike parameters into one class and forms a plurality of initial parameter layers through mapping. According to the parameter characteristic information of each level, the boundary of the burr parameter layer can be determined by a mode of presetting a mapping relation. The boundaries of the spur parameter layers may be preset based on historical data or experimental results, ensuring that each level is capable of representing a particular voltage spur behavior. For example, for the voltage amplitude, it may be classified into "low voltage (0V-1V)", "medium voltage (1V-3V)", and "high voltage (3V-5V)" stages according to different voltage values, and for the width, it may be classified into "short width (1 μs-10 μs)", "medium width (10 μs-50 μs)" and "long width (50 μs-100 μs)" stages, and the application timing may be classified into "early application", "medium application", and "late application" stages according to their changing points with respect to the signal. That is, each parameter has multiple parameter levels, each parameter level being a glitch initial parameter level.
S123, summarizing a plurality of burr initial parameter layers corresponding to all parameters to obtain a plurality of burr parameter layers, wherein the burr parameter layers comprise burr initial parameter layers with at least two parameters.
It will be appreciated that the initial parameter layers that can be extracted from each parameter (e.g., voltage amplitude, width, and time of application) will be integrated. These initial parameter layers are defined based on the respective parameter profile data and represent the voltage spike behavior in different situations. The process of summarizing may be accomplished by creating a multi-dimensional data structure in which each dimension corresponds to a parameter. And forming a plurality of comprehensive burr parameter layers by combining the initial layers with different parameters in a crossing way. For example, for a combination of "low voltage amplitude" and "short width", a new burr parameter layer may be defined that combines the common effects of both parameters in a particular situation. Based on experimental data, statistical methods (e.g., mean and standard deviation) can be used to determine correlations between different layers and identify combinations that have significant impact on chip performance. By such a summary, the resulting burr parameter layer will not only cover the individual features of the individual parameters, but also reveal interactions between the parameters, thereby providing a more comprehensive test solution.
S130, determining a plurality of voltage burr parameter combinations of the safety chip according to the plurality of burr parameter layers.
It will be appreciated that a voltage spike parameter combination for a security chip to be tested may be systematically generated by analyzing all spike parameter layers. The combination of voltage glitch parameters will provide a basis for subsequent testing, covering various possible voltage glitch conditions, in order to comprehensively evaluate the fault sensitivity of the chip.
Optionally, S130, determining a plurality of voltage glitch parameter combinations of the security chip according to the plurality of glitch parameter layers, including:
S131, determining the sample importance of each burr parameter layer according to the plurality of burr parameter layers, wherein the sample importance is used for reflecting the importance degree of the burr parameter layers in the test process.
It will be appreciated that the sample importance is used to evaluate the relative importance of different parameter layers in a particular task or model, reflecting the importance of the burr parameter layers during testing. The evaluation of the importance of the sample may rely on historical test data to calculate the frequency of failure of each parameter layer in the test or its significance to the failure response. The importance of each level to the final result may be determined by a variety of statistical methods, such as using weighting indicators or information gains, etc. The high level of sample importance indicates that it may have a greater impact in failure testing and therefore more importance and resource allocation should be given.
Illustratively, using information gain to evaluate the importance of a sample, a sample importance model may be constructed using known data sets (e.g., data containing different combinations of voltage spike parameters and their corresponding fault occurrences). Entropy of the entire data set may be calculated, representing uncertainty of the information. The entropy formula is: Where p i is the probability of each category (e.g., fault or normal). The entropy under a given parameter combination is calculated and represents the uncertainty of the system after the known parameter combination. The information gain formula is determined as IG (S, a) =h (S) -H (s|a), wherein IG (S, a is the information gain of the sample S passing through the parameter a, H (S) is the total entropy, and H (s|a) is the conditional entropy.
S132, determining the sampling quantity of each burr parameter layer according to the sample importance of each burr parameter layer.
It will be appreciated that by calculating the sample importance of each burr parameter layer, a relative specific gravity can be provided for each level that reflects the importance of that layer throughout the test. The sample importance level may be regarded as an index reflecting how much each of the burr parameter layers may affect the performance and failure of the security chip during the test. The higher the sample importance means that the layer is of greater importance in revealing potential failures or performance bottlenecks in the chip. Therefore, a higher sample importance parameter layer should be allocated a greater number of samples in order to collect enough data to ensure the reliability of its results. When determining the number of samples, the total number of samples may be set, which may be preset according to the resources tested, time constraints, experimental design, and other factors. And weighting and distributing the total sample number according to the sample importance of each burr parameter layer. The duty cycle of each layer may be calculated by dividing the sample importance of each layer by the sum of the sample importance of all layers, thereby determining a specific number of samples from the duty cycle. For example, if the total number of samples is set to 100, the sample importance of the parameter layer a is 0.4, the sample importance of the parameter layer B is 0.3, and the sample importance of the parameter layer C is 0.3, the number of samples of the layer a may be calculated as a number of samples a=100×0.4/(0.4+0.3+0.3) =40, and similarly, the number of samples of the layer B and the layer C may be calculated accordingly.
S133, based on the sampling quantity of each burr parameter layer, carrying out random parameter combination in each burr parameter layer, and determining a plurality of voltage burr parameter combinations of the safety chip.
It will be appreciated that each burr parameter layer determines a specific number of samples reflecting the importance and necessity of each parameter layer throughout the test. The process of random parameter combination is performed in each of the spur parameter layers, mainly by randomly extracting a certain number of sample parameters from each layer, and then combining these parameters to form a new voltage spur parameter combination. The importance of this process is that the working state of the security chip under various voltage conditions can be simulated so as to more comprehensively observe and analyze the response behavior of the chip under various conditions. A number of samples may be randomly selected from each burr parameter layer, the number of samples being based on the number of samples determined in the previous step. The random selection approach ensures sample diversity, thereby avoiding potential bias. After the samples are selected, the samples are combined according to a preset rule to form a plurality of voltage burr parameter combinations. Rules for combining may include, but are not limited to, cross-combining of different parameters, series or parallel connection under specific conditions, and the like. For example, if parameters included in a certain burr parameter layer are voltage amplitude, application width, and application time, the randomly extracted samples may be:
Voltage amplitude of 2V, 3V and 5V
Width of 1ms, 2ms
The application time is early, medium and late
By combining these random samples, one can form, for example:
combination 1, voltage amplitude 2V, width 1ms, early application time
Combination 2 voltage amplitude 3V, width 2ms, middle application time
Combination 3, voltage amplitude 5V, width 1ms, late application time
The random combination mode can generate a large number of voltage burr parameter combinations so as to ensure that as many working scenes as possible are covered, and the subsequent system test and evaluation on the performances of the safety chip under various voltage burr conditions are facilitated.
S200, controlling the burr injection device to perform burr injection on the safety chip according to each voltage burr parameter combination of the safety chip, and obtaining the fault occurrence times corresponding to each voltage burr parameter combination.
It can be understood that the voltage burr parameter combination can be input into the burr injection device according to the predefined voltage burr parameter combination, and the burr injection device has the function of performing burr injection on the safety chip, so that the influence of the voltage burr can be accurately simulated under the condition of each combination. The spur injection means (Glitch Injection Device) are typically used to test the robustness of the electronic device under non-ideal power supply conditions, and may simulate transient voltage changes (so-called "spurs" or "transients") on the power supply line to detect the response of the electronic device under such conditions. The burr injection device can simulate voltage fluctuation possibly encountered in a real environment, has high-precision voltage regulation capability, and can rapidly switch different voltage states. After each burr injection, the response conditions of the safety chip, including whether faults occur, the types of the faults and other performance indexes, can be received and recorded in real time, not only can the faults be identified, but also the parameter setting of the burr injection can be further optimized.
In one possible implementation manner, S200, according to each voltage burr parameter combination of the security chip, controls the burr injection device to perform burr injection on the security chip, so as to obtain the number of fault occurrences corresponding to each voltage burr parameter combination, including:
S210, controlling the burr injection device to perform burr injection on the safety chip according to each voltage burr parameter combination of the safety chip, and receiving burr injection data of the safety chip.
It will be appreciated that a combination of voltage spike parameters may be sent to the spike injection device to initiate an experiment of voltage spike injection. In this step, the controller applies the glitch signal to the security chips one by one according to the preset voltage glitch parameter combination. When the burr injection device performs burr injection on the safety chip, response data of the safety chip can be received in real time, and the received response data can comprise working states, current changes, integrity of output signals and the like. May be collected and stored by a data acquisition system for subsequent data analysis.
S220, determining fault events corresponding to each voltage burr parameter combination based on the burr injection data of the safety chip and a preset fault judgment rule.
It will be appreciated that after the spur injection data is obtained, the spur injection data may be analyzed and compared with a preset fault determination rule. The fault determination rule is set according to the historical data and the working characteristics of the safety chip and is used for determining the conditions under different voltage burr conditions, which cause faults. The fault decision rule may include thresholds for certain critical parameters, such as maximum current of the chip, temperature, waveform of the output signal, etc. When the injected voltage spike exceeds a certain threshold, or under certain conditions, it is recorded as a fault event (see fig. 4). In the analysis process, various data analysis methods, such as statistical analysis, anomaly detection methods, etc., may be used to improve the accuracy of fault detection. Statistical analysis may involve descriptive statistics of the collected data to find failure frequencies and patterns at different voltage glitches. The anomaly detection method can be used for calculating the occurrence probability of the abnormal condition by constructing a statistical model (such as normal distribution) under the normal operation state and comparing the new data points with the model. If the probability of a certain data point is lower than a preset threshold value, the data point is judged to be abnormal. By comparing the glitch injection data with the fault determination rules, it is possible to determine whether each voltage glitch parameter combination will cause a fault, and record a corresponding fault event.
S230, calculating the number of fault events corresponding to each voltage burr parameter combination, and obtaining the fault occurrence times corresponding to each voltage burr parameter combination.
It will be appreciated that after the spur injection is completed and the injection data is acquired, the injection data may be consolidated to determine that the relevant fault event for each voltage spur parameter combination is properly recorded. A data structure (e.g., a data table or database) may be constructed to associate each parameter combination with a corresponding fault event. The fault events may be classified and counted, and for each voltage glitch parameter combination, all recorded fault events are checked and classified and counted. A simple counter can also be used to track the number of occurrences of each fault event under each parameter combination, so that the fault data of each parameter combination can comprehensively reflect the performance of each parameter combination in the actual test.
Optionally, the fault event includes a plurality of different types of preset fault events, and S230, calculating the number of fault events corresponding to each voltage glitch parameter combination to obtain the number of times of fault occurrence corresponding to each voltage glitch parameter combination, including:
s231, calculating the number of each preset fault event corresponding to each voltage burr parameter combination, and obtaining the fault occurrence times of each preset fault event corresponding to each voltage burr parameter combination.
It will be appreciated that the predetermined fault event is determined based on past experimental data and theoretical analysis, and includes various fault types that may occur under different voltage glitch conditions. For example, these fault events may include response time-outs, too long responses, too short responses, etc. of the chip. Fault event records associated with each voltage spike parameter combination may be screened from the collected spike injection data. For each preset fault event, the occurrence frequency of the fault event under the corresponding voltage burr parameter combination is counted. The number of faults can be displayed in a chart form by using a visualization tool, so that the result is more visual. Through the statistical result, the voltage burr parameter combinations which are most likely to cause specific fault events can be clearly known, and an important basis is provided for subsequent fault analysis and safety design optimization.
In one possible implementation manner, S200, according to each voltage burr parameter combination of the security chip, controls the burr injection device to perform burr injection on the security chip to obtain the number of times of fault occurrence corresponding to each voltage burr parameter combination, and further includes:
s240, determining the total test times of each voltage burr parameter combination for testing according to the burr injection data of the safety chip.
It will be appreciated that the total number of tests refers to the total number of complete test operations performed under a particular voltage spike parameter combination, and that relevant information can be extracted from the collected spike injection data. All the burr injection data can be traversed, and the test condition of each voltage burr parameter combination is extracted. The data may be collated and processed using data analysis tools such as the Pandas library of Python or Excel, etc. For each combination of voltage glitch parameters, a counter may be created that counts the number of occurrences of the combination in the dataset, representing the number of tests under the combination, and the statistics will provide powerful data support for subsequent failure analysis, evaluation, and optimization of the design of the security chip.
S300, determining fault sensitivity corresponding to each voltage burr parameter combination based on the fault occurrence times corresponding to each voltage burr parameter combination.
It can be understood that the fault sensitivity is an index reflecting the response degree of the system to the fault event under the specific voltage condition, and the possibility of the fault of the safety chip under the specific voltage burr can be evaluated. The corresponding fault sensitivity can be calculated according to the fault occurrence times of each voltage burr parameter combination and the total test times of each voltage burr parameter combination for testing. By determining the fault sensitivity corresponding to each voltage burr parameter combination, the influence of different parameter combinations on the safety chip can be better understood, and guidance is provided for design and improvement.
In one possible implementation, S300, determining the fault sensitivity corresponding to each voltage spike parameter combination based on the number of times of fault occurrence corresponding to each voltage spike parameter combination, includes:
s310, determining fault sensitivity corresponding to each voltage burr parameter combination based on the fault occurrence times and the total test times of each preset fault event corresponding to each voltage burr parameter combination.
It can be understood that the corresponding fault sensitivity can be calculated according to the number of faults occurring in each voltage spike parameter combination and the total number of tests performed by each voltage spike parameter combination. By determining the fault sensitivity corresponding to each voltage burr parameter combination, the influence of different parameter combinations on the safety chip can be better understood, and guidance is provided for design and improvement.
Optionally, S310, determining, based on the number of fault occurrences and the total number of tests of each preset fault event corresponding to each voltage spike parameter combination, a fault sensitivity corresponding to each voltage spike parameter combination includes:
s311, determining fault sensitivity corresponding to each voltage burr parameter combination through a first formula based on the fault occurrence times and the total test times of each preset fault event corresponding to each voltage burr parameter combination, wherein the first formula is as follows: s is the sensitivity to faults, For the number of occurrences of each of the predetermined fault events corresponding to the voltage glitch parameter combination,The total test times corresponding to the voltage burr parameter combination.
It can be understood that the fault sensitivity corresponding to each voltage spike parameter combination can be calculated by a preset first formula: s is the sensitivity to faults, For the number of occurrences of each of the predetermined fault events corresponding to the voltage glitch parameter combination,The total test times corresponding to the voltage burr parameter combination.
S400, determining a test result of the safety chip according to the fault sensitivity corresponding to each voltage burr parameter combination.
It will be appreciated that the fault sensitivity may be combined with a particular fault type by analyzing the fault sensitivity for each voltage spike parameter combination to form a comprehensive test evaluation model. Fault type information and environmental path information may be received. The fault type information is derived from preset fault events, is associated with fault phenomena observed in actual tests, and can help evaluate the nature and influence degree of the faults. The environmental path information refers to a saved path, and includes information such as parameter setting, testing steps, environmental conditions, etc. used in the testing process. And generating a fault sensitivity curve of the safety chip according to the fault type information and the fault sensitivity. The fault sensitivity curve is a result of graphically presenting fault sensitivity data of different voltage glitch parameter combinations, and can intuitively show the reliability and vulnerability of the chip under different conditions. Through analysis of the curves, the parameter vulnerability sensitivity points can be identified. The parameter weakness points refer to parameter combinations which are easy to cause faults under specific conditions, and the parameter combinations can cause problems such as design defects or material fatigue. Through a statistical method such as linear feature extraction, abrupt points and inflection points of a curve can be identified, and the test result of the safety chip is comprehensively evaluated.
In one possible implementation manner, S400, determining a test result of the security chip according to the fault sensitivity corresponding to each voltage spike parameter combination includes:
S410, receiving fault type information and environment path information, wherein the fault type information is used for being associated with a preset fault event.
It may be understood that the fault type information is fault type information (refer to fig. 5) corresponding to preset fault events one to one, and is used for generating fault sensitivity curves corresponding to different types of preset fault events in a correlated manner, and the fault sensitivity curves can be obtained by receiving input or selection of a user on an input interface, and the user can select a corresponding fault type from a preset fault list and record the selection of the user as the fault type information. The environment path information refers to a document storage path for storing the generated fault sensitivity curve and related information of the generated running environment. The environment path points to a specific file storage location, so that the data can be correctly saved and the subsequent access is convenient when the fault sensitivity curve is generated and recorded. The user may select a storage path as desired, such as selecting a particular folder, and the acquisition of the environmental path information may also be accomplished by the user's selection. When a user selects a storage path in the system, the information is recorded so that the data can be quickly accessed during subsequent analysis and report generation, the test efficiency and the reliability of data analysis can be improved, and a scientific basis is provided for subsequent evaluation.
S420, generating a fault sensitivity curve of the safety chip according to the fault type information, the environment path information and the fault sensitivity corresponding to each voltage burr parameter combination.
It will be appreciated that the fault sensitivity values may be paired with corresponding voltage parameter combinations. The sensitivity value for each parameter combination will be taken as one data point in the curve. By a data fitting method (such as linear regression, spline interpolation and the like), data points of a targeted sensitivity curve are generated according to fault type information and are connected into a curve (refer to fig. 6), and the generated fault sensitivity curve is stored according to environment path information. The generated sensitivity curve may be plotted, for example, using a chart tool (e.g., matplotlib, excel, etc.) for visualization. The fault sensitivity curve can intuitively reflect the fault sensitivity under different voltage conditions and can also help identify key thresholds for fault occurrence under specific conditions.
S430, analyzing the fault sensitivity curve of the security chip, and determining the parameter sensitivity points of the security chip.
It can be appreciated that the fault sensitivity curve is formed by visualizing the combination of the voltage glitch parameters and the corresponding fault sensitivity data, reflecting the degree of response of the security chip to the fault under different voltage conditions. The performance of the chip under different working conditions can be revealed by analyzing the curve, and the parameter sensitive point of the security chip can be determined. Parameter sensitivity points refer to points of weakness in a particular system or component (e.g., a security chip) where small changes in certain parameters may lead to significant degradation or failure of the system.
Optionally, S430, analyzing the fault sensitivity curve of the security chip, and determining the parameter weak point of the security chip includes:
S431, carrying out linear feature extraction on the fault sensitivity curve of the safety chip, and determining the linear transformation trend of the fault sensitivity curve.
It will be appreciated that statistical methods such as linear regression analysis may be applied to extract features from the fault sensitivity curve. The purpose of linear feature extraction is to identify the region of linear variation in the curve, determining its slope and intercept. These trends in linear transformation may reveal the response characteristics of the chip over a particular voltage range. For example, if the curve exhibits a relatively smooth linear characteristic over a certain voltage interval, it is stated that the fault response of the chip is relatively stable within this range. Conversely, if the slope of the curve increases significantly in some areas, it is indicated that the change in parameters within the interval has a greater impact on the failure rate.
S432, determining abrupt points and inflection points of the fault sensitivity curve according to the linear transformation trend of the fault sensitivity curve, wherein the abrupt points are used for representing points where the linear transformation trend changes.
It will be appreciated that the linear feature extraction results may be analyzed to locate abrupt points and inflection points in the curve. A discontinuity refers to a location where the linear transformation trend of the fault sensitivity curve changes significantly, and generally means that the response characteristics of the system change around that point. The inflection point is the point where the slope of the curve changes, marking the transition of the system behavior. Through the determination of the abrupt points and the inflection points of the fault sensitivity curve, the potential vulnerability of the safety chip under different working conditions can be further understood, and a foundation is laid for the subsequent sensitivity analysis.
S433, performing sensitivity analysis on the abrupt points and inflection points of the fault sensitivity curve, and determining the parameter weak points of the safety chip.
It will be appreciated that the identified points of mutation and inflection may be analyzed in depth by sensitivity analysis methods to determine specific parametric weaknesses. It may involve calculating the extent to which small changes in parameters affect the failure rate or performance index near these key points. For example, the percent change in failure rate as the parameters change may be calculated, further confirming which parameters are most sensitive under certain conditions. Through a sensitivity analysis method, parameters with the greatest influence on the system performance can be effectively identified, and a basis is provided for subsequent evaluation.
Illustratively, by determining the specific locations of the abrupt and inflection points, it is possible to choose to take several voltage values before and after the abrupt and inflection points, respectively, to construct the range of the analysis. For example, if the mutation point is at 5V, a value between 4.5V and 5.5V may be selected for analysis. Within the selected voltage range, small changes in the parameters are made. Several different magnitudes of change (e.g., ±0.1v or ±0.2v) can be set and the failure rate at each voltage value recorded. For each voltage value, the failure rate in the case of a small change in the parameter is calculated. For example, assuming a failure rate of 3% at 5V, the failure rates are 2.5% and 3.5% when the voltage is trimmed to 4.9V and 5.1V, respectively. The percentage change can be calculated using the formula percentage change = (new failure rate-original failure rate)/original failure rate x 100% resulting in a relative change in failure rate at different voltage changes. And combining the calculated fault rate change with the corresponding voltage change to obtain the sensitivity index of each parameter. Sensitivity coefficients may be employed to quantify the impact of parameter variations on system performance. The calculation formula of the sensitivity coefficient is s=Δy/Δx, where S is the sensitivity coefficient, Δy is the change of the failure rate, and Δx is the change of the parameter (voltage). By analyzing the sensitivity coefficients of the different parameters it is determined which parameters are most sensitive under specific conditions. Typically, the parameter with the larger sensitivity coefficient value is the fragile point.
S440, determining the test result of the security chip according to the parameter sensitivity point and the fault sensitivity curve of the security chip.
It will be appreciated that all test data may be integrated into one database or spreadsheet depending on the parameter sensitivity points and fault sensitivity curves of the security chip. Test scripts such as Python can be used for executing test cases and recording results, complete test reports can be automatically generated through the scripts or tools, the fault sensitivity curves are combined to evaluate the performance of the chip under different fault conditions, the reliability and stability of the safety chip under each working state are output, and for example, the situation that the fault rate is remarkably increased under specific voltage or other conditions is identified. And outputting a final test report of the security chip according to all integrated data, rapidly and accurately evaluating the fault sensitivity of the chip, and finding out the weakest point of the chip under different conditions, thereby providing scientific basis for improving the chip design and optimizing the protective measures.
Corresponding to the voltage glitch-based fault sensitivity calculation method of the above embodiment, the embodiment of the present application further provides a voltage glitch-based fault sensitivity calculation system, where each unit of the system may implement each step of the voltage glitch-based fault sensitivity calculation method. Fig. 7 shows a block diagram of a fault sensitivity calculation system based on voltage glitches according to an embodiment of the present application, and only the portions related to the embodiment of the present application are shown for convenience of explanation.
Referring to fig. 7, the fault sensitivity calculation system based on the voltage spike includes:
The device comprises an acquisition unit, a detection unit and a control unit, wherein the acquisition unit is used for acquiring parameter scanning information of a safety chip and determining a plurality of voltage burr parameter combinations of the safety chip based on the parameter scanning information, wherein the parameter scanning information is related parameters of preliminary voltage burrs obtained according to the voltage burr fault injection result;
The injection unit is used for controlling the burr injection device to perform burr injection on the safety chip according to each voltage burr parameter combination of the safety chip to obtain the fault occurrence times corresponding to each voltage burr parameter combination;
the analysis unit is used for determining fault sensitivity corresponding to each voltage burr parameter combination based on the fault occurrence times corresponding to each voltage burr parameter combination;
and the result unit is used for determining the test result of the safety chip according to the fault sensitivity corresponding to each voltage burr parameter combination.
It should be noted that, because the content of information interaction and execution process between the above systems/units is based on the same concept as the method embodiment of the present application, specific functions and technical effects thereof may be referred to in the method embodiment section, and will not be described herein.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described functional distribution may be performed by different functional units and modules according to needs, i.e. the internal structure of the system is divided into different functional units or modules to perform all or part of the above-described functions. The functional units and modules in the embodiment may be integrated in one processing unit, or each unit module may exist alone physically, or two or more unit modules may be integrated in one unit, where the integrated unit may be implemented in a form of hardware or a form of a software functional unit. In addition, the specific names of the functional units and modules are only for distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working process of the units and modules in the above system may refer to the corresponding process in the foregoing method embodiment, which is not described herein again.
The embodiment of the application also provides a fault sensitivity calculating device based on the voltage glitch, and fig. 8 is a schematic structural diagram of the fault sensitivity calculating device based on the voltage glitch according to the embodiment of the application. As shown in fig. 8, the voltage spike based fault sensitivity calculation apparatus 6 of this embodiment includes at least one processor 60 (only one is shown in fig. 8), at least one memory 61 (only one is shown in fig. 8), and a computer program 62 stored in the at least one memory 61 and executable on the at least one processor 60, which processor 60, when executing the computer program 62, causes the voltage spike based fault sensitivity calculation apparatus 6 to implement the steps in any of the various voltage spike based fault sensitivity calculation method embodiments described above, or causes the voltage spike based fault sensitivity calculation apparatus 6 to implement the functions of the various elements in the system embodiments described above.
Illustratively, the computer program 62 may be partitioned into one or more units that are stored in the memory 61 and executed by the processor 60 to complete the present application. The one or more units may be a series of computer program instruction segments capable of performing a specific function for describing the execution of the computer program 62 in the voltage glitch-based fault sensitivity calculation 6.
For example, the voltage glitch-based fault sensitivity calculation device 6 may include a processor, a communication device (e.g., serial interface, parallel interface, USB), a network device, a hardware acquisition device (e.g., oscilloscope, digital-to-analog converter, sensor), a glitch injection device (e.g., signal generator, pulse generator, coupled network), a memory, and so forth. The voltage glitch-based fault sensitivity calculation device may include, but is not limited to, a processor 60, a memory 61. It will be appreciated by those skilled in the art that fig. 8 is merely an example of a voltage glitch-based fault sensitivity calculation device 6 and is not intended to be limiting of the voltage glitch-based fault sensitivity calculation device 6, and may include more or fewer components than illustrated, or may combine certain components, or different components, such as may also include input-output devices, network access devices, buses, etc.
The Processor 60 may be a central processing unit (Central Processing Unit, CPU), the Processor 60 may also be other general purpose processors, digital signal processors (DIGITAL SIGNAL Processor, DSP), application SPECIFIC INTEGRATED Circuit (ASIC), off-the-shelf Programmable gate array (Field-Programmable GATE ARRAY, FPGA) or other Programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The memory 61 may in some embodiments be an internal storage unit of the voltage glitch based fault sensitivity calculation device 6, such as a hard disk or a memory of the voltage glitch based fault sensitivity calculation device 6. The memory 61 may also be an external storage device of the voltage glitch-based fault sensitivity calculation device 6 in other embodiments, such as a plug-in hard disk, a smart memory card (SMART MEDIA CARD, SMC), a Secure Digital (SD) card, a flash memory card (FLASH CARD) or the like, which are provided on the voltage glitch-based fault sensitivity calculation device 6. Further, the memory 61 may also include both an internal memory unit and an external memory device of the voltage spike based fault sensitivity calculation device 6. The memory 61 is used for storing an operating system, application programs, boot loader (BootLoader), data, other programs, etc., such as program codes of the computer program. The memory 61 may also be used for temporarily storing data that has been output or is to be output.
Embodiments of the present application also provide a computer readable storage medium storing a computer program which, when executed by a processor, performs the steps of any of the various method embodiments described above.
Embodiments of the present application provide a computer program product that, when run on a voltage glitch-based fault sensitivity calculation device, causes the voltage glitch-based fault sensitivity calculation device to implement the steps of any of the various method embodiments described above.
The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the present application may implement all or part of the flow of the method of the above embodiments, and may be implemented by a computer program to instruct related hardware, where the computer program may be stored in a computer readable storage medium, and when the computer program is executed by a processor, the computer program may implement the steps of each of the method embodiments described above. Wherein the computer program comprises computer program code which may be in source code form, object code form, executable file or some intermediate form etc. The computer readable medium can include at least any entity or means that can carry computer program code to a voltage glitch-based fault sensitivity computing device, a recording medium, computer Memory, read-Only Memory (ROM), random access Memory (RAM, random Access Memory), electrical carrier signals, telecommunications signals, and software distribution media. Such as a U-disk, removable hard disk, magnetic or optical disk, etc. In some jurisdictions, computer readable media may not be electrical carrier signals and telecommunications signals in accordance with legislation and patent practice.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiments provided in the present application, it should be understood that the disclosed voltage glitch-based fault sensitivity calculation system/voltage glitch-based fault sensitivity calculation apparatus and method may be implemented in other manners. For example, the above-described voltage glitch-based fault sensitivity calculation system/voltage glitch-based fault sensitivity calculation apparatus embodiments are merely illustrative, e.g., the division of the elements is merely a logical functional division, and there may be additional divisions in actual implementation, e.g., multiple elements or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection via interfaces, devices or units, which may be in electrical, mechanical or other forms.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
The foregoing embodiments are merely illustrative of the technical solutions of the present application, and not restrictive, and although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that modifications may still be made to the technical solutions described in the foregoing embodiments or equivalent substitutions of some technical features thereof, and that such modifications or substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application.
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| CN109228861A (en) * | 2018-09-26 | 2019-01-18 | 合肥澎湃能源技术有限公司 | For diagnosing and handling the method and system of the failure of accelerator pedal |
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