Detailed Description
The present application will be described and illustrated with reference to the accompanying drawings and examples for a clearer understanding of the objects, technical solutions and advantages of the present application.
Unless defined otherwise, technical or scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms "a," "an," "the," "these" and similar terms in this application are not intended to be limiting in number, but may be singular or plural. The terms "comprises," "comprising," "includes," "including," "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, and system, article, or apparatus that comprises a list of steps or modules (units) is not limited to the list of steps or modules (units), but may include other steps or modules (units) not listed or inherent to such process, method, article, or apparatus. The terms "connected," "coupled," and the like in this disclosure are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The term "plurality" as used herein means two or more. "and/or" describes the association relationship of the association object, and indicates that three relationships may exist, for example, "a and/or B" may indicate that a exists alone, a and B exist simultaneously, and B exists alone. Typically, the character "/" indicates that the associated object is an "or" relationship. The terms "first," "second," "third," and the like, as referred to in this disclosure, merely distinguish similar objects and do not represent a particular ordering for objects.
Aiming at the problem of non-ideal performance of the current LC oscillator switch capacitor array, some technical schemes are proposed in the prior art, but the technical schemes still have the problem of obviously non-ideal performance.
Referring to fig. 3, the left side of the diagram shows a switching transistor with a differential structure (the right side of the diagram shows an equivalent model when the switch is turned off, and R on1、Ron2 and R on3 are the turn-off resistances of the transistors S 1、S2 and S 3, respectively), so that the on-resistance of the switch in the same size can be further halved, and the Q value of the switched capacitor array capacity can be improved, where the transistors S 2 and S 3 are used to provide a dc level at A, B points in the on state.
With the progress of the process and the further improvement of the tuning range, the conventional scheme shown in fig. 3 also has the following disadvantages:
(1) Because the on-resistance of the switch transistor S 1 is inversely related to the gate-source voltage V GS, the on-resistance of the switch transistor is greatly increased under the advanced process or low-voltage design condition, the Q value of the switch capacitor array is significantly reduced, and the phase noise of the oscillator is reduced.
(2) In order to reduce the parasitic capacitance of the transistor, S 2、S3 is typically the smallest transistor in the structure shown in fig. 3, and the switching transistor also typically uses the smallest trench length under the process, but this inevitably increases the contribution of flicker noise, worsening the 1/f 3 region phase noise, which is particularly significant under the advanced process.
(3) To ensure continuous frequency coverage in the case of process and temperature variations, the unit capacitance Cu in the capacitive array typically needs to be about 30% smaller than the range of capacitance values (Cmax-Cmin) provided by the selected varactor—obviously, at the same target tuning range, this means a larger array count and poorer noise performance.
Therefore, there still exists a problem in the prior art that the performance of the LC oscillator switched capacitor array is not ideal.
Based on this, in an embodiment of the present invention, there is provided a switching circuit of an LC oscillator, the LC oscillator further including a resonant cavity, the switching circuit being configured to control an oscillation frequency of the LC oscillator by controlling a capacitance value of the resonant cavity, a first output node and a second output node of the resonant cavity being connected to a first variable capacitor.
Generally, the LC oscillator comprises a resonant cavity and a switching circuit, and the invention is an improvement of the switching circuit. The circuit structure of the resonant cavity portion (including the first variable capacitor) is an existing mature structure, and referring to fig. 1 specifically, the present invention is not specifically described, and the first output node and the second output node are respectively the X node and the Y node in fig. 1.
Referring to fig. 4, the switch circuit comprises two groups of switch arrays, each group of switch arrays comprises a plurality of second variable capacitors connected in parallel, wherein the output end of each second variable capacitor in one group of switch arrays is connected with a first output node of a resonant cavity, the output end of each second variable capacitor in the other group of switch arrays is connected with a second output node of the resonant cavity, the size of each second variable capacitor in any group of switch arrays is multiplied, the smallest size of the second variable capacitor is a target multiple of the size of the first variable capacitor, the target multiple is smaller than 1, and the control ends of the second variable capacitors are sequentially connected with low-order control words to high-order control words in order of small size.
For example, the dimensions of the respective second variable capacitors are multiplied, meaning that the dimensions of the latter second variable capacitor are twice those of the former second variable capacitor. Correspondingly, the control ends of the second variable capacitors are sequentially connected with the lower bits to the upper bits of the multi-bit control word according to the order from small to large in size. For example, assuming that the switch array is formed by three second variable capacitors connected in parallel, and that the first second variable capacitor has a size of 1 and a three-bit control word is present, the control terminal of the first second variable capacitor is connected to the lowest bit of the control word, the second variable capacitor has a size of 2, the control terminal thereof is connected to the middle bit of the control word, and the third second variable capacitor has a size of 4, and the control terminal thereof is connected to the highest bit of the control word.
Compared with the prior art in fig. 2, the invention adopts the variable capacitance to replace the metal capacitance to provide capacitance value for the resonant cavity. As described above, it is necessary to use a switching device to control whether each metal capacitor provides a capacitance value for the resonant cavity, and when a certain switching device is closed, the metal capacitor connected in series with the switching device provides a capacitance value for the resonant cavity. In a first aspect, the switching device has a resistance when closed, the presence of which reduces the Q of the resonant cavity. In the second aspect, parasitic capacitance exists when the switching device is turned off, so that a capacitance value provided by a single metal capacitor for the resonant cavity is reduced, a tuning range of the resonant cavity is reduced, and capacitance noise of the resonant cavity is improved, or more metal capacitors are required to be arranged under the condition of ensuring the same tuning range, so that circuit area and layout difficulty are increased. In the third aspect, due to the existence of parasitic capacitance and difficulty in accurately measuring the parasitic capacitance, the difference between the actual capacitance value and the ideal capacitance value (capacitance labeling value) of a single metal capacitance is difficult to measure, and meanwhile, due to the process difference between the metal capacitance and a variable capacitance (the capacitance labeling value may be the same but the actual capacitance value is significantly different), in order to ensure continuous frequency coverage of the resonant cavity (the actual capacitance value of the metal capacitance is smaller than the maximum capacitance actual value of the variable capacitance), the capacitance labeling value of the metal capacitance is generally required to be set to be smaller than 30% of the maximum capacitance labeling value of the variable capacitance. Further, more metal capacitors are required to be arranged in the same tuning range, so that the circuit area and layout difficulty are increased.
The invention adopts the variable capacitor to provide capacitance value for the resonant cavity. On the one hand, the variable capacitor has no parasitic capacitance and resistance, and the actual capacitance value is basically the same as the capacitance labeling value, so that capacitance noise is basically not generated and the Q value of the resonant cavity is reduced. On the other hand, the process error between the capacitors of the same type is extremely small, namely, the process error of the first variable capacitor and the second variable capacitor is extremely small, and basically, when the maximum capacitance labeling values of the first variable capacitor and the second variable capacitor are the same, the maximum capacitance actual values of the first variable capacitor and the second variable capacitor are the same. In order to ensure continuous frequency coverage of the resonant cavity, the maximum capacitance marking value of the first variable capacitor is slightly smaller than the maximum capacitance marking value of the second variable capacitor (for example, 20% or 10% is reduced or even lower, and obviously less than 30% in the prior art), and excessive design margin is not required to be given, so that the number of columns of a switch array can be reduced, and the area occupation of a switch circuit is reduced.
In some of these preferred embodiments, the target multiple is between 0.8-0.95. The maximum capacitance value of the variable capacitance is positively correlated to its own size. The target multiple determines the maximum capacitance ratio between the first variable capacitance and the second variable capacitance. As described above, the process variation of the same type of capacitance is very small, and the maximum capacitance value of the variable capacitors with the same size is substantially the same. Even if a certain error is considered, the target multiple can be set close to 1. Preferably, when the target multiple is between 0.8 and 0.95, the maximum capacitance actual value of the second variable capacitor is smaller than the maximum capacitance actual value of the first variable capacitor, and meanwhile, a smaller design margin is ensured, and the area occupation of the switch circuit is reduced as much as possible.
In one embodiment, the target multiple is 0.8 and the ratio of the multiple of the second variable capacitance to the first variable capacitance is 0.8. For example, the first variable capacitance is a multiple of 5 and the second variable capacitance is a multiple of 4. Alternatively, the first variable capacitance may be a multiple of 10 and the second variable capacitance may be a multiple of 8. The embodiment can further ensure matching and simplify the drawing difficulty of the layout. In other embodiments, the ratio of the multiples of the two variable capacitances may meet the target multiple.
In some of these embodiments, the second variable capacitance number in each set of switch arrays is four. Each second variable capacitor corresponds to one bit of control word, and four second variable capacitors can support four bits of control word.
In summary, the invention replaces the metal capacitor in the traditional switch array with the variable capacitor, which not only can reduce the capacitance noise of the resonant cavity and improve the Q value of the resonant cavity, but also can reduce the area occupation of the switch circuit. Therefore, the switch capacitor array with good performance is provided, and the problem that the performance of the current LC oscillator switch capacitor array is not ideal is solved.
Referring to fig. 5, in some of these embodiments, each second variable capacitor is connected to a respective control word through a low pass filter. The control word is essentially a control signal. The capacitance value of the variable capacitor can be continuously changed and is related to the control signal of the variable capacitor. In the present invention, the second variable capacitor is used in a slightly different manner from the first variable capacitor. For the first variable capacitor, the characteristic that the capacitance value of the first variable capacitor can be continuously changed is needed to be utilized, and the continuously-changed control signal is used for controlling the capacitance value provided by the first variable capacitor for the resonant cavity to realize the continuously-changed capacitance value. For the second variable capacitors, it is necessary to use them as switching devices, and each of the second variable capacitors provides a capacitance value of 0 or its own maximum capacitance value to the resonant cavity, which is different from the conventional use of the variable capacitors. In this manner of use, the control signal noise of the second variable capacitance needs to be taken into account with great importance. The second variable capacitance cannot accurately provide the resonant cavity with its own maximum capacitance value due to the presence of noise. In particular, the second variable capacitors controlled by the high-order control word can generate larger capacitance errors because the maximum capacitance of the second variable capacitors is larger. In summary, the low-pass filtering of the control word of the second variable capacitor can further improve the Q value of the resonant cavity, and since the capacitance value error provided by the second variable capacitor to the resonant cavity is reduced, the design margin can be further reduced, that is, the value of the target multiple can be more prone to 1.
In the conventional switching circuit, the transistor as a switch is a two-state device, and is either turned on or off, so that control signal noise is not substantially introduced into the resonant cavity. Therefore, the control signal noise is not substantially of concern to those skilled in the art in the face of conventional switching circuits. The invention is not limited by the habitual thinking in the field after replacing the metal capacitor in the traditional switch circuit by the variable capacitor, but focuses on the noise of the control signal sharply, and correspondingly adopts a low-pass filter to denoise the control signal.
And, the control signal noise originates from the pre-inverter. Specifically, since the control signal is typically from the inverter of the previous stage, and whether the output is low or high, one of the transistors in the inverter is on, similar to the switching transistor in conventional designs, the limited on-resistance of the transistor causes thermal noise and flicker noise.
Further, the low-pass filter may have a different circuit configuration. Referring to fig. 5 and 6, the low-pass filter includes an NMOS transistor, a PMOS transistor, and a MOS capacitor, wherein the source-drain cross connection of the NMOS transistor (gate-to-power) and the PMOS transistor (gate-to-ground) forms a resistive portion, a first end of the resistive portion is connected to an output terminal of an inverter, an input terminal of the inverter is used for accessing a control word, and the other end of the resistive portion is grounded through the MOS capacitor and connected to a control terminal of a second variable capacitor. Fig. 6 is an equivalent circuit diagram of the low-pass filter.
The plurality of inverters respectively output multi-bit control words, and the output end of each inverter is connected with the control end of the corresponding second variable capacitor through the low-pass filter. The transistor serving as the resistance part comprises an N-type MOS transistor and a P-type MOS transistor to avoid threshold loss, and the N-type transistor serving as the resistance part can use a larger groove length to reduce flicker noise. Meanwhile, the MOS capacitor with higher capacitance density is used as a filter capacitor in the low-pass filter, and the filter capacitor in the low-pass filter is advocated to be realized by using the MOS capacitor and the metal capacitor at the same time, so that the chip area is further saved.
The above is the switching circuit of the LC oscillator provided by the present invention.
The embodiment of the invention also provides an LC oscillator which comprises a resonant cavity and a switching circuit, wherein the switching circuit is used for controlling the oscillation frequency of the LC oscillator by controlling the capacitance value of the resonant cavity, the first output node and the second output node of the resonant cavity are connected with a first variable capacitor, and the switching circuit is the switching circuit of the LC oscillator.
The switching circuit provided by the invention is applied to the existing resonant cavity structure, so that a new LC oscillator can be obtained.
In some of these embodiments, the LC oscillator is applied in a low supply voltage scenario.
As can be seen from the above description of the switching circuit of the LC oscillator, the present invention can effectively reduce noise introduced into the resonant cavity. It should be noted that, in the low power supply voltage scenario and the advanced process scenario, the noise is more obvious, and further the noise removal has more important significance. Furthermore, the LC oscillator and the switching circuit thereof provided by the invention are mainly applied to a low power supply voltage scene or an advanced process scene.
The embodiment of the invention also provides a regulating and controlling method of the LC oscillator, wherein the LC oscillator is provided by the invention, and the regulating and controlling method comprises the following steps:
The capacitance value of the resonant cavity is controlled by a switching circuit to control the oscillation frequency of the LC oscillator. Specifically, by adjusting the multi-bit control word of the switching circuit, the capacitance value of the resonant cavity can be controlled to control the oscillation frequency of the LC oscillator.
The oscillator and the switching circuit thereof in the present invention are described below by way of one embodiment.
Taking 4-bit array tuning as an example, the low voltage LC oscillation based on a variable capacitance array implemented by the present invention is shown in fig. 4. The oscillator core is the same as the traditional design, and consists of an inductor, a fixed and parasitic capacitor, a differential coupling tube and a tail current source, and the variable capacitor controlled by the control voltage V cont and the proposed variable capacitor array jointly form a frequency tuning unit. The working principle of the overall structure and the working principle of the proposed part are as follows:
The inductor L and the sum C tot of various capacitances in the circuit (including a fixed load capacitance C L, a variable capacitance C Var, an array capacitance C B and a parasitic capacitance C P) together form a resonant cavity, a pair of conjugated poles are shown at the frequency of 1/2 pi (LC tot)1/2, which means that the circuit will oscillate at the frequency after power-on), the cross-coupling pair of transistors and a tail current source I ss show alternating negative resistance for counteracting the parasitic resistance in the resonant cavity and maintaining the constant amplitude oscillation of the circuit, and the oscillation frequency can be changed by changing the size of C tot, such as changing the value of C Var by changing the control voltage or changing the value of C B by changing the digital control.
As shown in fig. 4, in the design of the unit capacitance of the capacitor array, the present invention uses a variable capacitance instead of a metal capacitance in the conventional design, so that:
(1) The design difficulty of frequency coverage is simplified by simply selecting the variable capacitor as the unit capacitor of the switched capacitor array with 0.8 times of the variable capacitor according to the application scene of the LC oscillator (such as K VCO required by the specific design of the phase-locked loop). Obviously, this design guarantees a good matching relationship between continuous tuning based on Varactor and discrete tuning based on switched capacitor—if the control voltage V cont changes from 0 to VDD, introducing a change in DC for the cavity, then an increase of 1 in the control word will cause the switched capacitor array to introduce a change in DC for the cavity of 0.8 times (the change needs to be less than or equal to DC), and there must be an overlap between two adjacent tuning curves (e.g. 0 to DC and 0.8 to 1.8DC overlap between two curves). In conventional metal capacitor based designs, careful simulation of the selection of the dimensions of the metal capacitors and the switching tubes is required to reduce area overhead while maintaining frequency coverage.
In the design of the invention, the multiple of 0.8 is advocated to be realized by selecting the multiple of the Vaactor to be 5 and the multiple of the unit switch capacitor to be 4, so that the value further ensures the matching and simplifies the drawing difficulty of the layout.
(2) The use of switching transistors is avoided in that the capacitance "seen" by the resonator can be changed by changing the voltage applied to the control plate, due to the use of a variable capacitance as the basic unit of the switching array, without the need to switch the capacitance into the resonator by means of a turned-on transistor. Thus, problems associated with the on-resistance or parasitic capacitance of the transistor are avoided.
As shown in fig. 5, before the digital control voltage is applied to the variable capacitors in the capacitor array, the low-pass filtering is performed first, because the control voltage is usually from the inverter of the previous stage, and one transistor in the inverter is in an on state no matter outputting a low voltage or a high voltage, similar to the switching transistor in the conventional design, the thermal noise and the flicker noise corresponding to the limited on-resistance of the transistor also enter the resonant cavity through the array capacitor, so as to deteriorate the phase noise of the oscillator. Although relatively superior to conventional capacitor array designs, transistor noise is still not negligible at low voltages, especially in advanced process design scenarios.
As shown in the figure, the addition of the transistor-based low-pass filter well solves the problems that most of noise is led to the ground due to the existence of a filter capacitor, and only a clean control voltage is presented to the capacitor in the array, and the influence of flicker noise is even greatly optimized (namely, the rotation angle of 1/f 3 is reduced) under the design of the prior process and low voltage.
As shown, the low-pass filter described in the present invention is implemented entirely by transistors, wherein the transistors acting as the resistive portion include both N-type MOS transistors and P-type MOS transistors to avoid threshold loss, and the N-type transistors acting as resistors use a larger channel length to reduce flicker noise.
As shown in the figure, the invention uses the MOS capacitor with higher capacitance density as the filter capacitor in the low-pass filter, and advocates the use of both the MOS capacitor and the metal capacitor to realize the filter capacitor in the low-pass filter, so as to further save the chip area.
As shown in the figure, the control paths of the variable capacitor array provided by the invention can use inverters with the minimum size, and only the noise simulation result is combined to properly optimize the size of the low-pass filter capacitor, namely, the reason is that the high-order control word corresponds to a larger variable capacitor in the array, the noise up-conversion effect caused by the high-order control word in the oscillator is more remarkable, and thus, more deep noise filtering is needed, and the filter capacitor on the smaller variable capacitor path corresponding to the low-order control word can be properly reduced to save the chip area.
It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to be limiting. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure in accordance with the embodiments provided herein.
It is to be understood that the drawings are merely illustrative of some embodiments of the present application and that it is possible for those skilled in the art to adapt the present application to other similar situations without the need for inventive work. In addition, it should be appreciated that while the development effort might be complex and lengthy, it would nevertheless be a routine undertaking of design, fabrication, or manufacture for those of ordinary skill having the benefit of this disclosure, and thus should not be construed as a departure from the disclosure.