CN119180243B - Integrated data analysis method, device and storage medium - Google Patents
Integrated data analysis method, device and storage medium Download PDFInfo
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- CN119180243B CN119180243B CN202411641075.8A CN202411641075A CN119180243B CN 119180243 B CN119180243 B CN 119180243B CN 202411641075 A CN202411641075 A CN 202411641075A CN 119180243 B CN119180243 B CN 119180243B
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- 238000000034 method Methods 0.000 title claims abstract description 26
- 238000007405 data analysis Methods 0.000 title claims abstract description 11
- 238000004458 analytical method Methods 0.000 claims abstract description 54
- 230000001133 acceleration Effects 0.000 claims abstract description 21
- 238000012545 processing Methods 0.000 claims abstract description 16
- 238000010230 functional analysis Methods 0.000 claims description 21
- 238000012360 testing method Methods 0.000 claims description 8
- 238000000605 extraction Methods 0.000 claims description 4
- 238000013461 design Methods 0.000 abstract description 3
- 238000005516 engineering process Methods 0.000 abstract description 2
- 230000006870 function Effects 0.000 description 35
- 238000004891 communication Methods 0.000 description 6
- 238000005070 sampling Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 3
- 230000007704 transition Effects 0.000 description 3
- 238000012795 verification Methods 0.000 description 3
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- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004590 computer program Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
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- G—PHYSICS
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- G06F2115/02—System on chip [SoC] design
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Abstract
本发明涉及芯片设计技术领域，特别是涉及一体化数据分析方法、设备及存储介质，其通过获取待测系统中用于性能分析和功能分析的所有关键信号，得到关键信号集合；硬件加速平台根据所述关键信号集合对所述待测系统中的信号进行采样，得到关键信号数据集合；所述硬件加速平台通过接口函数调用分析模块中的处理函数，所述处理函数用于接收所述关键信号数据集合并保存为数据文件；所述分析模块基于所述数据文件进行性能分析和/或功能分析，不会采集和存储冗余的数据，解决了数据冗余的技术问题。
The present invention relates to the field of chip design technology, and in particular to an integrated data analysis method, device and storage medium, which obtains a key signal set by acquiring all key signals used for performance analysis and function analysis in a system to be tested; a hardware acceleration platform samples the signals in the system to be tested according to the key signal set to obtain a key signal data set; the hardware acceleration platform calls a processing function in an analysis module through an interface function, and the processing function is used to receive the key signal data set and save it as a data file; the analysis module performs performance analysis and/or function analysis based on the data file, does not collect and store redundant data, and solves the technical problem of data redundancy.
Description
Technical Field
The present invention relates to the field of chip design technologies, and in particular, to an integrated data analysis method, apparatus, and storage medium.
Background
A hardware acceleration platform refers to an infrastructure that uses dedicated hardware devices (e.g., hardware emulators, FPGAs, etc.) to accelerate system design verification. The method has the main function of providing an efficient environment, so that the verification and analysis process of the SoC system is quicker and more accurate. The hardware acceleration platform supports verification and analysis of the SoC system. In a hardware acceleration platform, the implementation of the SoC system can run at speeds approaching real hardware, which is faster than pure software emulation speeds.
Performance and functional analysis are typically performed on SOC systems based on hardware acceleration platforms to evaluate and verify the actual performance and correctness of the SOC design. Among these, performance analysis focuses on the execution efficiency and resource utilization of the system, such as timing, communication delay, and the like. Functional analysis focuses on ensuring that the system works as intended and meets all functional requirements, such as input/output data flows, state transitions of state machines, etc. Since the purposes of performance analysis and functional analysis are different, the two are usually performed independently, and the respective key signals are sampled and analyzed. Although the emphasis is different, the same signal or data point may be involved in the actual analysis process. Such as interfaces for common protocols like AXI, PCIE, etc. I.e. there is redundancy in the sampled data during performance analysis and functional analysis, not only resulting in repeated sampling, but also increased storage capacity. Therefore, a data analysis method in which redundant data does not exist is demanded.
Disclosure of Invention
Aiming at the technical problems, the invention adopts the technical scheme that the integrated data analysis method comprises the following steps:
S100, acquiring all key signals used for performance analysis and functional analysis in a system to be tested, and obtaining a key signal set.
S300, the hardware acceleration platform samples signals in the system to be tested according to the key signal set to obtain a key signal data set.
S500, the hardware acceleration platform calls a processing function in the analysis module through an interface function, wherein the processing function is used for receiving the key signal data set and storing the key signal data set into a data file.
And S700, performing performance analysis and/or functional analysis by the analysis module based on the data file.
The present invention also provides a non-transitory computer readable storage medium having stored therein at least one instruction or at least one program loaded and executed by a processor to implement the above-described method.
Furthermore, the invention also provides an electronic device comprising a processor and the non-transitory computer readable storage medium.
The invention has at least the following beneficial effects:
The integrated data analysis method, the integrated data analysis equipment and the integrated data storage medium provided by the embodiment of the invention can simultaneously and uniformly acquire the key signals of the performance analysis and the function analysis without repeatedly acquiring the shared interface signals, then store the acquired key signals into the data file through the interface function and the processing function, and the data can not be repeatedly stored during storage, thereby reducing the expenditure of data communication and storage and solving the technical problem of data redundancy.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of an integrated data analysis method according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Unless defined otherwise, all technical and scientific terms used in the embodiments of the present invention have the same meaning as commonly understood by one of ordinary skill in the art.
Referring to fig. 1, there is shown an integrated data analysis method, comprising the steps of:
S100, acquiring all key signals used for performance analysis and functional analysis in a system to be tested, and obtaining a key signal set.
Wherein the system under test is the system being tested or verified.
Optionally, the system under test is SOC (System on Chip) systems, microprocessors, or multi-chip modules. The SOC system includes at least a Processor Core (Processor Core), a Memory Subsystem (Memory Subsystem), an input/output interface (I/O Interfaces), and the like. Other types of first systems under test are also within the scope of the present invention.
Optionally, the processor core is a CPU, GPU, digital Signal Processor (DSP), and/or other type of processor. Other types of processor cores are also within the scope of the present invention.
The key signals of the performance analysis are core indexes which directly reflect the performance of the system and are used for evaluating the operation efficiency, response speed and resource utilization condition of the system.
Optionally, the key signals for performance analysis in the system under test include timing signals collected and recorded through a dedicated interface, and/or communication delay signals. For example, time series signal data acquired through a clock synchronization interface, communication delay signal data acquired through a delay measurement mechanism of a network interface. Other types of key signals for performance analysis are also within the scope of the present invention.
The key signal of the function analysis is a core index which directly reflects whether the system functions work according to the expected or not and is used for verifying whether the system correctly meets the function requirement or not.
Optionally, the key signals for functional analysis in the system under test include input/output data streams transferred and analyzed through the corresponding interfaces, and/or state transition signals of the state machine. For example, input/output data stream signal data collected through the data transmission interface, state transition signal data of the state machine recorded through the state monitoring interface. Other types of key signals for functional analysis are also within the scope of the present invention.
In the system to be tested, part of key signals in performance analysis and functional analysis may be transmitted through shared interface signals. For example, bandwidth and data traffic statistics of network interfaces are used not only for bandwidth utilization and delay assessment in performance analysis, but also for data transmission and status monitoring in functional analysis. The interface signal plays a key role in both analysis tasks.
Wherein the key signal set includes all key signals for performance analysis and functional analysis.
As a preferred embodiment, S100 further comprises the step of selecting a key signal by configuring a selection signal for each key signal, selecting the current key signal when the value of the selection signal is valid, and not selecting the current key signal when the value of the selection signal is invalid.
Optionally, the step of selecting the key signal is implemented by conditional branching or macro definition. Other implementations of the step of selecting the key signal are within the scope of the present invention.
S300, the hardware acceleration platform samples signals in the system to be tested according to the key signal set to obtain a key signal data set.
Wherein, the hardware acceleration platform supports verification and analysis of the SoC system. The system to be tested is an analysis object of the hardware acceleration platform. The system under test is generally responsible for performing core computing and processing tasks, and the hardware acceleration platform provides additional hardware resources and functionality for enhancing analysis capabilities and processing speed.
Optionally, the hardware acceleration platform includes hardware components such as FPGA, GPU, and the like. Hardware acceleration platforms including other hardware groups are also within the scope of the present invention.
The key signal set is a signal which needs to be monitored and analyzed in a key mode in the testing process.
The key signal data is a value or state of the key signal at a specific time point or condition monitored and recorded by the hardware acceleration platform.
It should be noted that, for the shared interface signal of performance analysis and functional analysis, the sampling method only needs to collect once, and repeated acquisition is not needed, so that the data acquisition amount is reduced.
S500, the hardware acceleration platform calls a processing function in the analysis module through an interface function, wherein the processing function is used for receiving the key signal data set and storing the key signal data set into a data file.
The analysis module is a software side and is used for receiving and analyzing the performance data and the functional data according to the key signal data set.
The interface function is an interface between the hardware description language and the software side and is used for transmitting the key signal data set obtained by sampling of the hardware acceleration platform to the software side.
Optionally, the interface function is DPI (Direct Programming Interface) interface, which is an interface used for interacting with a programming language on a software side in a hardware description language. Other types of interface functions in hardware description languages for interacting with a programming language on the software side are also within the scope of the present invention.
The processing function is a part of the analysis module, is called by the interface function, and is used for receiving the key signal data set and storing the key signal data set into a data file.
Alternatively, the processing function is a function written in the C language. Functions written in other languages are also within the scope of the invention.
As a preferred embodiment, S500 further comprises the step of selecting a save file type:
s510, acquiring the values of the specified performance configuration parameters and the function configuration parameters. Wherein the values of the performance configuration parameters and the functional configuration parameters may be configured to be valid or invalid.
S520, selecting to store the key signal data set as a performance data file and/or an independent function data file according to the values of the performance configuration parameters and the function configuration parameters. When the performance configuration parameters are valid and the function configuration parameters are invalid, only the key signal data of the performance analysis are saved as performance data files, when the function configuration parameters are valid and the performance configuration parameters are invalid, only the key signal data of the function analysis are saved as function data files, and when the performance configuration parameters are valid and the function configuration parameters are valid, all the data in the key signal data set are saved as integrated files.
Optionally, the step of saving the file type is implemented by conditional branching or macro definition. Other implementations of the step of saving the file types are within the scope of the present invention.
It should be noted that, since the shared signal of the performance analysis and the functional analysis is collected only once, not only the collection amount of data is reduced, but also the overhead of further data communication and the overhead of storage capacity are further reduced.
And S700, performing performance analysis and/or functional analysis by the analysis module based on the data file.
The performance analysis may be performed based on a separate performance data file or may be performed based on an integrated file. Similarly, the functional analysis may be performed based on a separate functional data file or may be performed based on an integrated file.
As a preferred embodiment, S700 further includes parsing and extracting the data file by the extraction module to obtain key signal data for performance analysis and/or key signal data for functional analysis.
The data acquisition and extraction modes of performance analysis and functional analysis are unified, so that the use difficulty of a user is reduced, and the use of the user is more convenient.
It should be noted that "and/or" means that "and/or" preceding items are included only, "and/or" following items are included only, or "and/or" preceding and following items are included simultaneously.
According to the embodiment of the invention, the hardware acceleration platform is subjected to light weight processing, so that the hardware acceleration platform is focused on a sampling task, unnecessary hardware resource consumption and delay are reduced, and the sampling speed and accuracy are improved. The software side is subjected to re-quantization processing, and the performance data and the functional data can be accurately extracted after the sampling data are received, so that the subsequent analysis is more accurate and targeted. The cooperation of software and hardware not only can improve the efficiency and performance of the system, but also can provide higher flexibility and expandability, and simultaneously reduce the cost.
In summary, the method provided by the embodiment of the invention can simultaneously and uniformly acquire the key signals of the performance analysis and the function analysis without repeatedly acquiring the shared interface signals, then store the acquired key signals into the data file through the interface function and the processing function, and can not repeatedly store the data during storage, thereby reducing the expenditure of data communication and storage, and reducing the use difficulty of users due to the uniform data acquisition and extraction mode when the performance analysis and the function analysis are performed based on the data file.
Embodiments of the present invention also provide a non-transitory computer readable storage medium that may be disposed in an electronic device to store at least one instruction or at least one program for implementing one of the methods embodiments, the at least one instruction or the at least one program being loaded and executed by the processor to implement the methods provided by the embodiments described above.
Embodiments of the present invention also provide an electronic device comprising a processor and the aforementioned non-transitory computer-readable storage medium.
Embodiments of the present invention also provide a computer program product comprising program code for causing an electronic device to carry out the steps of the method according to the various exemplary embodiments of the invention as described in the specification, when said program product is run on the electronic device.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above functional units and the division of the modules are illustrated, and in practical application, the above functions may be allocated to different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to complete all or part of the functions described above.
While certain specific embodiments of the invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the invention. Those skilled in the art will also appreciate that many modifications may be made to the embodiments without departing from the scope and spirit of the invention. The scope of the present disclosure is defined by the appended claims.
Claims (8)
1. The integrated data analysis method is characterized by comprising the following steps of:
S100, acquiring all key signals used for performance analysis and functional analysis in a system to be tested to obtain a key signal set, wherein the system to be tested is a system being tested or verified;
s300, the hardware acceleration platform samples signals in the system to be tested according to the key signal set to obtain a key signal data set;
S500, the hardware acceleration platform calls a processing function in an analysis module through an interface function, wherein the processing function is used for receiving the key signal data set and storing the key signal data set into a data file;
S700, performing performance analysis and/or functional analysis by the analysis module based on the data file;
wherein S500 further comprises the step of selecting a save file type:
s510, acquiring the values of the specified performance configuration parameters and the function configuration parameters;
S520, storing the key signal data set as a performance data file and/or an independent function data file according to the values of the performance configuration parameters and the function configuration parameters, storing only the key signal data of the performance analysis as the performance data file when the performance configuration parameters are valid and the function configuration parameters are invalid, storing only the key signal data of the function analysis as the function data file when the function configuration parameters are valid and the function configuration parameters are invalid, and storing all the data in the key signal data set as an integrated file when the performance configuration parameters and the function configuration parameters are valid.
2. The method of claim 1, wherein S100 further comprises the step of selecting a key signal:
a selection signal is configured for each key signal, the current key signal is selected when the value of the selection signal is valid, and the current key signal is not selected when the value of the selection signal is invalid.
3. The method according to claim 2, wherein the step of selecting key signals is implemented by conditional branching or macro definition.
4. The method according to claim 1, wherein S700 further comprises parsing and extracting the data file by an extraction module to obtain key signal data for performance analysis and/or key signal data for functional analysis.
5. The method of claim 1, wherein the interface function is a DPI function.
6. The method of claim 1, wherein the system under test is a SOC system.
7. A non-transitory computer readable storage medium having stored therein at least one instruction or at least one program, wherein the at least one instruction or the at least one program is loaded and executed by a processor to implement the method of any one of claims 1-6.
8. An electronic device comprising a processor and the non-transitory computer readable storage medium of claim 7.
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| CN115629928A (en) * | 2022-12-22 | 2023-01-20 | 中国人民解放军国防科技大学 | A software and hardware co-verification method and system for brain-inspired processors |
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| US6856951B2 (en) * | 2002-11-15 | 2005-02-15 | Rajat Moona | Repartitioning performance estimation in a hardware-software system |
| CN101562827B (en) * | 2009-05-22 | 2011-05-25 | 中兴通讯股份有限公司 | Fault information acquisition method and system |
| US9075674B2 (en) * | 2012-12-12 | 2015-07-07 | Freescale Semiconductor, Inc. | Systems with adjustable sampling parameters and methods of their operation |
| CN110427537A (en) * | 2019-08-19 | 2019-11-08 | 宋凤玲 | A kind of method and apparatus of smart city information sharing |
| CN113094385B (en) * | 2021-03-10 | 2024-04-30 | 广州中国科学院软件应用技术研究所 | Data sharing fusion platform and method based on software defined open tool set |
| CN116756049B (en) * | 2023-08-17 | 2023-11-07 | 上海燧原科技有限公司 | Universal verification methods, devices, electronic equipment and storage media for chips |
| CN117436404A (en) * | 2023-09-28 | 2024-01-23 | 上海天数智芯半导体有限公司 | Time sequence simulation method and device, electronic equipment and storage medium |
| CN117313649B (en) * | 2023-11-28 | 2024-02-27 | 苏州元脑智能科技有限公司 | Chip simulation verification method and application device thereof |
| CN118095156B (en) * | 2024-04-29 | 2024-07-05 | 北京燧原智能科技有限公司 | Verification method, device, equipment and medium of memory management unit MMU circuit |
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