CN119173810A

CN119173810A - Display substrate, manufacturing method thereof, and display device

Info

Publication number: CN119173810A
Application number: CN202380008722.9A
Authority: CN
Inventors: 吴刘; 李永谦; 袁志东
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Priority date: 2023-04-20
Filing date: 2023-04-20
Publication date: 2024-12-20
Also published as: WO2024216585A1

Abstract

The disclosure provides a display substrate, which comprises a substrate, a conductive wiring layer and a driving functional layer, wherein the conductive wiring layer is positioned on one side of the substrate and comprises a plurality of fan-out lines, the driving functional layer is positioned on one side of the conductive wiring layer away from the substrate and comprises a plurality of sub-pixel driving circuits and a plurality of signal supply lines for providing signals for the sub-pixel driving circuits, and at least part of the signal supply lines are coupled with the corresponding fan-out lines. The disclosure also provides a preparation method of the display substrate and a display device.

Description

Display substrate, preparation method thereof and display device

Technical Field

The disclosure relates to the technical field of display, in particular to a display substrate, a preparation method thereof and a display device.

Background

With the continuous development of display technology, organic Light-Emitting Diode (OLED) display products are widely used with the advantages of high brightness, low power consumption, quick response, high definition, good flexibility, high luminous efficiency and the like. As the market of OLED display products is gradually opened, the demand of OLED special-shaped display products is also increasing.

Disclosure of Invention

In a first aspect, an embodiment of the present disclosure provides a display substrate, including:

a substrate base;

The conductive wiring layer is positioned on one side of the substrate base plate and comprises a plurality of fan-out lines;

The driving functional layer is positioned on one side of the conductive wiring layer away from the substrate base plate and comprises a plurality of sub-pixel driving circuits and a plurality of signal supply lines for providing signals for the sub-pixel driving circuits, wherein at least part of the signal supply lines are coupled with the corresponding fan-out lines.

In some embodiments, the driving functional layer comprises a buffer layer, an active layer positioned on one side of the buffer layer away from the substrate and a first source drain conductive layer positioned on one side of the active layer away from the substrate, the sub-pixel driving circuit comprises a plurality of transistors, an active pattern of the transistors is positioned on the active layer, and the signal supply line is positioned on the first source drain conductive layer;

The conductive wiring layer is located between the buffer layer and the substrate base plate.

In some embodiments, the fan-out line is in contact with the buffer layer.

In some embodiments, there is no overlap between the orthographic projection of the fan-out line on the substrate and the orthographic projection of the active pattern of the transistor on the substrate.

In some embodiments, the conductive wiring layer further includes a plurality of first connection terminals corresponding to the plurality of fan-out lines, one ends of the fan-out lines being connected to the corresponding signal supply lines through the corresponding first connection terminals.

In some embodiments, the substrate includes a display region, and a first peripheral region and a second peripheral region located at the periphery of the display region, the first peripheral region and the second peripheral region being located at opposite sides of the display region in a first direction, respectively, the second peripheral region including a binding region;

the first connection terminal is located in the first peripheral region.

In some embodiments, the signal supply line extends along the first direction.

In some embodiments, the material of the fanout line comprises a metallic material and the metallic material has a melting point greater than 580 ℃.

In some embodiments, the fanout line has a sheet resistance of 0.05 Ω/≡.

In some embodiments, the thickness of the fan-out line comprises:

in some embodiments, the plurality of signal supply lines includes a plurality of data lines;

The fan-out lines include a plurality of data fan-out lines coupled with the corresponding data lines.

In some embodiments, the plurality of signal supply lines includes a plurality of reference signal lines;

The fan-out lines include a plurality of reference fan-out lines coupled with the corresponding reference signal lines.

In some embodiments, the subpixel driving circuit includes a driving subcircuit and a light emission control subcircuit coupled;

The plurality of sub-pixel driving circuits are divided into a plurality of sub-pixel driving circuit groups, each sub-pixel driving circuit group comprises two sub-pixel driving circuits arranged along a first direction, two sub-pixel driving circuits in the same sub-pixel driving circuit group multiplex the same light-emitting control sub-circuit, and the light-emitting control sub-circuit is used for controlling the coupled two driving sub-circuits to respectively output corresponding driving signals;

The plurality of signal supply lines include a plurality of data lines extending in the first direction.

In some embodiments, two of the driving sub-circuits within a same sub-pixel driving circuit group are axisymmetrically disposed, and an axis of symmetry extends along a second direction intersecting the first direction.

In some embodiments, the substrate includes a display region within which the subpixel drive circuit is located;

Two sub-pixel driving circuits located in the same sub-pixel driving circuit group are adjacent in the first direction;

The fan-out line comprises at least one first part which is positioned in the display area and extends along a first direction, and the orthographic projection of the first part on the driving functional layer is positioned between two adjacent sub-pixel driving circuit groups along a second direction.

In some embodiments, at least a portion of the fan-out lines further include at least one second portion located within the display area and extending in a second direction, an orthographic projection of the second portion on the driving function layer being located between two of the sub-pixel driving circuit groups adjacent in the first direction.

In some embodiments, the driving sub-circuit includes a first transistor, a second transistor, a third transistor, a storage capacitor, and a driving transistor, and the light emission control sub-circuit includes a light emission control transistor;

A control electrode of the first transistor is coupled with a first scanning line, a first electrode of the first transistor is coupled with a data line, and a second electrode of the first transistor is coupled with a control electrode of the driving transistor;

a control electrode of the second transistor is coupled with a second scanning line, a first electrode of the second transistor is coupled with a reference signal line, and a second electrode of the second transistor is coupled with a control electrode of the driving transistor;

A control electrode of the third transistor is coupled with the third scanning line, a first electrode of the third transistor is coupled with the initialization signal line, and a second electrode of the third transistor is coupled with a second electrode of the driving transistor;

The control electrode of the light-emitting control transistor is coupled with the light-emitting control signal line, the first electrode of the light-emitting control transistor is coupled with the power line, and the second electrode of the light-emitting control transistor is coupled with the first electrode of the driving transistor;

The second pole of the driving transistor is coupled with the anode pattern of the corresponding light-emitting element;

The first electrode plate of the storage capacitor is coupled with the control electrode of the driving transistor, and the second electrode of the storage capacitor is coupled with the second electrode of the driving transistor.

In some embodiments, the display substrate further comprises:

the second planarization layer is positioned on one side of the driving functional layer away from the substrate base plate;

The light-emitting element layer comprises a plurality of light-emitting elements, a plurality of sub-pixel accommodating holes corresponding to the light-emitting elements one by one are formed in the pixel defining layer, the light-emitting elements are located in the corresponding sub-pixel accommodating holes, and an anode pattern of the light-emitting elements is coupled with the corresponding sub-pixel driving circuit.

In a second aspect, an embodiment of the present disclosure further provides a display device, including the display substrate provided in the first aspect.

In a third aspect, an embodiment of the present disclosure further provides a method for manufacturing a display substrate, including:

Providing a substrate;

Forming a conductive wiring layer on one side of the substrate base plate, wherein the conductive wiring layer comprises a plurality of fan-out lines;

And forming a driving functional layer on one side of the conductive wiring layer far away from the substrate base plate, wherein the driving functional layer comprises a plurality of sub-pixel driving circuits and a plurality of signal supply lines for providing signals for the sub-pixel driving circuits, and at least part of the signal supply lines are coupled with the corresponding fan-out lines.

Drawings

The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification, illustrate the disclosure and together with the description serve to explain, but do not limit the disclosure. In the drawings:

FIG. 1A is a schematic top view of a display substrate according to an embodiment of the disclosure;

FIG. 1B is a schematic cross-sectional view showing a portion of a substrate in accordance with one embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a circuit configuration of a sub-pixel driving circuit according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a circuit configuration of a subpixel driving circuit group according to an embodiment of the present disclosure;

FIG. 4 is a schematic layout view of the region S in FIG. 1A;

FIG. 5 is a schematic layout of a conductive routing layer in an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of a layout of an active layer in an embodiment of the disclosure;

FIG. 7 is a schematic layout of a first gate conductive layer according to an embodiment of the disclosure;

FIG. 8 is a schematic diagram of a layout of a second gate conductive layer in an embodiment of the disclosure;

FIG. 9 is a schematic diagram illustrating a layout of a first source-drain conductive layer according to an embodiment of the disclosure;

FIG. 10 is a schematic diagram of a layout of a second source-drain conductive layer according to an embodiment of the disclosure;

FIG. 11 is a schematic layout of a conductive routing layer and an active layer in the disclosed embodiments;

FIG. 12 is a schematic illustration of a layout of anode graphic layers in a disclosed embodiment;

FIG. 13 is a schematic diagram of a layout of a pixel defining layer in an embodiment of the disclosure;

fig. 14 is a schematic flow chart of a method for manufacturing a display substrate according to an embodiment of the disclosure.

Detailed Description

In order to enable those skilled in the art to better understand the technical scheme of the present invention, the following describes in detail a display substrate, a manufacturing method thereof and a display device provided by the present invention with reference to the accompanying drawings.

In order to enable those skilled in the art to better understand the technical solutions of the present invention, a shift register unit, a gate driving circuit, a display panel and a display device provided by the present invention are described in detail below with reference to the accompanying drawings.

The terms "first," "second," and the like, as used in embodiments of the present disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "coupled" or "connected," and the like, are not limited to physical or mechanical coupling, but may include electrical connection, whether direct or indirect.

The transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics. In this embodiment, the drain and source of each transistor may be coupled interchangeably, so that the drain and source of each transistor are virtually indistinguishable in the embodiments of the present disclosure. Here, only in order to distinguish between two electrodes of a transistor except a control electrode (i.e., a gate electrode), one of the electrodes is called a drain electrode and the other is called a source electrode. The thin film transistor adopted in the embodiment of the disclosure may be an N-type transistor or a P-type transistor. In the embodiment of the disclosure, when an N-type thin film transistor is used, the first pole may be a source electrode and the second pole may be a drain electrode. In the following embodiments, a thin film transistor is described as an example of an N-type transistor.

In the present disclosure, an "active level signal" refers to a signal that can control the transistor to be turned on after being input to the control electrode of the transistor, and a "inactive level signal" refers to a signal that can control the transistor to be turned off after being input to the control electrode of the transistor. For an N-type transistor, the high level signal is an active level signal, the low level signal is an inactive level signal, and for a P-type transistor, the low level signal is an active level signal, and the high level signal is an inactive level signal.

In the following description, a transistor will be described as an example of an N-type transistor, where an active level signal means a high level signal and an inactive level signal means a low level signal. It is conceivable that when a P-type transistor is employed, the timing variation of the control signal needs to be adjusted accordingly. Specific details are not set forth herein but are intended to be within the scope of the present disclosure.

In addition, the light emitting element in the embodiments of the present disclosure is a current driven light emitting element, and the light emitting element is exemplified as an organic light emitting diode in the embodiments of the present disclosure.

In order to realize a narrow frame or an extremely narrow frame of a product, a Fanout line in a display area (Fanout IN ACTIVE AREA, abbreviated as FIA) design is proposed in the related art, that is, a Fanout line for transmitting a signal to a signal supply line in the display area is disposed in the display area (also referred to as AA area). The FIA design is particularly suitable for use with heterogeneous displays such as hexagonal, circular, heart-shaped, etc.

In the related art, a fan-out line (also referred to as Fanout line) is designed between a sub-pixel driving circuit and a light emitting element layer including a plurality of light emitting elements. Specifically, a second source-drain conductive layer and a second planarization layer are arranged between the sub-pixel driving circuit and the light-emitting element layer, the second planarization layer is arranged between the second source-drain conductive layer and the light-emitting element layer, the second source-drain conductive layer comprises a conductive connecting part used for connecting the sub-pixel driving circuit and the light-emitting element, and a Fanout line is arranged on the second source-drain conductive layer.

Based on the foregoing, it can be seen that there is only one layer of second planarization between the Fanout line and the anode pattern layer (including the anode pattern of the plurality of light emitting elements), by which planarization is difficult to achieve, and especially for places where the Fanout line is relatively dense, the portion of the second planarization layer covering the densely distributed area of the Fanout line appears to be significantly convex upward. In this case, the anode pattern layer on the second planarizing layer is also inferior in flatness, and for example, there are different anode patterns on different planes, and there are differences in the direction perpendicular to the substrate at different positions on the side surface of the same anode pattern away from the substrate. However, the poor flatness of the anode pattern in the anode pattern layer may cause a significant metal reflection phenomenon in the anode pattern layer and uneven display of the entire light emitting element layer.

The present disclosure provides a corresponding solution for effectively improving the above-mentioned technical problem of poor flatness of the anode pattern layer due to the Fanout line.

Fig. 1A is a schematic top view of a display substrate according to an embodiment of the disclosure. FIG. 1B is a schematic cross-sectional view showing a portion of a substrate in accordance with one embodiment of the present disclosure. Fig. 2 is a schematic circuit diagram of a subpixel driving circuit according to an embodiment of the present disclosure. Fig. 3 is a schematic circuit diagram of a subpixel driving circuit group according to an embodiment of the present disclosure. Fig. 4 is a schematic layout diagram of the region S in fig. 1A. Fig. 5 is a schematic layout diagram of a conductive wiring layer in an embodiment of the disclosure. Fig. 6 is a schematic layout diagram of an active layer in an embodiment of the disclosure. Fig. 7 is a schematic layout diagram of a first gate conductive layer according to an embodiment of the disclosure. Fig. 8 is a schematic layout diagram of a second gate conductive layer according to an embodiment of the disclosure. Fig. 9 is a schematic layout diagram of a first source-drain conductive layer according to an embodiment of the disclosure. Fig. 10 is a schematic layout diagram of a second source-drain conductive layer according to an embodiment of the disclosure. Fig. 11 is a schematic layout of a conductive routing layer and an active layer in the disclosed embodiments. Fig. 12 is a schematic layout of an anode pattern layer in the disclosed embodiment. FIG. 13 is a schematic layout of a pixel defining layer in an embodiment of the disclosure. As shown in fig. 1A to 13, the display substrate includes a base substrate 1, a conductive wiring layer 2, and a driving function layer 1000.

The substrate 1 may be a flexible substrate (for example, a resin substrate) or a rigid substrate (for example, a glass substrate). The shape of the base substrate 1 may be a regular rectangle or a special shape, for example

The conductive wiring layer 2 is located at one side of the substrate base 1, and the conductive wiring layer 2 includes a plurality of fan-out lines 20. The number and position distribution of the fanout lines 20 can be designed and adjusted accordingly according to actual needs.

The driving function layer 1000 is located on a side of the conductive wiring layer 2 away from the substrate 1, and includes a plurality of sub-pixel driving circuits 100 and a plurality of signal supply lines for providing signals to the sub-pixel driving circuits 100, at least a portion of the signal supply lines being coupled with the corresponding fan-out lines 20.

In the embodiment of the disclosure, the display substrate includes a plurality of sub-pixels, and the sub-pixels include a sub-pixel driving circuit 100 and a light emitting element OLED coupled to each other, and the sub-pixel driving circuit is configured to provide a driving signal for the corresponding light emitting element OLED to drive the light emitting element OLED to emit light. The present disclosure is not limited to the specific circuit configuration of the sub-pixel driving circuit 100, and for example, 5T1C (including 5 transistors and 1 capacitor) mentioned later may be employed, and other circuit configurations may be employed. The reference hereinafter to 5T1C is only an alternative implementation in the examples of the present disclosure, which does not limit the technical solution of the present disclosure.

In the embodiment of the disclosure, the fan-out line (particularly the second source/drain conductive layer in the driving functional layer) on the side of the sub-pixel driving circuit far away from the substrate in the related art is moved down between the driving functional layer 1000 and the substrate 1, so that the film layer between the fan-out line 20 and the second planarization layer 18 is increased, the area where the fan-out line 20 is located can be planarized to a certain extent by the film layer between the fan-out line 20 and the second planarization layer 18, so as to improve the adverse effect of the fan-out line 20 on the flatness of the second planarization layer 18, and improve the overall flatness of the second planarization layer 18, and accordingly, the flatness of the anode pattern layer 8 on the second planarization layer 18 can also be effectively improved, so that the problems of obvious metal reflection phenomenon and uneven overall display of the light-emitting element layer in the anode pattern layer 8 caused by poor flatness of the anode pattern layer 8 can be effectively improved, even completely solved.

In some embodiments, the driving functional layer 1000 includes a buffer layer 11, an active layer 3 on a side of the buffer layer 11 away from the substrate 1, and a first source drain conductive layer 6 on a side of the active layer 3 away from the substrate 1, the sub-pixel driving circuit 100 includes a plurality of transistors T1 to T5, active patterns 31 to 35 of the transistors T1 to T5 are located on the active layer 3, signal supply lines are located on the first source drain conductive layer 6, and the conductive wiring layer 2 is located between the buffer layer 11 and the substrate 1.

In some embodiments, the fan-out line 20 is in contact with the buffer layer 11.

Referring to fig. 11, in some embodiments, there is no overlap between the front projection of the fanout line 20 on the substrate 1 and the front projection of the active patterns of the transistors (the active patterns 31 to 35 of the first transistor T1 to the third transistor T3, the light emission control transistor T4, and the driving transistor T5 are illustrated in fig. 11 by way of example) on the substrate 1.

In the embodiment of the disclosure, the fan-out line 20 is disposed between the buffer layer 11 and the substrate 1, and at this time, a height level difference exists between a surface of a portion of the buffer layer 11, which is far from the substrate 1, and does not cover the fan-out line 20, that is, a surface flatness of the buffer layer 11 is poor. At this time, if the active pattern of the transistor covers the level difference position, a level difference occurs in the active pattern of the transistor, which causes a problem of uneven active pattern of the transistor, and affects the electrical characteristics of the transistor, and if the portion of the fan-out line 20 is located directly above the active pattern of the transistor, the signal loaded in the fan-out line 20 affects the carrier distribution in the active pattern to a certain extent, and affects the electrical characteristics of the transistor.

In order to effectively solve the above technical problems, the technical solution of the present disclosure does not overlap the orthographic projection of the fanout line 20 on the substrate 1 and the orthographic projection of the active pattern of the transistor on the substrate 1, so that the uneven problem of the active pattern of the transistor can be effectively avoided, and the influence of the signal loaded in the fanout line 20 on the carriers in the active pattern can be avoided.

In addition, in practical application, if the conductive wiring layer 2 is too thick, obvious protrusions appear on the buffer layer 11, which is unfavorable for the subsequent process, while if the conductive wiring layer 2 is too thin, the overall resistance of the fan-out line 20 is too large, which is unfavorable for the signal transmission. Based on the dual consideration of the fabrication process and the overall resistance of the fan-out line 20, in some embodiments, the thickness of the conductive routing layer 2 is set at: For example, the number of the cells to be processed,

In some embodiments, the sheet resistance of the fan-out lines 20 is equal to or less than 0.05 Ω/≡.

In the embodiment of the disclosure, after the preparation process of the active layer 3 is completed, lattice repair is performed on the semiconductor material (for example, low-temperature polysilicon material) in the active layer 3 to repair lattice damage of the lattice of the active layer 3 caused by ion doping, repair silicon dangling bonds on the surface of the active layer 3, and activate doped ions.

A high temperature environment (typically at 580C) is created during lattice repair to avoid melting of the fanout line 20, which in some embodiments is a metallic material having a melting point greater than 580C.

Further, in order to ensure the stability of the electrical characteristics of the fanout line 20, the selected metal material should not be easily oxidized in the high temperature environment generated in the lattice repairing process, i.e. have better high temperature oxidation resistance. As an example, the material of the fanout wire adopts a molybdenum-aluminum-molybdenum three-layer metal material laminated structure (conventional metallic titanium has a high melting point but is easily oxidized at high temperature).

In some embodiments, the conductive wiring layer 2 further includes a plurality of first connection terminals 205 corresponding to the plurality of fan-out lines 20, and one end of the fan-out line 20 is connected to a corresponding signal supply line through the corresponding first connection terminal 205.

In some embodiments, the substrate 1 includes a display area 1a, and a first peripheral area 1c and a second peripheral area 1b located at the periphery of the display area 1a, the first peripheral area 1c and the second peripheral area 1b being located at opposite sides of the display area 1a in the first direction Y, respectively, the second peripheral area 1b including a binding (Bonding) area in which binding terminals are provided to bind electronic devices (e.g., a driving chip, a flexible circuit board, etc.) to the display substrate, and the first connection terminal 205 being located at the first peripheral area 1c, that is, the first connection terminal 205 being located at the opposite side of the display area 1a from the binding area.

In the embodiment of the present disclosure, one end of the fan-out line 20 is connected to the first connection terminal 205, and the other end of the fan-out line 20 is connected to a second connection terminal (not shown) located in the second peripheral area 1b, which may be a pin of a driving chip or a binding terminal in some embodiments.

In some implementations, the signal supply line extends along the first direction Y. In some embodiments, the plurality of signal supply lines includes a plurality of data lines 62, and the plurality of fan-out lines 20 includes a plurality of data fan-out lines 201-203, the data fan-out lines 20 being coupled to the corresponding data lines 62. In some embodiments, the plurality of signal supply lines includes a plurality of reference signal lines 63, and the plurality of fan-out lines 20 includes a plurality of reference fan-out lines 204, the reference fan-out lines 20 being coupled to corresponding reference signal lines 63. The detailed description will be made later in connection with specific examples.

Referring to fig. 2, 3 and 5, in some embodiments, the sub-pixel driving circuit includes a driving sub-circuit 101 and a light emission control sub-circuit 102 coupled to each other, the plurality of sub-pixel driving circuits 100 are divided into a plurality of sub-pixel driving circuit groups, each sub-pixel driving circuit group includes two sub-pixel driving circuits 100 arranged along a first direction Y, two sub-pixel driving circuits 100 located within the same sub-pixel driving circuit group multiplex the same light emission control sub-circuit 102, the light emission control sub-circuit 102 is configured to control the two coupled driving sub-circuits 101 to output corresponding driving signals, respectively, and the plurality of signal supply lines include a plurality of data lines 62, and the data lines 62 extend along the first direction Y.

In the embodiment of the disclosure, the same light-emitting control sub-circuits are multiplexed by the two sub-pixel driving circuits in the same sub-pixel driving circuit group, so that the number of the light-emitting control sub-circuits arranged on the display substrate is reduced, the layout space of each sub-pixel driving circuit group is effectively reduced, and the realization of high resolution of the display device is facilitated.

In some embodiments, two driving sub-circuits 101 within the same sub-pixel driving circuit group are axisymmetrically arranged and the symmetry axis extends along a second direction X intersecting the first direction Y. As an example, the second direction X is perpendicular to the first direction Y. In the embodiment of the disclosure, the two driving sub-circuits 101 located in the same sub-pixel driving circuit group are axisymmetrically arranged, so that the layout space occupied by the sub-pixel driving circuit group can be effectively reduced, which is beneficial to realizing high resolution of the display device.

In some embodiments, two sub-pixel driving circuits 100 adjacent in the second direction X are symmetrically disposed with the symmetry axis along the first direction Y.

In some embodiments, two sub-pixel driving circuits 100 located in the same sub-pixel driving circuit group are adjacent in the first direction Y, and the fan-out line 20 includes at least one first portion 20a located within the display area 1a and extending along the first direction Y, and the orthographic projection of the first portion 20a on the driving function layer 1000 is located between the two sub-pixel driving circuit groups adjacent in the second direction X.

In some embodiments, at least part of the fanout line 20 further comprises at least one second portion 20b located within the display area 1a and extending in the second direction X, the orthographic projection of the second portion 20b onto the driving function layer 1000 being located between two sub-pixel driving circuit groups adjacent in the first direction Y.

That is, the fan-out line 20 in the embodiment of the disclosure includes at least a portion extending along the first direction Y, and may also include a portion extending along the second direction X, and the fan-out line 20 is always located between the sub-pixel driving circuit groups, so that the interference of the signals loaded in the fan-out line 20 on the sub-pixel driving circuit 100 can be effectively avoided, so as to improve the working stability of the sub-pixel driving circuit.

In some embodiments, the driving sub-circuit 101 includes a first transistor T1, a second transistor T2, a third transistor T3, a storage capacitor Cst, and a driving transistor T5, and the emission control sub-circuit 102 includes an emission control transistor T4.

The control electrode of the first transistor T1 is coupled to the first scan line 41, the first electrode of the first transistor T1 is coupled to the data line 62, and the second electrode of the first transistor T1 is coupled to the control electrode of the driving transistor T5.

The control electrode of the second transistor T2 is coupled to the second scan line 42, the first electrode of the second transistor T2 is coupled to the reference signal line 63, and the second electrode of the second transistor T2 is coupled to the control electrode of the driving transistor T5.

The control electrode of the third transistor T3 is coupled to the third scan line 43, the first electrode of the third transistor T3 is coupled to the initialization signal line 51, and the second electrode of the third transistor T3 is coupled to the second electrode of the driving transistor T5.

The control electrode of the light emitting control transistor T4 is coupled to the light emitting control signal line 44, the first electrode of the light emitting control transistor T4 is coupled to the power line VDD, and the second electrode of the light emitting control transistor T4 is coupled to the first electrode of the driving transistor T5.

The second pole of the driving transistor T5 is coupled to the anode pattern of the corresponding light emitting element OLED.

The first electrode Cst1 of the storage capacitor Cst is coupled to the control electrode of the driving transistor T5, and the second electrode of the storage capacitor Cst is coupled to the second electrode of the driving transistor T5.

Referring to fig. 2, 12 and 13, in some embodiments, the display substrate further includes a second planarization layer 18, a light emitting element OLED layer, and a pixel defining layer 9. The second planarization layer 18 is located at a side of the driving functional layer 1000 away from the substrate 1, the light-emitting element OLED layer and the pixel defining layer 9 are located at a side of the second planarization layer 18 away from the substrate 1, the light-emitting element OLED layer includes a plurality of light-emitting elements OLED, the light-emitting elements OLED include an anode pattern 80, a light-emitting layer 19 and a cathode layer 10, and the cathode layer 10 is laid over the whole surface. The pixel defining layer 9 includes a plurality of sub-pixel receiving holes 90 in one-to-one correspondence with the light emitting elements OLED, the light emitting elements OLED (light emitting layer 19) being located in the corresponding sub-pixel receiving holes 90, the anode pattern 80 of the light emitting elements OLED being coupled with the corresponding sub-pixel driving circuit 100.

In some embodiments, the material of the anode pattern 80 may be a metal material (e.g., silver), or a stacked structure of transparent conductive materials (e.g., indium tin oxide-silver-indium tin oxide). The material of the cathode layer 10 is a transparent conductive material (e.g., indium tin oxide).

The functional layers of the display substrate in the embodiments of the present disclosure will be described in detail with reference to fig. 1B and fig. 4 to 11.

As one example, the display substrate includes a plurality of pixels arranged in an array along a first direction Y and a second direction X, each pixel including a first subpixel, a second subpixel, and a third subpixel sequentially arranged along the second direction X. The data line 62 connected to the first subpixel is a first data line 621, the data line 62 connected to the second subpixel is a second data line 622, and the data line 62 connected to the third subpixel is a third data line 623.

Referring to fig. 1B, the driving function layer 1000 includes a buffer layer 11, an active layer 3, a first gate insulating layer 12, a first gate conductive layer 4, a second gate insulating layer 13, a second gate conductive layer 5, an interlayer dielectric layer 14, a first source drain conductive layer 6, a first planarization layer 15, a first passivation layer 16, a second source drain conductive layer 7, a second passivation layer 17, and a second planarization layer 18, which are sequentially disposed away from the substrate 1.

The buffer layer 11, the first gate insulating layer 12, the second gate insulating layer 13, the interlayer dielectric layer 14, the first passivation layer 16, and the second passivation layer 17 may be made of at least one of silicon oxide and silicon nitride. The material of each of the first planarizing layer 15 and the second planarizing layer 18 may be a resin material.

Referring to fig. 5, as an example, the material of the conductive wiring layer 2 may be a molybdenum-aluminum-molybdenum three-layer metal material laminated structure. The conductive wiring layer 2 includes a first data fanout line 201 for supplying a signal to a first data line 621, a second data fanout line 202 for supplying a signal to a second data line 622, a third data fanout line 203 for supplying a signal to a third data line 623, and a reference fanout line 204 for supplying a signal to a reference signal line 63.

Based on the above, the film layer which is located between the conductive wiring layer 2 and the anode electrode layer 8 and can effectively cover the fan-out line 20 includes the buffer layer 11, the first gate insulating layer 12, the second gate insulating layer 13, the interlayer dielectric layer 14, the first planarization layer 15 and the second planarization layer 18, so that more covering film layers can better planarize the area where the fan-out line 20 is located.

Referring to fig. 6 and 11, the active layer 3 includes a first active pattern 31 of the first transistor T1, a second active pattern 32 of the second transistor T2, a third active pattern 33 of the third transistor T3, a fourth active pattern 34 of the light emission control transistor T4, and a fifth active pattern 35 of the driving transistor T5.

In some embodiments, the active layer 3 further includes a reference connection 36, the reference connection 36 extending in the second direction X, the first pole of the second transistor T2 being coupled to the reference signal line 63 through the reference connection 36.

Within the same sub-pixel driving circuit group, the two first active patterns 31 are symmetrically arranged with one symmetry axis parallel to the second direction X, the two second active patterns 32 are symmetrically arranged with one symmetry axis parallel to the second direction X, the two third active patterns 33 are symmetrically arranged with one symmetry axis parallel to the second direction X, the two fourth active patterns 34 are symmetrically arranged with one symmetry axis parallel to the second direction X, and the two fifth active patterns 35 are symmetrically arranged with one symmetry axis parallel to the second direction X. The two reference connection portions 3636 corresponding to the same sub-pixel driving circuit group are symmetrically disposed with one symmetry axis parallel to the second direction X.

In the two sub-pixel driving circuits adjacent in the second direction X, the two first active patterns 31 are symmetrically arranged with one symmetry axis parallel to the first direction Y, the two second active patterns 32 are symmetrically arranged with one symmetry axis parallel to the first direction Y, the two third active patterns 33 are symmetrically arranged with one symmetry axis parallel to the first direction Y, the two fourth active patterns 34 are symmetrically arranged with one symmetry axis parallel to the first direction Y, the two fifth active patterns 35 are symmetrically arranged with one symmetry axis parallel to the first direction Y

Referring to fig. 11, the orthographic projections of the data fan-out lines 201 to 203 and the reference fan-out line 204 in the conductive wiring layer 2 on the substrate 1 do not overlap with the orthographic projections of the active patterns 31 to 35 of the transistors in the active layer 3 on the substrate 1.

In some embodiments, the plurality of data fanout lines respectively arranged at two pixels adjacent in the second direction X are symmetrically arranged with one symmetry axis parallel to the first direction Y. Referring to fig. 4,5 and 11, each pixel unit is configured with 3 data fanout lines 201 to 203, and the 3 data fanout lines 201 to 203 configured by the pixels located at the left side in the figure and the 3 data fanout lines 201 to 203 configured by the pixels located at the right side in the same figure are symmetrical about a symmetry axis parallel to the first direction Y. More specifically, in fig. 4,5 and 11, a first data fanout line 201 is disposed in a pixel on the left side and a third data fanout line 203 is disposed in a pixel on the right side, a second data fanout line 202 is disposed in a pixel on the left side and a second data fanout line 202 is disposed in a pixel on the right side, and a third data fanout line 203 is disposed in a pixel on the left side and a first data fanout line 201 is disposed in a pixel on the right side.

Referring to fig. 7, the material of the first gate conductive layer 4 includes a metal material, for example, molybdenum. The first gate conductive layer 4 includes a first scan line 41, a second scan line 42, a third scan line 43, a light emission control signal line 44, a power connection portion, and a first plate Cst1 of a storage capacitor. The first scan line 41, the second scan line 42, the third scan line 43, the light emission control signal line 44, and the power connection portion 45 all extend in the second direction X.

The portion of the first scan line 41 overlapping the first active pattern 31 may be used as a control electrode of the first transistor T1, the portion of the second scan line 42 overlapping the second active pattern 32 may be used as a control electrode of the second transistor T2, the portion of the third scan line 43 overlapping the third active pattern 33 may be used as a control electrode of the third transistor T3, the portion of the light emission control signal line 44 overlapping the fourth active pattern 34 may be used as a control electrode of the light emission control transistor T4, and the portion of the first plate Cst1 of the storage capacitor overlapping the fifth active pattern 35 may be used as a control electrode of the driving transistor T5. The power connection portion 45 is for electrically connecting with a power line VDD formed later.

The first plates Cst1 of the two storage capacitors in the same sub-pixel driving circuit group are symmetrically arranged with one symmetry axis parallel to the second direction X. The two first scan lines 41 corresponding to the same sub-pixel driving circuit group are symmetrically arranged with one symmetry axis parallel to the second direction X, the two second scan lines 42 are symmetrically arranged with one symmetry axis parallel to the second direction X, and the two third scan lines 43 are symmetrically arranged with one symmetry axis parallel to the second direction X.

In the two sub-pixel driving circuits 100 adjacent in the second direction X, the first plates Cst1 of the two storage capacitors are symmetrically disposed with one symmetry axis parallel to the first direction Y.

Referring to fig. 8, the material of the second gate conductive layer 5 includes a metal material, for example, molybdenum. The second gate conductive layer 5 includes an initialization signal line 51 and a second plate Cst2 of the storage capacitor. The initialization signal line 51 extends in the second direction X.

The second pole plates Cst2 of the two storage capacitors in the same sub-pixel driving circuit group are symmetrically arranged with one symmetry axis parallel to the second direction X. The two reference connection portions 3636 corresponding to the same sub-pixel driving circuit group are symmetrically disposed with one symmetry axis parallel to the second direction X, and the two initialization signal lines 51 corresponding to the same sub-pixel driving circuit group are symmetrically disposed with one symmetry axis parallel to the second direction X.

In the two sub-pixel driving circuits 100 adjacent in the second direction X, the second plates Cst2 of the two storage capacitors are symmetrically disposed with one symmetry axis parallel to the first direction Y.

Referring to fig. 9, the material of the first source drain conductive layer 6 includes a metal material, for example, titanium-aluminum-titanium. The first source-drain conductive layer 6 includes a first data line 62, a second data line 62, a third data line 62, a reference signal line 63, a power line VDD, a first conductive connection portion 60, a first conductive pattern 64, a second conductive pattern 65, a third conductive pattern 66, a fourth conductive pattern 67, a fifth conductive pattern 68, and a sixth conductive pattern 69.

The first pole of the driving transistor T5 is connected with the second pole of the light emitting control transistor T4 through a first conductive pattern 64, the power supply connection part 45 is connected with the first pole of the light emitting control transistor T4 through a second conductive pattern 65, the second pole of the driving transistor T5 is connected with the second pole plate Cst2 through a third conductive pattern 66, the reference connection part 36 is connected with the first pole of the second transistor T2 through a fourth conductive pattern 67, the first pole of the third transistor T3 is connected with the initialization signal line 51 through a fifth conductive pattern 68, the second pole of the first transistor T1 is connected with the control pole of the driving transistor T5 and the second pole of the second transistor T2 through a sixth conductive pattern 69, and the second pole of the third transistor T3 is connected with the second pole plate Cst2 of the storage capacitor through the first conductive connection part 60.

Within the same sub-pixel driving circuit group 100, the two first conductive patterns 64 are symmetrically disposed with respect to one symmetry axis parallel to the second direction X, the two third conductive patterns 66 are symmetrically disposed with respect to one symmetry axis parallel to the second direction X, the two fourth conductive patterns 67 are symmetrically disposed with respect to one symmetry axis parallel to the second direction X, the two fifth conductive patterns 68 are symmetrically disposed with respect to one symmetry axis parallel to the second direction X, the two sixth conductive patterns 69 are symmetrically disposed with respect to one symmetry axis parallel to the second direction X, and the two first conductive connection portions 60 are symmetrically disposed with respect to one symmetry axis parallel to the second direction X.

In the two sub-pixel driving circuits adjacent in the second direction X, the two first conductive patterns 64 are symmetrically disposed with one symmetry axis parallel to the first direction Y, the two second conductive patterns 65 are symmetrically disposed with one symmetry axis parallel to the first direction Y, the two third conductive patterns 66 are symmetrically disposed with one symmetry axis parallel to the first direction Y, the two fourth conductive patterns 67 are symmetrically disposed with one symmetry axis parallel to the first direction Y, the two fifth conductive patterns 68 are symmetrically disposed with one symmetry axis parallel to the first direction Y, the two sixth conductive patterns 69 are symmetrically disposed with one symmetry axis parallel to the first direction Y, and the two first conductive connection portions 60 are symmetrically disposed with one symmetry axis parallel to the first direction Y.

Referring to fig. 10, the material of the second source drain conductive layer 7 includes a metal material, for example, titanium-aluminum-titanium. The second source drain conductive layer 7 includes a second conductive connection portion 70. The second pole of the third transistor T3 is connected to the anode image of the corresponding light emitting element OLED through the second conductive connection part 70.

Within the same sub-pixel driving circuit group, the two second conductive connection portions 70 are symmetrically disposed with one symmetry axis parallel to the second direction X.

In the two sub-pixel driving circuits 100 adjacent in the second direction X, the two second conductive connection portions 70 are symmetrically disposed with one symmetry axis parallel to the first direction.

Based on the same inventive concept, the embodiments of the present disclosure also provide a method for manufacturing a display substrate, which may be used to manufacture the display substrate provided in the foregoing embodiments. Fig. 14 is a schematic flow chart of a method for manufacturing a display substrate according to an embodiment of the disclosure. As shown in fig. 14, the preparation method includes:

Step S1, providing a substrate.

And S2, forming a conductive wiring layer on one side of the substrate base plate, wherein the conductive wiring layer comprises a plurality of fan-out lines.

And S3, forming a driving functional layer on one side of the conductive wiring layer far away from the substrate base plate, wherein the driving functional layer comprises a plurality of sub-pixel driving circuits and a plurality of signal supply lines for providing signals for the sub-pixel driving circuits, and at least part of the signal supply lines are coupled with the corresponding fan-out lines.

The step S3 may specifically include a step of forming a buffer layer, a step of forming an active layer, a step of forming a first gate insulating layer, a step of forming a first gate conductive layer, a step of forming a second gate insulating layer, a step of forming a second gate conductive layer, a step of forming an interlayer dielectric layer, a step of forming a first source drain conductive layer, a step of forming a first planarization layer, a step of forming a first passivation layer, a step of forming a second source drain conductive layer, a step of forming a second passivation layer, and a step of forming a second planarization layer.

For a specific description of the steps S1 to S3, reference may be made to the corresponding content in the previous embodiment, and the description is omitted here.

Based on the same inventive concept, the embodiments of the present disclosure further provide a display device, where the display device includes a display substrate, and the display substrate in the previous embodiments may be used as the display substrate, and for a specific description of the display substrate, reference may be made to the content in the previous embodiments, which is not repeated herein.

It should be noted that the display device may be any product or component with display function, such as a television, a display, a digital photo frame, a mobile phone, a tablet computer, etc., where the display device further includes a flexible circuit board, a printed circuit board, a back board, etc.

It is to be understood that the above embodiments are merely illustrative of the application of the principles of the present invention, but not in limitation thereof. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the invention, and are also considered to be within the scope of the invention.

Claims

A display substrate, comprising:

a substrate base;

The conductive wiring layer is positioned on one side of the substrate base plate and comprises a plurality of fan-out lines;

The driving functional layer is positioned on one side of the conductive wiring layer away from the substrate base plate and comprises a plurality of sub-pixel driving circuits and a plurality of signal supply lines for providing signals for the sub-pixel driving circuits, wherein at least part of the signal supply lines are coupled with the corresponding fan-out lines.
The display substrate according to claim 1, wherein the driving function layer includes a buffer layer, an active layer located on a side of the buffer layer away from the substrate, and a first source drain conductive layer located on a side of the active layer away from the substrate, the sub-pixel driving circuit includes a plurality of transistors, an active pattern of the transistors is located on the active layer, and the signal supply line is located on the first source drain conductive layer;

The conductive wiring layer is located between the buffer layer and the substrate base plate.
The display substrate of claim 2, wherein the fanout line is in contact with the buffer layer.
A display substrate according to claim 2 or 3, wherein there is no overlap of the orthographic projection of the fan-out lines on the substrate with the orthographic projection of the active pattern of transistors on the substrate.
The display substrate according to any one of claims 1 to 4, wherein the conductive wiring layer further includes a plurality of first connection terminals corresponding to a plurality of the fan-out lines, one end of the fan-out line being connected to the corresponding signal supply line through the corresponding first connection terminal.
The display substrate of claim 5, wherein the substrate comprises a display region, and a first peripheral region and a second peripheral region located at the periphery of the display region, the first peripheral region and the second peripheral region being located on opposite sides of the display region in a first direction, respectively, the second peripheral region comprising a binding region;

the first connection terminal is located in the first peripheral region.
The display substrate according to claim 6, wherein the signal supply line extends in the first direction.
The display substrate according to any one of claims 1 to 7, wherein a material of the fanout line comprises a metal material and a melting point of the metal material is greater than 580 ℃.
The display substrate according to any one of claims 1 to 8, wherein the sheet resistance of the fanout line is 0.05 Ω/≡or less.
The display substrate according to any one of claims 1 to 9, wherein a thickness of the fanout line includes:
the display substrate according to any one of claims 1 to 10, wherein the plurality of signal supply lines include a plurality of data lines;

The fan-out lines include a plurality of data fan-out lines coupled with the corresponding data lines.
The display substrate according to any one of claims 1 to 11, wherein the plurality of signal supply lines include a plurality of reference signal lines;

The fan-out lines include a plurality of reference fan-out lines coupled with the corresponding reference signal lines.
The display substrate of any one of claims 1 to 12, wherein the subpixel driving circuit comprises a driving sub-circuit and a light emission control sub-circuit coupled;

The plurality of sub-pixel driving circuits are divided into a plurality of sub-pixel driving circuit groups, each sub-pixel driving circuit group comprises two sub-pixel driving circuits arranged along a first direction, two sub-pixel driving circuits in the same sub-pixel driving circuit group multiplex the same light-emitting control sub-circuit, and the light-emitting control sub-circuit is used for controlling the coupled two driving sub-circuits to respectively output corresponding driving signals;

The plurality of signal supply lines include a plurality of data lines extending in the first direction.
A display substrate according to claim 13, wherein two of said drive sub-circuits within a same said sub-pixel drive circuit group are arranged axisymmetrically and the symmetry axis extends along a second direction intersecting said first direction.
The display substrate of claim 13 or 14, wherein the substrate comprises a display region within which the subpixel drive circuit is located;

Two sub-pixel driving circuits located in the same sub-pixel driving circuit group are adjacent in the first direction;

The fan-out line comprises at least one first part which is positioned in the display area and extends along a first direction, and the orthographic projection of the first part on the driving functional layer is positioned between two adjacent sub-pixel driving circuit groups along a second direction.
The display substrate of claim 15, wherein at least a portion of the fan-out lines further comprise at least one second portion located within the display area and extending in a second direction, an orthographic projection of the second portion on the driving functional layer being located between two of the sub-pixel driving circuit groups adjacent in the first direction.
The display substrate according to any one of claims 13 to 16, wherein the driving sub-circuit includes a first transistor, a second transistor, a third transistor, a storage capacitor, and a driving transistor, and the light emission control sub-circuit includes a light emission control transistor;

A control electrode of the first transistor is coupled with a first scanning line, a first electrode of the first transistor is coupled with a data line, and a second electrode of the first transistor is coupled with a control electrode of the driving transistor;

a control electrode of the second transistor is coupled with a second scanning line, a first electrode of the second transistor is coupled with a reference signal line, and a second electrode of the second transistor is coupled with a control electrode of the driving transistor;

A control electrode of the third transistor is coupled with the third scanning line, a first electrode of the third transistor is coupled with the initialization signal line, and a second electrode of the third transistor is coupled with a second electrode of the driving transistor;

The control electrode of the light-emitting control transistor is coupled with the light-emitting control signal line, the first electrode of the light-emitting control transistor is coupled with the power line, and the second electrode of the light-emitting control transistor is coupled with the first electrode of the driving transistor;

The second pole of the driving transistor is coupled with the anode pattern of the corresponding light-emitting element;

The first electrode plate of the storage capacitor is coupled with the control electrode of the driving transistor, and the second electrode of the storage capacitor is coupled with the second electrode of the driving transistor.
The display substrate of any one of claims 1 to 17, further comprising:

the second planarization layer is positioned on one side of the driving functional layer away from the substrate base plate;

The light-emitting element layer comprises a plurality of light-emitting elements, a plurality of sub-pixel accommodating holes corresponding to the light-emitting elements one by one are formed in the pixel defining layer, the light-emitting elements are located in the corresponding sub-pixel accommodating holes, and an anode pattern of the light-emitting elements is coupled with the corresponding sub-pixel driving circuit.
A display device comprising the display substrate according to any one of claims 1 to 18.
A method of manufacturing the display substrate according to any one of claims 1 to 18, comprising:

Providing a substrate;

Forming a conductive wiring layer on one side of the substrate base plate, wherein the conductive wiring layer comprises a plurality of fan-out lines;

And forming a driving functional layer on one side of the conductive wiring layer far away from the substrate base plate, wherein the driving functional layer comprises a plurality of sub-pixel driving circuits and a plurality of signal supply lines for providing signals for the sub-pixel driving circuits, and at least part of the signal supply lines are coupled with the corresponding fan-out lines.