CN119170641A - A heterogeneous integrated N-well superjunction silicon carbide MOSFET structure and its preparation method - Google Patents
A heterogeneous integrated N-well superjunction silicon carbide MOSFET structure and its preparation method Download PDFInfo
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Abstract
本发明涉及一种异质集成N阱的超结碳化硅MOSFET结构及其制备方法，该结构包括：第一导电类型的半导体衬底；形成于所述半导体衬底上方的第一导电类型的第一柱区和第二导电类型的第二柱区，所述第一柱区和所述第二柱区相互交错，形成超结结构。本发明的超结结构与普通的超结结构不同，普通的超结结构需要考虑器件在JFET‑沟道‑Pwell三个部分的导通和耗尽的折中关系，但本发明的超结结构可以完全近似为P柱和N柱的浓度和宽度的设计，在特定P/N柱的浓度下，器件中的P+、Pwell区域可以完全被P柱代替。
The present invention relates to a heterogeneous integrated N-well superjunction silicon carbide MOSFET structure and a preparation method thereof, the structure comprising: a semiconductor substrate of a first conductivity type; a first column region of the first conductivity type and a second column region of a second conductivity type formed above the semiconductor substrate, the first column region and the second column region interlaced with each other to form a superjunction structure. The superjunction structure of the present invention is different from an ordinary superjunction structure. An ordinary superjunction structure needs to consider the compromise relationship between conduction and depletion of the device in the three parts of JFET-channel-Pwell, but the superjunction structure of the present invention can be completely approximated to the design of the concentration and width of the P column and the N column. At a specific P/N column concentration, the P+ and Pwell regions in the device can be completely replaced by the P column.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a heterojunction silicon carbide MOSFET structure of a heterogeneous integrated N well and a preparation method thereof.
Background
Compared with the traditional silicon device, the silicon carbide (Si l i con Carbide) high-voltage power device has more excellent electrothermal performance and can normally work in harsh environments, so that the silicon carbide (Si l i con Carbide) high-voltage power device has wide application prospect in the fields of photovoltaic power generation, electric automobiles, aerospace, aviation and the like.
For silicon carbide MOSFET devices, the continuous reduction of specific on-resistance is currently the main direction of development by shrinking cell size and improving the process. However, the technology difficulty and cost of cell size miniaturization and advanced process development are rapidly increased due to the limitation of the characteristic process of the power device. Meanwhile, the on-resistance and the blocking voltage of the device have the problem of one-dimensional limit, namely, as the blocking voltage of the device is increased, the doping concentration of the drift region is reduced and the thickness is increased, so that the on-resistance of the device is increased sharply. In order to break through the one-dimensional limit of the power semiconductor device, a super junction structure can be constructed by adopting a charge balance principle, so that the contradiction between the on-resistance and the blocking voltage of the S iC MOSFET device is greatly optimized.
Currently, silicon carbide MOSFET devices exist in three technical routes:
(1) The planar gate silicon carbide MOSFET has the characteristic of high reliability, is a silicon carbide power switch device which is mainstream in the market, but has a certain bottleneck in terms of cell miniaturization;
(2) The trench gate silicon carbide MOSFET has great advantages in the aspect of realizing the miniaturization of the cell size, but the high strength of the gate oxide electric field at the bottom of the trench brings serious danger to the reliability of the device;
(3) The super junction silicon carbide MOSFET realizes the reduction of on-resistance while maintaining high voltage by alternately arranging P-type and N-type doped regions in a Si C matrix, is suitable for high-energy-efficiency and high-power-density fast switching application, but has some problems of reverse current and reverse recovery time of an internal diode due to larger pn junction area.
Disclosure of Invention
Aiming at the defects, the invention provides a heterojunction silicon carbide MOSFET structure of a heterogeneous integrated N well and a preparation method thereof, so as to break through the performance limit of the traditional silicon carbide MOSFET.
In order to solve the technical problems, the invention adopts the following technical scheme:
a heterojunction silicon carbide MOSFET structure of a hetero-integrated N-well, comprising:
A semiconductor substrate of a first conductivity type;
a first column region of a first conductivity type and a second column region of a second conductivity type formed over the semiconductor substrate, the first column region and the second column region being staggered with each other to form a superjunction structure;
A shielding region is formed on the surface of the second column region, a first groove is formed in the shielding region, a source region of a first conductivity type is formed in the first groove, and the source region is contacted with the first column region to form a heterojunction structure;
forming source metal above the first column region and the second column region, wherein the source metal is in contact with the shielding region and part of the source region;
A grid structure is formed between the first column region, the second column region and the source metal, and the grid structure is contacted with part of the source region and part of the second column region;
Drain metal is formed under the semiconductor substrate.
Further, the first column region comprises a drift region and a carrier storage region which are sequentially arranged from bottom to top.
Further, the shielding region and the source region are coated with a well region of a second conductivity type, and the side surface of the well region extends to the first column region;
The surface of the well region is spaced from the surface of the first column region to form a channel, the carrier storage region and the source region are contacted through the channel to form a heterojunction, the surface energy band of the carrier storage region can be adjusted by applying voltage to the gate structure to enable the carrier storage region and the source region to be conducted, or the surface of the well region is not spaced from the surface of the first column region, namely the channel is not formed.
Further, the gate structure comprises gate oxide and a polysilicon gate, wherein the gate oxide is formed on the surfaces of the first column region, the second column region and the source region, the gate oxide is in contact with the first column region, the second column region and the source region, and the polysilicon gate is formed on the surface of the gate oxide.
Further, the gate structure further comprises an interlayer dielectric formed between the polysilicon gate and the source metal.
Further, an insulating layer is arranged between the source metal and the first column region.
Further, the first conductivity type is N-type, the second conductivity type is P-type, and the shielding region is p+ region.
Further, the preparation materials of the first column region and the second column region are silicon carbide, and the preparation materials of the source region are polysilicon.
A preparation method of a heterojunction silicon carbide MOSFET of a heterogeneous integrated N well comprises the following steps:
step S1, forming silicon carbide of a first conductivity type on a semiconductor substrate of the first conductivity type;
Step S2, etching on the silicon carbide to form a second groove;
s3, forming silicon carbide of a second conductivity type in the second groove to obtain a first column region and a second column region, and forming a super junction structure;
S4, forming a shielding region of a second conductivity type on the second column region through an ion implantation process, and forming a carrier storage region on the second column region;
step S5, etching the surface of the shielding region to form a first groove, and filling polysilicon of a first conductivity type in the first groove to obtain a source region;
S6, performing thermal oxidation above the source region and the second column region to form gate oxide;
Step S7, depositing a polysilicon gate and an interlayer medium above the gate oxide to form a MOS structure;
S8, depositing source metal in the area between adjacent polysilicon gates, and enabling the source metal to be in contact with the source area;
Step S9, forming a grid hole;
Step S10, depositing a layer of thick source metal above the interlayer dielectric to form a source structure;
Step S11, drain metal is formed below the semiconductor substrate.
Further, before the step S4, the method further includes the following steps:
and S3.5, implanting ions of the first conductivity type into the surface of the first column region, and performing high-temperature annealing and activation to form a well region with the second conductivity type on the first column region.
After the technical scheme is adopted, compared with the prior art, the invention has the following advantages:
1. The super junction structure is different from a common super junction structure, and the common super junction structure needs to consider the trade-off relation of the conduction and the exhaustion of the device in the JFET-channel-Pwe l l parts, but the super junction structure can be completely similar to the design of the concentration and the width of a P column and an N column, and the P+ Pwe l l region in the device can be completely replaced by the P column under the concentration of a specific P/N column;
2. the grid electrode design of the invention can be shorter than that of a common split grid, and the strong electric field of the JFET region needs to be considered in the common split grid structure, but the grid electrode structure of the invention can reduce the influence of the strong electric field of the JFET by reducing the cell size;
3. The side wall of the source region (namely the side wall of the first groove) is contacted with the second column region to form a heterojunction, so that a channel can be shortened or omitted to reduce the cell size, and meanwhile, an N-type accumulation type channel is adopted to replace an inversion type channel, so that the channel mobility is greatly improved, and the device is greatly reduced in specific on-resistance;
When the device is blocked in the forward direction, the leakage current of the device can be reduced by combining the protection effect of the shielding region and the well region, and when the device is conducted in the reverse direction, the voltage drop of the heterojunction in the forward direction is lower, the reverse conduction loss of the device can be greatly reduced, bipolar degradation caused by the conduction of the body diode is inhibited, meanwhile, the excessive carriers stored by the heterojunction are less, and the reverse recovery characteristic of the device is better;
4. The invention can control the height of the heterojunction barrier by utilizing the grid electrode, and realize the on and off of the regulating and controlling device;
5. according to the invention, a P well can be omitted as required, the bottom of the source region is shielded and protected by adopting the P+ region, meanwhile, the parasitic NPN transistor can be greatly reduced to be started by completely surrounding the source region by P+, and the reliability of the device is improved;
6. The preparation method of the invention is compatible with the preparation process of the traditional planar gate silicon carbide MOSFET device.
The invention will now be described in detail with reference to the drawings and examples.
Drawings
Fig. 1 is a device structure diagram of an embodiment of the present invention.
In the drawings, the list of components represented by the various numbers is as follows:
1. Semiconductor substrate, 2, first column region, 21, drift region, 22, carrier storage region, 3, second column region, 41, shielding region, 42, first trench, 43, source region, 44, well region, 45, channel, 5, source metal, 51, insulating layer, 6, gate structure, 61, gate oxide, 62, polysilicon gate, 63, interlayer dielectric, 64, gate dielectric, 7, drain metal
Detailed Description
The principles and features of the present invention are described below with reference to the drawings, the examples are illustrated for the purpose of illustrating the invention and are not to be construed as limiting the scope of the invention.
In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, merely to facilitate description of the present invention and simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention.
Embodiment one:
As shown in fig. 1, a heterojunction silicon carbide MOSFET structure of a hetero-integrated N-well, comprising:
an N-type semiconductor substrate 1.
The first column region 2 and the second column region 3 are formed on the semiconductor substrate 1, the first column region 2 and the second column region 3 are arranged in a staggered mode to form a super junction structure, the first column region 2 is made of N-type silicon carbide, and the second column region 3 is made of P-type silicon carbide;
after forming N-type silicon carbide on the semiconductor substrate 1, etching a second groove on the surface of the semiconductor substrate, enabling the second groove to penetrate through the back surface of the N-type silicon carbide, and then epitaxially growing P-type silicon carbide (P column) in the second groove, so that a super junction structure is formed;
the first column region 2 includes a drift region 21 and a carrier storage region 22, which are sequentially arranged from bottom to top.
A shielding region 41 is formed above the second column region 3, the shielding region 41 is a P+ region, a first groove 42 is etched on the surface of the second column region 41, N-type polysilicon is filled in the first groove 42, so that a source region 43 is formed in the first groove 42, and the shielding region 41 is coated on the outer side of the first groove 42 to form shielding protection;
the side wall of the first trench 42 contacts the first column region 2, so that the N-type polysilicon contacts the N-type silicon carbide, forming a heterojunction;
The heterojunction formed by the N-type polysilicon and the N-type silicon carbide has a certain barrier height, so that the device is in a normally-off state when no grid voltage is applied;
When a positive voltage exceeding a threshold voltage is applied to the gate electrode, the barrier height of silicon carbide in the heterojunction is lowered, the silicon carbide MOSFET device is turned on, and electrons in the source region 43 enter the drain after passing through the channel 45, the carrier storage region 22, the drift region 21, and the semiconductor substrate 1;
when the gate voltage is lower than the device threshold voltage, the silicon carbide MOSFET device is turned off;
when high voltage is applied to the drain electrode of the device, PN junctions formed by the P well region 44, the P+ shielding region 41 and the N-type drift region 21 are reversely biased to bear blocking voltage, and meanwhile, the reversely biased heterojunction can also reduce leakage current of the device;
When the drain and source of the device bear reverse voltage, the heterojunction formed by the N-type polycrystalline silicon and the N-type silicon carbide is conducted forward, the device conducts reverse current, the reverse conduction voltage drop of the silicon carbide MOSFET device is lower due to the fact that the forward conduction voltage drop of the heterojunction is lower, bipolar degradation caused by the conduction of the body diode can be simultaneously restrained, and the reverse recovery characteristic of the device is better due to the fact that the heterojunction formed by the N-type polycrystalline silicon and the N-type silicon carbide has single polarity (only electrons work as carriers).
The shielding region 41 and the outer side of the first groove 42 are coated with a P well region 44, and the well region 44 and the shielding region 41 are sequentially coated on the outer side of the first groove 42 so as to shield and protect N-type polycrystalline silicon in the first groove 42;
the well region 44 and the shielding region 41 surround the N-type polysilicon to form shielding protection, the upper surface of the well region 44 is spaced apart from the upper surface of the first pillar region 2 by a distance that is transverse to form a channel 45 of the silicon carbide MOSFET device, and the N-type polysilicon and the N-type silicon carbide form a heterojunction, so that the device is in a normally-off state when no gate voltage is applied.
The structure utilizes the method of controlling the height of the heterojunction barrier by the grid electrode to realize the control of the on and off of the MOSFET device, can greatly shorten or remove the channel in the traditional planar grid structure, can adopt the accumulation type channel to replace the inversion type channel in the traditional structure, improves the mobility of the channel and reduces the specific on-resistance of the device.
A source metal 5 is formed above the first column region 2 and the second column region 3, an insulating layer 51 is disposed between the source metal 5 and the first column region 2, the insulating layer 51 is an sio 2 film, and the insulating layer 51 is used for preventing the short circuit between the first column region 2 and the source metal 5.
A gate structure 6 is formed between the first and second column regions 2 and 3 and the source metal 5, the gate structure 6 includes a gate oxide 61, a polysilicon gate 62 and an interlayer dielectric 63, the gate oxide 61 is formed on the surfaces of the first column region 2 and the source region 43 and contacts the first column region 2 and the source region 43, the polysilicon gate 62 is formed on the surface of the gate oxide 61 (the gate dielectric 64 may be deposited between the gate oxide 61 and the polysilicon gate 62, or may be omitted), and the interlayer dielectric 63 is formed on the side surfaces and the top surface of the polysilicon gate 62.
In this embodiment, the N-type silicon carbide is actually only required to provide a longitudinal voltage in the gate region, so that the band bending of the N-type silicon carbide is smaller than or equal to the band of the heterojunction under the gate voltage. The length of the gate can be reduced from that of the conventional structure to that of the N-type silicon carbide band bending conduction device in the heterojunction in theory. The design can greatly reduce the grid-drain capacitance of the device and improve the switching characteristic of the device.
A drain metal 7 is formed under the semiconductor substrate 1.
A preparation method of a heterojunction silicon carbide MOSFET of a heterogeneous integrated N well comprises the following steps:
(1) Forming N-type silicon carbide on the N-type semiconductor substrate 1 to obtain a drift region 21 of the same conductivity type as the semiconductor substrate 1;
(2) Etching a second groove on the N-type silicon carbide, wherein the bottom end of the second groove penetrates through the N-type silicon carbide;
(3) Epitaxially growing P-type silicon carbide in the second groove to form a first column region 2 and a second column region 3, namely an N column and a P column, so as to form a super junction structure;
(4) Ion implantation, high temperature annealing and activation are adopted to form a P well region 44 on the first column region 2;
(5) A carrier storage region 22 is formed on the surface of the first column region 2 and a shielding region 41 is formed on the surface of the second column region 3 by an ion implantation process;
(6) Etching a first trench 42 in the shielding region 41, and filling N-type polysilicon in the first trench 42 to form a source region 43;
(7) Forming a thin gate oxide 61 above the source region 43 and the second column region 3 by a thermal oxidation process, wherein the gate oxide 61 is in contact with part of the second column region 3 and part of the source region 43;
(8) Depositing a high-k dielectric such as Al 2O3 over the gate oxide 61 to form a layer of gate dielectric 64 (this step and this layer may be omitted as desired)
(9) A polysilicon gate 62 and an interlayer dielectric 63 are deposited above the gate dielectric 64 or the gate oxide 61 to form a MOS structure;
(10) Depositing source metal 5 in the regions between adjacent polysilicon gates 62 and contacting source metal 5 with source region 43;
(11) A gate opening;
(12) A layer of thick source metal 5 is deposited above the polysilicon gate 62 (interlayer dielectric) to form a source structure;
(13) Forming TEOS, PI and other surface protection structures;
(14) Thinning the back surface of the semiconductor substrate 1;
(15) A drain metal 7 is formed on the back surface of the semiconductor substrate 1 to form a drain structure.
Embodiment two:
In this embodiment, the well region 44 is omitted, and step (4) in the above-described manufacturing process is omitted.
Well region 44 may be removed without reserving the channel to reduce the reticle and an ion implantation process. In this case, the shielding region 41 (p+ region) is directly used to form shielding protection for the N-type polysilicon in the first trench 42, and the p+ region forms full-surrounding protection for the N-type polysilicon, so that the p+ region has a higher concentration, and the parasitic NPN transistor in the silicon carbide MOSFET device can be greatly suppressed, thereby improving the reliability of the device.
The foregoing is illustrative of the best mode of carrying out the invention, and is not presented in any detail as is known to those of ordinary skill in the art. The protection scope of the invention is defined by the claims, and any equivalent transformation based on the technical teaching of the invention is also within the protection scope of the invention.
Claims (10)
1. A heterojunction silicon carbide MOSFET structure of a hetero-integrated N-well, comprising:
a semiconductor substrate (1) of a first conductivity type;
A first column region (2) of a first conductivity type and a second column region (3) of a second conductivity type formed above the semiconductor substrate (1), the first column region (2) and the second column region (3) being staggered with each other to form a superjunction structure;
A shielding region (41) is formed on the surface of the second column region (3), a first groove (42) is formed in the shielding region (41), a source region (43) of a first conductivity type is formed in the first groove (42), and the source region (43) is contacted with the first column region (2) to form a heterojunction structure;
a source metal (5) is formed above the first column region (2) and the second column region (3), and the source metal (5) is in contact with the shielding region (41) and part of the source region (43);
a grid structure (6) is formed between the first column region (2) and the second column region (3) and the source metal (5), and the grid structure (6) is contacted with part of the source region (43) and part of the first column region (2);
a drain metal (7) is formed below the semiconductor substrate (1).
2. The heterojunction silicon carbide MOSFET structure of a hetero-integrated N-well according to claim 1, wherein the first pillar region (2) comprises a drift region (21) and a carrier storage region (22) arranged in sequence from bottom to top.
3. The heterojunction silicon carbide MOSFET structure of a hetero-integrated N-well according to claim 2, characterized in that the outer sides of the shielding region (41) and the source region (43) are clad with a well region (44) of the second conductivity type, the sides of the well region (44) extending to the first pillar region (2);
the surface of the well region (44) is spaced from the surface of the first column region (2), a channel (45) is formed at the interval, the carrier storage region (22) and the source region (43) are contacted through the channel (45) to form a heterojunction, the surface energy band of the carrier storage region (22) can be adjusted by applying voltage to the gate structure (6) so as to enable the carrier storage region (22) and the source region (43) to be conducted, or the surface of the well region (44) is not spaced from the surface of the first column region (2), namely, the channel (45) is not formed.
4. The heterojunction silicon carbide MOSFET structure of a hetero-integrated N-well of claim 1 wherein the gate structure (6) comprises a gate oxide (61) and a polysilicon gate (62), the gate oxide (61) being formed on the surfaces of the first pillar region (2), the second pillar region (3) and the source region (43), the gate oxide (61) being in contact with the first pillar region (2), the second pillar region (3) and the source region (43), the polysilicon gate (62) being formed on the surface of the gate oxide (61).
5. The heterojunction silicon carbide MOSFET structure of a hetero-integrated N-well of claim 4 wherein the gate structure (6) further comprises an interlayer dielectric (63), the interlayer dielectric (63) being formed between the polysilicon gate (62) and the source metal (5).
6. The heterojunction silicon carbide MOSFET structure of a hetero-integrated N-well according to claim 1, characterized in that an insulating layer (51) is provided between the source metal (5) and the first pillar region (2).
7. The heterojunction silicon carbide MOSFET structure of any one of claims 1-6, wherein the first conductivity type is N-type, the second conductivity type is P-type, and the shielding region (41) is a p+ region.
8. The heterojunction silicon carbide MOSFET structure of a hetero-integrated N-well as claimed in any one of claims 1 to 6, wherein the preparation material of said first pillar region (2) and said second pillar region (3) is silicon carbide and the preparation material of said source region (43) is polysilicon.
9. The preparation method of the heterojunction silicon carbide MOSFET of the heterogeneous integrated N well is characterized by comprising the following steps of:
Step S1, forming silicon carbide of a first conductivity type on a semiconductor substrate (1) of the first conductivity type;
Step S2, etching on the silicon carbide to form a second groove;
S3, forming silicon carbide of a second conductivity type in the second groove to obtain a first column region (2) and a second column region (3), and forming a super junction structure;
s4, forming a shielding region (41) of a second conductivity type on the second column region (3) through an ion implantation process, and forming a carrier storage region (22) on the second column region (3);
s5, etching a first groove (42) on the surface of the shielding region (41), and filling polysilicon of a first conductivity type in the first groove (42) to obtain a source region (43);
step S6, forming gate oxide (61) by thermal oxidation above the source region (43) and the second column region (3);
step S7, a polysilicon gate (62) and an interlayer medium (63) are deposited above the gate oxide (61) to form a MOS structure;
step S8, depositing source metal (5) in the area between the adjacent polysilicon gates (62), and enabling the source metal (5) to be in contact with the source area (43);
Step S9, forming a grid hole;
Step S10, depositing a layer of thick source metal (5) above the interlayer medium (63) to form a source structure;
Step S11, forming a drain metal (7) under the semiconductor substrate (1).
10. The method for fabricating a heterojunction silicon carbide MOSFET with a heterogeneous integrated N-well as claimed in claim 9, further comprising the following steps before said step S4:
Step S3.5, implanting ions of the first conductivity type into the surface of the first column region (2), and performing high-temperature annealing and activation to form a well region (44) of the second conductivity type on the first column region (2).
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