CN119155143A - DFE simplified parallel implementation circuit and method - Google Patents
DFE simplified parallel implementation circuit and method Download PDFInfo
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- CN119155143A CN119155143A CN202411643984.5A CN202411643984A CN119155143A CN 119155143 A CN119155143 A CN 119155143A CN 202411643984 A CN202411643984 A CN 202411643984A CN 119155143 A CN119155143 A CN 119155143A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
- H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
- H04L25/03057—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure
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Abstract
本发明提供一种DFE简化并行实现电路及方法，属于高速光通信技术领域，包括前向反馈均衡器FFE、判决反馈均衡器DFE、判决器以及控制模块，还包括一预判决电路模块，所述前向反馈均衡器FFE、预判决电路模块、判决反馈均衡器DFE、判决器依次连接，所述判决器的输出同时作为所述预判决电路模块的输入进行连接，所述判决反馈均衡器与所述控制模块连接。通过本发明对于每个PAM4符号，由原来的4路预处理再4选1变为2路预处理后2选1，简化DFE并行架构的实现复杂度，减少资源，缓解时序压力。同时，对于N抽头DFE，预处理运算的数量由4N减少为2N，大大减少了实现复杂度，同样资源下可实现更多抽头DFE。
The present invention provides a DFE simplified parallel implementation circuit and method, belonging to the field of high-speed optical communication technology, including a forward feedback equalizer FFE, a decision feedback equalizer DFE, a decision device and a control module, and also includes a pre-decision circuit module, wherein the forward feedback equalizer FFE, the pre-decision circuit module, the decision feedback equalizer DFE, and the decision device are connected in sequence, and the output of the decision device is also connected as the input of the pre-decision circuit module, and the decision feedback equalizer is connected to the control module. Through the present invention, for each PAM4 symbol, the original 4-way preprocessing and then 4-choose-1 is changed to 2-way preprocessing and then 2-choose-1, which simplifies the implementation complexity of the DFE parallel architecture, reduces resources, and alleviates timing pressure. At the same time, for an N-tap DFE, the number of preprocessing operations is reduced from 4 N to 2 N , which greatly reduces the implementation complexity, and more tap DFEs can be implemented under the same resources.
Description
Technical Field
The invention belongs to the technical field of high-speed optical communication, and particularly relates to a DFE simplified parallel implementation circuit and a method.
Background
Serializer and deserializer (Serializer and Deserializer, serDes) technology is mainly used to convert between parallel data and serial data in high-speed communication systems. SerDes systems typically transmit through a controlled impedance transmission line between a transmitting end and a receiving end. The SerDes system includes parallel-to-serial and serial-to-parallel data conversion, an impedance matching circuit, and a clock data recovery function.
In high-speed SerDes systems, the signal is severely corrupted by non-ideal characteristics of the channel, and thus equalization techniques are also introduced to counteract the non-ideal effects of the channel. A common equalization technique at the transmitting end is to add a fixed tap coefficient to the feedforward equalizer (Feed Forward Equalizer, FFE) to pre-distort the signal. The equalization function of the receiving end is similar to that of the transmitting end, and a combination of a plurality of equalization modules such as a Continuous Time Linear Equalizer (CTLE), a receiving end FFE, a decision feedback equalizer (Decision Feedback Equalizer, DFE) and the like is generally required.
In high-speed transmission, a parallel architecture is generally adopted to increase the data processing speed. Because the DFE feedback branch has very high requirement on time sequence, special design is often needed in the parallel implementation process, in order to realize parallel processing of DFE in the prior art, all possible 4 decision values of PAM4 are usually subjected to multiplication, addition and decision preprocessing in advance to obtain 4 output decision values, and an accurate decision value is obtained through 4-choice 1 recursion, but the algorithm is based on the mode of area time change, the operation which only needs to be calculated once originally needs to be calculated for 4 times at the same time, more resources are consumed, and more resources are used to change time, so that parallel processing is realized.
Disclosure of Invention
The invention aims to provide a DFE simplified parallel implementation circuit and a method thereof, which are used for solving the technical problem that more resources are used for replacing time in the parallel implementation process in the background technology.
In order to achieve the above purpose, the present invention provides the following technical solutions:
The DFE simplified parallel implementation circuit comprises a forward feedback equalizer FFE, a decision equalizer DFE, a decision device and a control module, and further comprises a pre-decision circuit module, wherein the forward feedback equalizer FFE, the pre-decision circuit module, the decision equalizer DFE and the decision device are sequentially connected, the output of the decision device is simultaneously used as the input of the pre-decision circuit module to be connected, and the decision feedback equalizer is connected with the control module.
Further, ideal values v0, v1, v2 and v3 obtained by convergence in the decider correspond to decision values-3, -1, 1 and 3 corresponding to 4 signal levels 00, 01, 10 and 11 of the PAM4 signal respectively, input signals x i (n) and v1 and v2 are compared to decide one of 3 areas, each area selects two most probable decision values as input of the next path to be preprocessed, and one of two preprocessed output results is recursively selected through final decision values.
Further, when the input signal x i (n) is not less than v2, the output of 3, i+1 paths of selection pre-selection decision values 3 is actually output, the output of 1, -3, i+1 paths of selection pre-selection decision values 1 is actually output, when the input signal v1< x i (n) is not less than v2, the output of 3, 1, i+1 paths of selection pre-selection decision values 1 is actually output, the output of-1, -3, i+1 paths of selection pre-selection decision values-1 is actually output, and when the input signal x i (n) is not more than v1, the output of 3, 1, -1, i+1 paths of selection pre-selection decision values-1 is actually output, the output of-3, i+1 paths of selection decision values-3 is actually output.
The invention further provides a method for realizing the simplified parallel of the DFE, which is based on the simplified parallel of the DFE and comprises the steps of starting the FFE and the decision device, starting the pre-decision circuit module and the DFE after the coefficients of the FFE and the decision device are converged, and reporting the DFE coefficients of the DFE to the control module after the coefficients of the FFE and the decision device are converged by a self-adaptive algorithm.
The invention has the following beneficial effects:
1. Simple pre-judgment is carried out on the input data of the DFE, the most probable two judgment values are selected from all the original four judgment values to replace the two judgment values, and finally the final output is selected after the two-choice one-recurrence. The parallel implementation architecture of the DFE is greatly simplified, because the input possibility is reduced, the processing complexity is reduced, and the occupation of resources is reduced.
2. After the FFE and the ideal level of the decision device are converged, the DFE is started, the decision classification is carried out on the ideal value converged by the decision device in advance, and the ideal value fluctuates in a smaller range after being converged, so that the feedback loop is relatively stable, the requirement on the time sequence is not high, and the time sequence pressure is relieved.
3. After the pre-judgment, only two pre-processing results are provided, all 4 possibilities are mapped to two alternative results according to the nearby principle, and the two alternative results are processed after the output judgment value of the previous symbol is finally obtained, so that the generation of error codes is reduced to the greatest extent, and the accuracy of data transmission is improved.
4. For the N-tap DFE, and the like, each tap correspondingly inputs and selects the most possible two decision values to perform preprocessing, the number of required preprocessing operations is reduced from 4 N to 2 N, the implementation complexity is greatly reduced, more tap DFEs can be realized under the same resource, and the performance and the flexibility of the system are improved.
5. The coefficients of the DFE are detected at intervals. If the coefficient is too large, reporting to the control module. The control module prompts the risk and processes the risk by uniformly coordinating the balancing capacity distribution of a plurality of balancing modules in the system. This ensures the stability and reliability of the system.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a block diagram of digital equalization at the receiving end of a prior art SerDes system;
FIG. 2 is a schematic diagram of a prior art DFE parallel implementation circuit;
FIG. 3 (a) is a block diagram of each preprocessing circuit of a prior art DFE parallel implementation circuit;
fig. 3 (b) is a block diagram of a prior art DFE parallel implemented circuit 4 option 1 recursion circuit;
FIG. 4 is a block diagram of a simplified parallel implementation circuit of the DFE of the present invention;
FIG. 5 is a schematic diagram of a pre-decision implementation circuit of the present invention;
FIG. 6 (a) is a block diagram of each preprocessing circuit of the DFE simplified parallel implementation circuit of the present invention;
FIG. 6 (b) is a block diagram of a DFE simplified parallel implementation circuit 2 option 1 recursion circuit of the present invention;
Fig. 7 is a flow chart of a simplified parallel implementation method of DFE according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without undue burden, are within the scope of the invention.
Four-level pulse amplitude modulation (4-Level Pulse Amplitude Modulation, PAM 4) techniques are commonly employed in high-speed SerDes systems. Using four different signal levels to represent 00, 01, 10, 11, 2 bits of information can be transmitted per cycle, whereas conventional two-level Non-Return-to-Zero (NRZ) signal techniques can only transmit 1 bit of information per cycle. Thus, PAM4 has twice the bit rate of the NRZ signal at the same baud rate, which makes PAM4 more efficient and cost-effective to transmit in high-speed data communication.
Digital domain equalization at the receiving end of a high-speed SerDes system typically employs joint equalization of a combination of a forward feedback equalizer (Feed Forward Equalizer, FFE) and a decision feedback equalizer (Decision Feedback Equalizer, DFE), the structure of which is shown in fig. 1. Because the input of the current symbol of the DFE is the decision value of the previous symbol output, as shown in fig. 2, multiplication, addition and decision of each path need to be sequentially completed in sequence when parallel implementation is performed, and the delay required by these processes is too long to meet the time sequence requirement when parallel implementation is performed.
In high-speed transmission, a parallel architecture is generally adopted to increase the data processing speed. Because the DFE feedback branch has very high time-sequence requirement, special design is often needed in the parallel implementation process, and more resources are used for time exchange, so that parallel processing is realized. In order to implement DFE parallel processing in the prior art, all possible 4 decision values of PAM4 are usually subjected to multiplication, addition and decision preprocessing in advance to obtain 4 output decision values, and an accurate decision value is obtained through 4-choice 1 recursion, as shown in fig. 3. Because the calculation requiring more time is finished in advance, the calculation of the last 4 times of 1 selection takes relatively less time, and the completion within 1 beat can be realized. However, the algorithm is based on the mode of area time change, and the operation which is originally only needed to be calculated once needs to be calculated for 4 times at the same time, so that more resources are consumed. Due to the complex implementation of parallelism, the resources required for each tap are multiplied by 4, typically a 1-tap DFE is used in high speed SerDes systems.
The invention optimizes the parallel implementation of DFE in PAM4 modulation based on a high-speed SerDes system comprising FFE and DFE. For the common scheme of joint equalization of the FFE and the DFE of the receiving end, the FFE shares part of equalization tasks, and the coefficient of the controllable DFE is not particularly large, namely the input signal is not deviated from an ideal value too far in a large probability.
Referring to fig. 4-7, a DFE simplified parallel implementation circuit includes a forward feedback equalizer (Feed Forward Equalizer, FFE), a decision feedback equalizer (Decision Feedback Equalizer, DFE), a decision device, a control module, and a pre-decision circuit module. The forward feedback equalizer, the pre-decision circuit module, the decision feedback equalizer and the decision device are sequentially connected, the output of the decision device is simultaneously used as the input of the pre-decision circuit module to be connected, and the decision feedback equalizer is connected with the control module. The structure of the DFE reduced parallel implementation circuit of the present invention is shown in fig. 4.
The pre-decision circuit is shown in fig. 5. Wherein x i (n) is the input data of the n-th beat of parallel i-th path DFE, s i (n, 1) and s i (n, 2) are the most probable two decision values pre-decided and selected by the n-th beat of i-th path. The ideal level obtained by the convergence of the decision device is used for selecting the most probable two decision values of each symbol as the DFE filter input of the next symbol by the pre-decision circuit module. And reporting the DFE coefficient to the control module once at intervals.
The 4 signal levels 00, 01, 10, 11 of the PAM4 signal correspond to decision values-3, -1, 3, respectively, and correspond to ideal values v0, v1, v2, v3 converged in the decision device, respectively. Table 1 is a mapping relation of the pre-decision circuit module, by comparing the input signal with v1 and v2, deciding one of 3 regions, each region selecting two most probable decision values as the input of the next path for preprocessing, and recursively selecting one of the preprocessed two output results through the final decision value. Since v1 and v2 fluctuate slightly above and below the optimum after convergence, the feedback branch is not so demanding on the timing. As shown in fig. 6, w (n) is a DFE coefficient of the nth beat, y i (n, 1) and y i (n, 2) are two decision values of the ith preprocessing output of the nth beat, and z i (n) is an output decision value obtained by recursion of the ith beat.
Because the pre-judgment is carried out, each path only needs to carry out the pre-treatment of two possible judgment values, and finally carries out the result recursion of 2-choice 1, thereby greatly reducing the required operation resources.
Table 1 pre-decision circuit module mapping relationship
Fig. 7 is a flow chart of a simplified parallel implementation method of DFE according to the present invention. Firstly, starting the FFE and the decision device, starting the pre-decision circuit module and the DFE after the coefficients of the FFE and the decision device are converged, and reporting the DFE coefficients to the control module after the coefficients of the FFE and the decision device are converged by a self-adaptive algorithm. And judging the risk of error codes by monitoring whether the DFE coefficient is too large, so that the control module totally coordinates the coordination of all the equalization modules.
The preferred embodiments of the invention disclosed above are intended only to assist in the explanation of the invention. The preferred embodiments are not exhaustive or to limit the invention to the precise form disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention.
Claims (3)
1. The simplified parallel DFE realization circuit comprises a forward feedback equalizer FFE, a decision feedback equalizer DFE, a decision device and a control module, and is characterized by further comprising a pre-decision circuit module, wherein the forward feedback equalizer FFE, the pre-decision circuit module, the decision feedback equalizer DFE and the decision device are sequentially connected, the output of the decision device is simultaneously used as the input of the pre-decision circuit module to be connected, the decision feedback equalizer is connected with the control module, ideal values v0, v1, v2 and v3 converged in the decision device are respectively corresponding to decision values-3, -1, 1 and 3 corresponding to 4 signal levels 00, 01, 10 and 11 of a PAM4 signal, the input signals x i (n) and v1 and v2 are compared, one of 3 areas is decided, each area selects two most possible decision values as the input of the next path to be preprocessed, and one of the preprocessed two output results is selected through the final decision values in a recurrence mode.
2. The DFE simplification parallel implementing circuit according to claim 1, wherein when the input signal x i (n) is not less than v2, the output of the preselected decision value 3 is actually outputted in 3, i+1 paths, the output of the preselected decision value 1 is actually outputted in 1, -3, i+1 paths, when the input signal v1< x i (n) < v2, the output of the preselected decision value 1 is actually outputted in 3, 1, i+1 paths, the output of the preselected decision value-1 is actually outputted in-1, -3, i+1 paths, and when the input signal x i (n) is not more than v1, the output of the preselected decision value-1 is actually outputted in 3, 1, -1, i+1 paths, the output of the preselected decision value-3 is actually outputted in 3, i+1 paths.
3. A method for implementing DFE simplification and parallelism, based on the DFE simplification and parallelism implementing circuit according to claim 1 or 2, characterized in that firstly, the forward feedback equalizer FFE and the decision device are started, after the coefficients of the forward feedback equalizer FFE and the decision device are converged, the pre-decision circuit module and the decision feedback equalizer DFE are started, and after the coefficients of the decision feedback equalizer DFE are converged by an adaptive algorithm, the system works normally and reports the coefficients of the decision feedback equalizer DFE to the control module at intervals.
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