CN119154868B

CN119154868B - Amplitude detection delay phase-locked loop for voltage isolation amplifier

Info

Publication number: CN119154868B
Application number: CN202411623371.5A
Authority: CN
Inventors: 吴浩; 丁辉; 樊琦; 王巍
Original assignee: Nanjing Modular Smart Chip Microelectronics Technology Co ltd
Current assignee: Nanjing Modular Smart Chip Microelectronics Technology Co ltd
Priority date: 2024-11-14
Filing date: 2024-11-14
Publication date: 2025-03-21
Anticipated expiration: 2044-11-14
Also published as: CN119154868A

Abstract

The present invention relates to the field of analog integrated circuit design technology, specifically an amplitude detection delay phase-locked loop applied to a voltage isolation amplifier, comprising a high voltage end portion CHIP1-HV, wherein the high voltage end portion CHIP1-HV comprises a chopper modulation circuit CHIN, a waveform optimizer PWO, and an isolation capacitor Csig1 Csig2、Cclk1、Cclk2、 Clock signal φ 2; The low voltage end portion CHIP2_LV includes a transconductance amplifier AMP, a chopper modulation circuit CHOUT, a low-pass filter LPF, an output buffer BUFFER, an analog-to-digital converter 8-bit ADC, a logic control circuit CON LOGIC, a digital to analog converter 8-bit DAC, an encoding circuit ENCODER, a voltage controlled delay chain VCDL, a ring oscillator RING OSC, and a frequency divider Divider1 Divider2， The present invention calibrates the clock of the chopper modulation circuit located at the low voltage end by continuously iterating the control signal, causing a delay in the low voltage end clock and ultimately aligning it with the high voltage end clock, so that the signal is not distorted during transmission due to the phase difference of the clock signal.

Description

Amplitude detection delay phase-locked loop applied to voltage isolation amplifier

Technical Field

The invention belongs to the technical field of analog integrated circuit design, and particularly relates to an amplitude detection delay phase-locked loop applied to a voltage isolation amplifier.

Background

Industrial applications such as motor drives, photovoltaic inverters and Uninterruptible Power Supplies (UPS) and automotive applications such as on-board chargers (OBCs), traction inverters and DC/DC converters operate at high voltage and current levels. These systems are subject to harsh environments such as electrical noise, vibration, mechanical shock, extreme temperatures, contaminant intrusion, etc. These systems require robust, reliable isolation techniques to isolate the high voltage circuit from the low voltage circuit.

When the chopper modulation technology is used for transmitting signals in the voltage isolation field, the phase consistency of the chopper modulation clock signal and the chopper demodulation clock signal is extremely important, if the clock delays due to parasitic resistance, inductance and capacitance during transmission, the phase inconsistency between the modulation clock and the demodulation clock is caused, so that partial signals are lost, gain attenuation, distortion and the like finally occur, and in order to ensure that the signals have no distortion phenomenon in transmission, the chopper modulation clock and the chopper demodulation clock are aligned by using a calibration technology, and the phase calibration is consistent.

The closest prior art publication CN115425937a discloses a chopper operational amplifier circuit for voltage isolation, which mainly comprises transconductance amplifiers amp1, amp2, amp3, amp4, amp5, chopper modulation circuit CHIN, CHOUT, CHfb, CHRRL, capacitors Cin1, cin2, cfb1, cfb2, cs1, cs2, cm1, cm21a, cm21b, cm22a, cm22b, resistors res1, res2, chopper modulation signal fchop. The chopper modulation circuit CHIN modulates the analog voltage signal input from the high-voltage terminal to the voltage signal with the frequency fchop and couples the analog voltage signal to the low-voltage terminal through the isolation capacitors Cin1 and Cin2, the bias resistors res1 and res2 of the low-voltage terminal provide the direct current bias signal for the input transconductance amplifier amp1 of the low-voltage terminal again, CHOUT modulates the offset voltage VOFFSET and 1/f noise of the transconductance amplifier amp1 to high frequency, simultaneously remodulates the output current signal of the amp1 to the frequency input from the high-voltage terminal, and finally the output voltage is vout=vin× (Cfb/Cin), and the ripple cancellation loop eliminates ripples generated by the offset voltages of the transconductance amplifiers amp1, amp2 and amp 3.

In the prior art, distortion phenomenon caused by inconsistent phases of a high-voltage section clock and a low-voltage end clock is not considered, and in a chip, due to the influences of a bonding wire, parasitic capacitance, parasitic inductance and parasitic resistance, a clock signal can generate phase shift phenomenon in the process of transmitting from the low-voltage section to the high-voltage end, and the signal can be distorted in the processes of modulating a high-voltage port and demodulating the low-voltage end.

Disclosure of Invention

This section is intended to outline some aspects of embodiments of the application and to briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section as well as in the description of the application and in the title of the application, which may not be used to limit the scope of the application.

In view of the technical problems in the prior art, the prior circuit cannot avoid the phenomenon that signals are distorted in the high-voltage port modulation and low-voltage port demodulation processes.

In order to solve the technical problems, the invention provides the following technical scheme:

A high voltage end part CHIP 1-HV including a chopper modulation circuit CHIN, a waveform optimizer PWO, and isolation capacitors Csig1, csig2, cclk1, cclk2, a clock signal Φ2;

A low-voltage end part CHIP2_lv including a transconductance amplifier AMP, a chopper modulation circuit CHOUT, a low-pass filter LPF, an output BUFFER, an analog-to-digital converter 8bitADC, a LOGIC CONTROL circuit CONTROL, a digital-to-analog converter 8bitDAC, an encoding circuit ENCODER, a voltage-controlled delay chain VCDL, a RING oscillator RING OSC, frequency dividers diver 1, diver 2, a clock signal Φ1, a voltage-controlled delay signal Vctrl, digital signals D1[0:7], D2[0:7], D3[0:7];

The chopper modulation circuit CHIN is respectively connected with the waveform optimizer PWO and the isolation capacitors Csig1 and Csig2, the isolation capacitors Csig1 and Csig2 are respectively connected with the input end of the chopper modulation circuit CHOUT, the output end of the chopper modulation circuit CHOUT is respectively connected with the input end of the transconductance amplifier AMP and the output end of the frequency Divider2, the output end of the transconductance amplifier AMP is connected with the input end of the low-pass filter LPF, the output end of the low-pass filter LPF is connected with the output BUFFER and outputs, the waveform optimizer PWO is connected with the isolation capacitors cck 1 and cck 2 and then is connected with the frequency Divider1, the frequency Divider1 is respectively connected with the RING oscillator RING and the voltage-controlled delay chain VCDL, the voltage-controlled delay chain VCDL is also respectively connected with the frequency Divider2 and the digital-analog converter 8bitDAC, the digital-analog converter 8bitDAC is also connected with the LOGIC CONTROL circuit CONTROL gic, and the LOGIC CONTROL circuit CONTROL LOGIC CONTROL is also respectively connected with the encoder ENCODER and the analog-digital converter 8 and the analog-digital converter bitADC.

As a preferred technical solution applied to the amplitude detection delay locked loop of the voltage isolation amplifier, the isolation input capacitors Csig1, csig2, cclk1, cclk2 isolate the high voltage end part CHIP1_hv and the low voltage end part CHIP2_lv, and play a role of protecting the low voltage end, the chopper modulation circuit CHIN modulates the input ac signal into a high frequency to be transmitted from the high voltage end part CHIP1_hv to the low voltage end part CHIP2_lv through Csig1, csig2, and the function of the CHIP is to modulate the high frequency signal transmitted from the high voltage end part into the low frequency signal, and the low frequency signal is amplified ten times by the transconductance amplifier AMP and then outputted by the low pass filter LPF.

As a preferred technical scheme applied to the amplitude detection delay phase-locked loop of the voltage isolation amplifier, the voltage output by the low-pass filter LPF is encoded into an eight-bit digital code D1[0:7] by the analog-to-digital converter 8bitADC, the ideal output voltage is encoded into an eight-bit digital code D2[0:7] by the encoding circuit ENCODER, the LOGIC CONTROL circuit CONTROL performs a subtraction operation on the D1[0:7] and the D2[0:7] to generate a new eight-bit digital code D3[0:7], and the D3[0:7] is sent to the digital-to-analog converter 8bitDAC to generate a voltage which is proportional to the difference between the ideal output voltage and the real output voltage.

As a preferred solution applied to the amplitude detection delay locked loop of the voltage isolation amplifier, the RING oscillator RING OSC generates a signal of 2MHz, which is transmitted to the CHIP1_hv portion through the isolation capacitors Cclk1 and Cclk2, and generates a clock signal Φ2 through the waveform optimizer PWO.

As a preferred technical solution applied to the amplitude detection delay locked loop of the voltage isolation amplifier, the voltage CONTROL delay signal Vctrl input by the LOGIC CONTROL circuit CONTROL LOGIC will generate a delay to the voltage CONTROL delay chain VCDL, and the delay acts on the clock signal Φ1, so that the clock signal Φ1 calibrates the clock signal Φ2, and the output voltage approaches the ideal value.

As a preferred solution applied to the amplitude detection delay locked loop of the voltage isolation amplifier, the chopper modulation circuit CHIN of the high-voltage side portion CHIP 1-HV takes the input ac signal (denoted as) Modulated into a high frequency signal at the same clock frequency phi 2. The modulation formula is:

Wherein, ,Is frequency (e.g., 1 MHz). The signal is transmitted to the low voltage end part through the isolation capacitors Csig1 and Csig2, ensuring the electrical isolation of the high voltage end and the low voltage end,The input signal is converted into a high-frequency signal through a modulation process for the signal voltage after chopper modulation.

As a preferred solution applied to the amplitude detection delay locked loop of the voltage isolation amplifier, the transconductance amplifier AMP of the low voltage end part CHIP2_lv receives the output signal from CHOUT, and the amplification factor is 10, namely:

Wherein, Is the amplified voltage value of the output signal of the transconductance amplifier AMP.

As a preferable technical scheme applied to the amplitude detection delay phase-locked loop of the voltage isolation amplifier, the amplified signal is processed by a low pass filter LPF to remove high-frequency ripple. Cut-off frequency of low-pass filterIs determined by the following formula:

The invention has the beneficial effects that the low-voltage end uses the circuits such as ADC, DAC, logic control, encoder, voltage-controlled delay chain and the like to calibrate the chopper modulation circuit clock at the low-voltage end, detects the actual output signal and converts the actual output signal into the clock signal controlled by the chopper modulation circuit at the low-voltage end, the phase of the clock signal is related to the output voltage, and the clock at the low-voltage end is delayed and finally aligned with the clock at the high-voltage end by continuously iterating the control signal, so that the signal is not distorted due to the phase difference of the clock signal in the transmission process.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. Wherein:

FIG. 1 is a voltage isolation amplitude detection delay locked loop of the preferred embodiment of the present invention

FIG. 2 voltage controlled delay chain of the present invention

FIG. 3 true output 8bitADC encoded values of the present invention

FIG. 4 ideal output ENCODER encoded values of the present invention

FIG. 5A simulation diagram of the difference between the ideal value and the actual value of the present invention

FIG. 6 simulation of the relationship between VCDL delay time and vctrl of the present invention

Fig. 7 is a simulation diagram of the duty cycle of the corresponding clock signal Φ1 at different Vctrl of the present invention.

Detailed Description

In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present invention is not limited to the specific embodiments disclosed below.

Further, reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic can be included in at least one implementation of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments.

Further, in describing the embodiments of the present invention in detail, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of description, and the schematic is only an example, which should not limit the scope of protection of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.

Referring to fig. 1 and 2, the present embodiment provides an amplitude detection delay locked loop applied to a voltage isolation amplifier, including a high voltage end part CHIP1_hv including a chopper modulation circuit CHIN, a waveform optimizer PWO, and isolation capacitors Csig1, csig2, cclk1, cclk2, a clock signal Φ2;

Wherein, the chopper modulation circuit CHIN is configured to modulate an analog input signal at a high voltage end into a signal with the same clock frequency phi 2; the isolation capacitors Csig1, csig2, cclk1 and Cclk2 are used for isolating the high-voltage end part CHIP1_HV from the low-voltage end part CHIP2_LV, and play a role in blocking direct communication; the chopper modulation circuit CHOUT is used for modulating an analog input signal transmitted from a high-voltage end into a signal with the same clock frequency phi 1; the transconductance amplifier AMP is used for amplifying a signal output by the CHOUT to ten times of an input signal, the low-pass filter LPF is used for eliminating ripple caused by AMP output and chopper modulation circuits CHIN and CHOUT, the analog-to-digital converter 8bitADC is used for encoding the signal output by the LPF into an eight-bit digital code D1[0:7], the encoding circuit ENCODER is used for encoding an ideal output signal into an eight-bit digital code D2[0:7], the LOGIC CONTROL circuit CONTROL LOGIC is used for amplifying the digital code D1[0:7] output by the 8bitADC and the digital code D2[0:7] output by the encoder, a new eight-bit digital code D3[0:7] is output after subtraction operation, the digital-to-analog converter 8bitDAC is used for converting the eight-bit digital code D3[0:7] output by the LOGIC CONTROL circuit into an analog voltage value Vctrl, the RING oscillator RING is used for generating a clock of 2MHz, the clock signal Cclk1, the clock signal is transferred to the RING oscillator through the isolation capacitors Cclk1 and the voltage-delay circuit Cclk2, the clock signal is transferred to the clock 1-phase delay circuit and the clock signal is transferred to the clock 1-delay circuit 1 and the clock signal is transferred to the clock 1, the clock signal is transferred to the clock 1, so that the output value approximates the ideal output.

The isolation input capacitors Csig1, csig2, cclk1, cclk2 isolate the high voltage side portion CHIP 1-HV and the low voltage side portion CHIP 2-LV, and function to protect the low voltage side, the chopper modulation circuit CHIN modulates an input ac signal into a high frequency to be transmitted from the high voltage side portion CHIP 1-HV to the low voltage side portion CHIP 2-LV through Csig1, csig2, and the function of the CHOUT is to modulate the high frequency signal transmitted from the high voltage side portion into a low frequency signal and to be amplified ten times by the transconductance amplifier AMP and then output by the low pass filter LPF.

The voltage output by the low pass filter LPF is encoded by the A/D converter 8bitADC into an eight bit digital code D1[0:7], the desired output voltage is encoded by the encoding circuit ENCODER into an eight bit digital code D2[0:7], the LOGIC CONTROL circuit CONTROL performs a subtraction operation on D1[0:7] and D2[0:7] to generate a new eight bit digital code D3[0:7], and D3[0:7] is fed into the D/A converter 8bitDAC to generate a voltage proportional to the difference between the desired output voltage and the actual output voltage.

The RING oscillator RING OSC generates a 2MHz signal that is transferred to the high voltage side CHIP1 HV via the isolation capacitors Cclk1, cclk2 and generates a clock signal Φ2 via the waveform optimizer PWO.

The voltage CONTROL delay signal Vctrl input by the LOGIC CONTROL circuit CONTROL LOGIC generates a delay to the voltage CONTROL delay chain VCDL, which delay acts on the clock signal Φ1, so that the clock signal Φ1 is calibrated with respect to the clock signal Φ2, and the output voltage approaches an ideal value.

The analog-to-digital converter 8bitADC functions to encode the signal output from the low pass filter LPF into an eight-bit digital code D1[0:7], the encoding circuit ENCODER functions to encode the desired output signal into an eight-bit digital code D2[0:7], and the LOGIC CONTROL circuit CONTROL functions to subtract the digital code D1[0:7] output from the analog-to-digital converter 8bitADC and the digital code D2[0:7] output from the encoder and then output a new eight-bit digital code D3[0:7].

Further, the dac 8bitDAC is configured to convert the eight-bit digital code D3[0:7] outputted by the logic control circuit into an analog voltage value Vctrl, where the analog voltage value Vctrl controls the delay time of the voltage-controlled delay chain VCDL.

Further, the transconductance amplifier AMP is a nested miller compensation operational amplifier structure, the chopper modulation circuits chn and CHOUT are chopper switch structures, the low-pass filter LPF is an active RC low-pass filter structure, the output BUFFER is a Class-AB operational amplifier structure analog-to-digital converter 8bitADC is a pipeline analog-to-digital converter structure, the LOGIC CONTROL circuit LOGIC, the digital-to-analog converter 8bitDAC is an R-2R digital-to-analog converter structure, the encoding circuit ENCODER can use a shift register structure such as 74HC595 to support 8-bit parallel input encoding, the voltage-controlled delay chain VCDL adopts a structure as shown in fig. 2, the RING oscillator RING circuit can use a common 555 timer circuit design, and the waveform optimizer PWO can use an Application Specific Integrated Circuit (ASIC) with digital signal processing capability.

In the structure of the voltage-controlled delay chain VCDL, vbias is the bias voltage supplied to the circuit below the voltage-controlled delay chain, VID is the difference between vi+ and VI-in fig. 1, and VOD is the difference between vo+ and VO-, i.e. the actual output voltage.

Chopper modulation circuit CHIN of high-voltage side portion CHIP 1-HV inputs an ac signal (denoted as) Modulated into a high frequency signal at the same clock frequency phi 2. The modulation formula is:

The transconductance amplifier AMP of the low-voltage end part CHIP2 LV receives the output signal from CHOUT with a amplification factor of 10, namely:

The amplified signal is processed by a low pass filter LPF to remove high frequency ripple. Cut-off frequency of low-pass filterIs determined by the following formula:

The appropriate resistor R and capacitor C are chosen to ensure that the cut-off frequency is below the signal frequency, thereby effectively filtering out noise.

Filtered signalThe digital signal is converted by an analog-to-digital converter (8 bit ADC) and output as an 8bit digital code D1[0:7]. The conversion process follows:

Wherein the method comprises the steps of Is the reference voltage (typically 5V).

Ideal output voltageThe digital code D2[0:7] is encoded by the encoding circuit ENCODER. Here it is assumed that the ideal output isThe coding formula is similar to analog-to-digital conversion.

The LOGIC CONTROL circuit performs subtraction operation on the two digital signals to obtain an error value:

D3=D2−D1

The result reflects the difference between the ideal output and the actual output for subsequent control signal generation.

Digital-to-analog conversion and delay adjustment-digital-to-analog converter (8 bit DAC) converts D3 to analog voltageFor controlling the delay of the voltage controlled delay chain VCDL. The conversion relation is as follows:

this voltage will affect the delay time and thereby adjust the phase of the clock signal phi 1.

Finally, the clock signal φ 1 generated by the voltage-controlled delay chain (VCDL) should be phase aligned with φ 2 to ensure that the output signal is undistorted. This can be achieved by feedback regulation, the feedback loop ensuring that the phase difference Δt of both is minimal.

Furthermore, the invention also adds an increment feedback mechanism, and dynamically adjusts the control voltage Vctrl of the voltage-controlled delay chain VCDL by monitoring the difference value between the output signal and the ideal signal in real time so as to improve the correction precision of the clock signal.

The method comprises the following specific steps:

First step, signal acquisition

Input signal monitoring first, the actual output voltage value VOD output from the low pass filter LPF is obtained by means of an analog-to-digital converter 8 bitADC. Meanwhile, the encoding circuit ENCODER encodes the ideal output voltage video into digital signals D2[0:7].

Second, error calculation

Calculating an error value:

Error=Videal-VOD

Wherein Error represents the difference between the ideal output voltage, which is typically the target voltage value expected by the system, and the actual output voltage, VOD, which is the voltage value measured by an analog-to-digital converter, 8bit ADC, i.e., the Error, vdea.

The error value reflects the difference between the ideal signal and the actual signal.

Third step, incremental adjustment calculation

Control algorithm the control voltage Vctrl is adjusted using a simple incremental control algorithm, such as proportional control. The control formula is:

Where K is a gain factor, determining the response strength to the error, where a larger K value may make the system respond faster, but may cause overshoot and oscillation, and a smaller K value may cause slow response, vctrl (t) is a control voltage value at time point t, used for adjusting the voltage-controlled delay chain (VCDL), and Vctrl (t-1) is a control voltage value at time point t-1, that is, a control voltage at the last iteration.

Fourth step, control voltage application

Update Vctrl-the calculated new control voltage Vctrl' is fed back to the voltage controlled delay chain VCDL to adjust the delay of the clock signal phi 1.

Fifth step, output signal monitoring

And acquiring the output signal again, namely acquiring a new output signal value VOD' through an analog-to-digital converter (8 bit ADC) after adjusting the control voltage Vctrl.

And (3) circularly selecting the generation, namely repeating the second step to the fifth step until the error value is lower than a set threshold value, wherein the error value indicates that the clock signal is corrected to an ideal state.

The incremental feedback mechanism has the functions of responding in real time, and allowing the system to adjust the control voltage in real time according to the difference between the current output signal and the ideal signal so as to continuously optimize the accuracy of the output signal;

Dynamic correction, when the input signal changes, the incremental feedback mechanism can be quickly adapted to new conditions, and the phase of the clock signal is ensured to be consistent all the time, so that the distortion of the output signal is reduced.

Specifically, the RING oscillator RING OSC of the present invention generates a clock signal with a frequency of 2MHz, generates a clock signal with a frequency of 1MHz through the Divider1, and transmits the clock signal to the CHIP1 HV through the isolation capacitors Cclk1 and Cclk2, and the delay caused by the isolation capacitors Cclk1 and Cclk2, the waveform optimizer PWO, and the bonding wire from the output terminal of the Divider1 to the output terminal of the PWO causes a delay time Δt between the clock signal Φ2 and the clock signal Φ1, which delay causes a distortion phenomenon during signal transmission to occur, thereby resulting in an output voltage signal smaller than that without delay. For example, the input voltage VIP-VIN is 250mV, the output voltage is 2.5V when no delay is performed after ten times of AMP amplification, the output voltage is less than 2.5V when delay is performed, the analog-to-digital converter 8bitADC is used at the output end of the LPF to convert the collected analog voltage value into 8-bit digital code D1[0:7], the ideal output voltage 2.5V is generated by the encoding circuit ENCODER to generate 8-bit digital code D2[0:7], the 8-bit digital code D3[0:7] is generated after the input voltage is sent to the LOGIC CONTROL circuit CONTROL LOGIC for subtraction operation, the D3[0:7] is sent to the digital-to-analog converter 8bitDAC, an analog voltage value Vctrl is generated after the analog voltage value Vctrl CONTROLs the voltage-controlled delay chain VCDL to delay the clock signal Φ1, and finally the clock signal Φ1 is aligned with the phase of the clock signal Φ2, so that the output voltage approaches to the ideal output voltage, and distortion is avoided.

The above scheme was simulated.

The simulation was performed in an environment containing the following conditions:

Software tools, circuit simulation tools such as MATLAB/Simulink or Cadence are used.

The model parameters, such as a set voltage source, an amplifier gain, a filter parameter and the like, are consistent with the actual circuit.

Input signal a sine wave with a frequency of 1kHz was set as input signal for testing.

The simulation flow is as follows

And generating a signal, namely operating an input signal source module and outputting a sine wave signal of 1kHz to CHIN.

And the CHIN module modulates the input signal into a high-frequency signal and outputs the high-frequency signal to the isolation capacitor.

Signal amplification and filtering, in which signal amplification is performed by AMP and input to a low pass filter for filtering.

And D, analog-to-digital conversion, namely, performing digital processing on the output of the LPF through an 8-bit ADC and outputting the digital processing to a logic control circuit.

And the coding process is that the coding circuit receives the ideal output signal and converts the ideal output signal into a digital code.

And calculating errors by subtracting the CONTROL LOGIC module, and outputting the calculated errors.

And the control signal is generated by converting the DAC receiving error output into control voltage to influence the voltage-controlled delay chain.

Phase alignment VCDL adjust signal delay to ensure that the final output is phase coincident with the ideal output.

The simulation results are shown in fig. 3, fig. 4, fig. 5, fig. 6 and fig. 7, fig. 3 is an output signal of the low-pass filter LPF, that is, an input signal of the analog-to-digital converter 8bitADC, the analog-to-digital converter 8bitADC converts the output signal into an 8-bit digital code D1 according to a reference voltage with a conversion frequency of 5V of 1MHz, the output voltage of the LPF is dynamically detected, fig. 4 is an 8-bit digital code D2[10000000] with an ideal output value converted by ENCODER under the condition that the reference voltage is 5V, the 8-bit digital code D1 and the 8-bit digital code D2 output by the analog-to-digital converter 8bitADC are sent into the LOGIC CONTROL circuit LOGIC for subtraction operation, so as to generate an 8-bit digital code D3, the D3 characterizes a voltage CONTROL delay signal Vctrl waveform generated after the difference between the D1 and the D2 above the digital domain is reconstructed by the digital-to-analog converter 8bitDAC with a reference voltage of 5V, as shown in fig. 5, the voltage CONTROL delay signal Vctrl output by the digital-analog converter 8bitDAC is sent into the CONTROL delay signal Vctrl in the voltage CONTROL delay chain dl, as shown in fig. 6, and the clock signal Vctrl generated by the CONTROL delay signal with a larger time than the clock signal vcl is generated in the voltage CONTROL signal vcl with a larger value than 50% when the clock signal is shown in fig. 6, and the clock signal is seen from the clock signal with a larger than the clock signal with a larger value than the clock signal. By this means the clock signal phi 1 can be delayed to the same phase as the clock signal phi 2, thereby ensuring a coincidence between the true output value and the ideal value.

1. In the isolation amplifier using the chopping technology, if the phases of the up-conversion modulation circuit and the down-conversion modulation circuit are different, the transmitted alternating current signal is incomplete, so that the amplitude of the reconstructed voltage is lower than that of the voltage without phase errors, the amplitude detection technology is adopted to judge the delay time in order to keep the phases of the two frequency conversion circuits consistent, and the calibration circuits such as an ADC (analog to digital converter), a DAC (digital to analog converter) and the like are used for calibrating the clock.

2. The clock calibration loop adopts an ADC, a DAC and a logic control circuit, the logic control circuit can generate an eight-bit digital code obtained by subtracting the actual output voltage from the ideal output voltage, the digital code is sent into the DAC to reconstruct into an analog signal, the size of the reconstructed signal can be selected by the reference voltage of the DAC, the signal is input into a voltage-controlled delay chain to delay the output square wave signal of the voltage-controlled delay chain to a certain time, the time delay size is related to the difference value between the ideal output voltage and the actual output voltage, the voltage-controlled delay chain finally outputs the square wave signal to be sent into a frequency Divider Divider2 to serve as a control signal of a low-voltage end chopper modulation circuit CHOUT, and finally, the clock signal at a high-voltage end part is aligned with the clock signal at a low-voltage end part to realize the effect of reducing the phase difference.

3. An amplitude detection delay locked loop for voltage isolation of the present invention generates a clock signal with a frequency of 2MHz from the low voltage side CHIP2_lv using a ring oscillator, and transmits the clock signal to the high voltage side CHIP1_hv through isolation capacitors Cclk1, cclk2, and generates a phi 2 clock signal after passing through a waveform optimizer PWO.

This patent considers this problem, therefore utilize ADC, DAC, logic control, encoder, voltage-controlled delay chain etc. circuit to carry out the calibration to the chopper modulation circuit clock that is located the low pressure end at the low pressure end, detect actual output signal and convert it into the clock signal that controls in low pressure end chopper modulation circuit, this clock signal's phase place is relevant in output voltage, through constantly iterating control signal, let low pressure end clock take place the time delay, finally with high pressure end clock alignment for the signal does not produce the distortion because of the phase difference of clock signal in the transmission process.

It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions may be made. Such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.

It should be noted that the above embodiments are only for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solution of the present invention may be modified or substituted without departing from the spirit and scope of the technical solution of the present invention, which is intended to be covered in the scope of the claims of the present invention.

Claims

1. An amplitude detection delay phase-locked loop applied to a voltage isolation amplifier is characterized by comprising,

2. The amplitude detection delay locked loop for voltage isolation amplifier of claim 1, wherein said isolation input capacitors Csig1, csig2, cclk1, cclk2 isolate the high voltage side portion CHIP1 HV and the low voltage side portion CHIP2 LV, and wherein the chopper modulation circuit CHIN modulates the input AC signal to a high frequency for transmission from the high voltage side portion CHIP1 HV to the low voltage side portion CHIP2 LV via Csig1, csig2, and wherein the function of CHOUT modulates the high frequency signal transmitted from the high voltage side portion to a low frequency signal and amplified ten times by the transconductance amplifier AMP and outputted by the low pass filter LPF.

3. The amplitude detection delay phase-locked loop for voltage isolation amplifier according to claim 2, wherein the voltage output by the low pass filter LPF is encoded by the analog-to-digital converter 8bitADC into an eight-bit digital code D1[0:7], the ideal output voltage is encoded by the encoding circuit ENCODER into an eight-bit digital code D2[0:7], the LOGIC CONTROL circuit CONTROL performs a subtraction operation on the D1[0:7] and the D2[0:7] to generate a new eight-bit digital code D3[0:7], and the D3[0:7] is fed into the digital-to-analog converter 8bitDAC to generate the voltage CONTROL delay signal Vctrl, and the voltage CONTROL delay signal Vctrl is proportional to the difference between the ideal output voltage and the real output voltage.

4. The amplitude detection delay locked loop for voltage isolation amplifier of claim 3, wherein said RING oscillator RING OSC generates a 2MHz signal that is transferred to CHIP1_HV portion via isolation capacitors Cclk1, cclk2 and generates clock signal φ 2 via waveform optimizer PWO.

5. The amplitude detection delay locked loop for a voltage isolation amplifier of claim 4, wherein the voltage CONTROL delay signal Vctrl input by the LOGIC CONTROL circuit CONTROL LOGIC produces a delay to the voltage CONTROL delay chain VCDL, the delay acting on the clock signal φ 1 such that the clock signal φ 1 is calibrated to the clock signal φ 2 such that the output voltage approximates the desired value.

6. The amplitude detection delay locked loop for a voltage isolation amplifier of claim 5, wherein the chopper modulation circuit CHIN of the high voltage side portion CHIP1_HV outputs an input AC signalModulated into a high frequency signal with the same clock frequency phi 2, and the modulation formula is as follows:

;

Wherein, ,For frequency, the signal is transferred to the low voltage side portion through isolation capacitors Csig1 and Csig2, ensuring electrical isolation of the high voltage side from the low voltage side,The input signal is converted into a high-frequency signal through a modulation process for the signal voltage after chopper modulation.

7. The amplitude detection delay locked loop of claim 6 wherein the transconductance amplifier AMP of the low side section CHIP2 LV receives an output signal from CHOUT at a gain of 10:

;

8. The amplitude detection delay locked loop for voltage isolation amplifier of claim 7, wherein the amplified signal is processed by a low pass filter LPF to remove high frequency ripple, cut-off frequency of the low pass filterIs determined by the following formula:

;

Wherein R is a resistance value, and C is a capacitance value.