CN119153535A - Asymmetric super junction MOSFET structure and manufacturing method thereof - Google Patents
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Abstract
一种非对称超级结MOSFET结构及其制造方法，属于半导体技术领域，一种超级结MOSFET结构，包括衬底及元胞结构；所述元胞结构包括：第一柱区，包括N型漂移区；第二柱区，设置在第一柱区中，包括柱区结构和设置在柱区结构上的栅极结构；第三柱区，包括侧壁P柱区，侧壁P柱区为离子注入式P柱区，侧壁P柱区与相邻的N型漂移区电荷平衡；第三柱区设置在第二柱区与第一柱区之间，第三柱区设置在第二柱区的一侧。本申请通过深沟槽离子注入的侧壁P柱区，使得侧壁P柱区与对应的N型漂移区的电荷平衡控制更为精准；同时，由于超级结的PN结位置远离刻蚀界面，降低了缺陷界面处的电场，提升了产品的可靠性，也避免了多次外延，有助于节约超级结MOSFET的制造成本。
An asymmetric super junction MOSFET structure and a manufacturing method thereof, belonging to the field of semiconductor technology, a super junction MOSFET structure, including a substrate and a cell structure; the cell structure includes: a first column region, including an N-type drift region; a second column region, arranged in the first column region, including a column region structure and a gate structure arranged on the column region structure; a third column region, including a side wall P column region, the side wall P column region is an ion implanted P column region, and the side wall P column region is charge balanced with the adjacent N-type drift region; the third column region is arranged between the second column region and the first column region, and the third column region is arranged on one side of the second column region. The present application uses a side wall P column region implanted with deep trench ions, so that the charge balance control between the side wall P column region and the corresponding N-type drift region is more accurate; at the same time, because the PN junction position of the super junction is far away from the etching interface, the electric field at the defect interface is reduced, the reliability of the product is improved, and multiple epitaxy is avoided, which helps to save the manufacturing cost of the super junction MOSFET.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to an asymmetric super junction MOSFET structure and a manufacturing method thereof.
Background
Superjunction MOSFET (Super Junction MOSFET) is an advanced power semiconductor device that optimizes the electric field distribution by introducing additional charge between the N-type and P-type regions based on charge balancing techniques, thereby reducing on-resistance and reducing parasitic capacitance.
In terms of process technology, the superjunction may be formed by a trench or multiple epitaxial processes. For example, china patent publication No. CN113488388A discloses a trench gate superjunction VDMOSFET semiconductor device and a method of making the same, comprising the steps of growing an N-type epitaxial layer on an N + type substrate, forming a plurality of first trenches on the N-type epitaxial layer, growing a P-type epitaxial layer on the surface of the N-type epitaxial layer and in each first trench, forming a plurality of second trenches on the P-type epitaxial layer, growing an N-type epitaxial layer in each second trench, growing a P-epitaxial layer on the P-type epitaxial layer and the N-type epitaxial layer, forming a plurality of third trenches on the P-type epitaxial layer, forming a gate oxide film on the side wall and bottom of each third trench, forming an N + source region on the surface of the P-epitaxial layer at the opening of the third trench, forming a P + implant region on the surface of the P-epitaxial layer, burying a gate material in the third trenches, forming a source above the P + implant region and N + source region, and forming a drain below the N + type substrate surface. The method overcomes the limitation of etching process and epitaxial growth process for forming the groove by repeated epitaxial growth process.
However, the super junction formed by multiple epitaxial processes is too complex in process and high in cost, and the super junction formed by etching the grooves is poor in doping control, and the reliability of the device is easily affected by etching interface defects.
Therefore, there is a need to develop an asymmetric super junction MOSFET structure and a method for fabricating the same to solve the problems in the prior art.
Disclosure of Invention
The invention aims to provide an asymmetric super junction MOSFET structure and a manufacturing method thereof, which avoid forming a super junction through multiple epitaxial processes or forming a super junction through etching a groove through an ion implantation type side wall P column region so as to solve the problems of too complex process or poor doping control of the existing super junction structure.
In order to solve the technical problems, the specific technical scheme of the invention is as follows:
an asymmetric super junction MOSFET structure comprises a substrate and a cell structure positioned on the substrate, wherein the cell structure comprises:
a first pillar region comprising an N-type drift region;
A second column region disposed in the first column region, including a column region structure and a gate structure disposed on the column region structure;
the third column region comprises a side wall P column region, the side wall P column region is an ion implantation type P column region, the side wall P column region is in charge balance with an adjacent N-type drift region, the third column region is arranged between the second column region and the first column region, and the third column region is arranged on one side of the second column region.
Further, the first column region further comprises a side wall P + region, the side wall P + region is located on the side wall P column region, the side wall P + region is an ion implantation type P + region, the inclination angle of the side wall P + region during ion implantation is larger than that of the side wall P column region during ion implantation, and the depth of the side wall P + region is not lower than that of the gate structure.
Further, the column region structure comprises a semiconductor column region or a dielectric column region;
when the column region structure is a semiconductor column region, the gate structure comprises gate oxide contacted with the semiconductor column region and a gate electrode contacted with the gate oxide;
When the column region structure is a dielectric column region, the gate structure comprises a gate electrode in contact with the dielectric column region, and a dielectric column region is arranged between the gate electrode and the first column region.
Further, the semiconductor column region is an intrinsic semiconductor column region or a low-doped semiconductor column region, and the dielectric column region is an insulating dielectric column region.
Further, the first column region further comprises a P-well region and an N + region, the N-type drift region is located on the substrate, the P-well region is located on the N-type drift region, and the N + region is located on the P-well region;
Or the first column region further comprises a current diffusion layer, a P well region and an N + region, wherein the N-type drift region is positioned on the substrate, the current diffusion layer is positioned on the N-type drift region, the P well region is positioned on the current diffusion layer, and the N + region is positioned on the P well region.
Further, the semiconductor device further comprises an N-type drift layer, wherein the N-type drift layer is located on the substrate, and the first column region and the second column region are located on the N-type drift layer.
Further, a bottom P column region is arranged in the N-type drift layer, the bottom P column region is arranged at the top of the N-type drift layer, the bottom P column region is an ion implantation type P column region, the inclination angle of the bottom P column region during ion implantation is equal to the inclination angle of the side wall P column region during ion implantation, and the bottom P column region and the side wall P column region are formed during the same ion implantation.
Further, one of the cell structures includes two of the first column regions and one of the second column regions, the second column region being disposed between the two first column regions, the second column region separating the two first column regions.
Further, one of the cell structures includes one of the first column regions and one of the second column regions, the first column region surrounding the second column region.
A manufacturing method of an asymmetric super junction MOSFET structure comprises the following steps:
Constructing an initial MOSFET structure, wherein the initial MOSFET structure comprises a substrate, an N-type drift region, a P-well region and an N + region;
constructing a mask on the upper surface of the initial MOSFET structure, and etching the deep trench;
Constructing a side wall P column region at one side of the N-type drift region by carrying out first ion implantation on one side of the deep trench, wherein the side wall P column region is in charge balance with the corresponding N-type drift region;
Constructing a side wall P + region on the side wall P column region by carrying out second ion implantation on one side of the deep trench;
Removing the mask;
Filling the deep trench to form a column region structure;
A gate structure is constructed on top of each pillar structure.
Further, the inclination angle of the first ion implantation is larger than that of the second ion implantation, the depth of the side wall P + area is not lower than that of the grid structure, and at least three deep trenches are etched, wherein two deep trenches are positioned at the end parts of two sides of the initial MOSFET structure.
Further, the masks used in the first ion implantation and the second ion implantation are masks structured on the upper surface of the initial MOSFET structure.
Further, the filling of the deep trench to form a pillar structure includes the steps of:
depositing dielectric medium in the deep trench to form a dielectric column region;
the construction of the gate structure on top of each pillar structure comprises the following steps:
Etching a grid groove at the top of each dielectric column region, wherein a dielectric column region is reserved between the etched grid groove and the first column region;
and filling a gate electrode in the gate trench.
Further, the filling of the deep trench to form a pillar structure includes the steps of:
forming a semiconductor column region in all the deep trenches through an epitaxial backfilling process;
the construction of the gate structure on top of each pillar structure comprises the following steps:
etching a grid groove at the top of the dielectric column region;
depositing gate oxide in the gate trench and filling a gate electrode in the gate oxide;
Wherein the gate oxide is in contact with the first column region.
Further, when the deep trench is etched, the depth of the etched deep trench is smaller than the height of the N-type drift region;
the shape of the deep groove comprises a blind hole or a through groove;
when the first ion implantation is performed on one side of the deep trench, the method comprises the following steps:
and constructing a side wall P column region at one side of the N-type drift region and constructing a bottom P column region at the top of the N-type drift layer by carrying out first ion implantation on one side of the deep trench, wherein the bottom P column region is connected with the side wall P column region.
The method has the advantages that the charge balance control of the side wall P column region and the corresponding N-type drift region can be more accurate through the side wall P column region of deep trench ion implantation, meanwhile, as the PN junction position of the super junction is far away from the etching interface, the electric field at the defect interface is reduced, the reliability of products is improved, multiple epitaxy is avoided, and the manufacturing cost of the super junction MOSFET is saved.
Meanwhile, the ion implantation with the inclination angle is carried out in the deep groove, and the vertical depth of the formed P column region is only related to the inclination angle of the ion implantation and the depth of the groove, so that the height of the P column region formed in the mode is not limited by the maximum implantation energy and the implantation depth of the implanter.
Other features and advantages of the present invention will be disclosed in the following detailed description of the invention and the accompanying drawings.
Drawings
FIG. 1 is a schematic overall structure of a first embodiment;
FIG. 2 is a schematic diagram of an initial MOSFET structure in accordance with a first embodiment;
FIG. 3 is a schematic diagram of a structure after etching deep trenches according to the first embodiment;
FIG. 4 is a schematic diagram of a structure after forming a sidewall P pillar region and a sidewall P + region according to an embodiment;
FIG. 5 is a schematic diagram of a post structure according to an embodiment;
FIG. 6 is a schematic diagram of a structure after etching a gate trench according to an embodiment;
FIG. 7 is a schematic overall structure of a second embodiment;
FIG. 8 is a schematic overall structure of a third embodiment;
FIG. 9 is a schematic diagram of the electric field strength of each structure at the time of blocking in the third embodiment;
FIG. 10 is a diagram showing the relationship between the electric field strength and the vertical position during the third embodiment;
FIG. 11 is a cross-sectional view of the overall structure of the fourth embodiment;
fig. 12 is a cross-sectional view of the entire structure of the fifth embodiment.
The figure shows that the substrate is 1, the drift region of 2 and N type, the well region of 3 and P type, the well region of 4 and N + type, the side wall P column region of 51 type, the bottom P column region of 52 type, the side wall P + type, the column region structure of 7 type, the gate electrode of 8 type, the gate oxide of 9 type, the drift layer of 101 type and N type, the current diffusion layer of 102 type and the current diffusion layer of 103 type and the mask.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings for a better understanding of the objects, structures and functions of the present invention.
An asymmetric super junction MOSFET structure, as shown in FIG. 1, comprises a substrate 1 and a cell structure arranged on the substrate 1, wherein the cell structure comprises:
a first column region, which is positioned on the substrate 1 and comprises an N-type drift region 2;
A second column region disposed in the first column region, including a column region structure 7 and a gate structure disposed on the column region structure 7;
The third column region is located on the substrate 1 and comprises a side wall P column region 51, the side wall P column region 51 is an ion implantation type P column region, and the side wall P column region 51 and an adjacent N-type drift region 2 are in charge balance;
The third column region is disposed between the second column region and the first column region, and the third column region is disposed at one side of the second column region.
In this embodiment, one of the cellular structures includes two first column regions and one second column region, the second column region is disposed between the two first column regions, and the second column region separates the two first column regions.
The third column region further comprises a side wall P + region 6, the side wall P + region 6 is arranged on the side wall P column region 51, the side wall P + region 6 is an ion implantation type P + region, the inclination angle of the side wall P + region 6 during ion implantation is larger than that of the side wall P column region 51 during ion implantation, and the depth of the side wall P + region 6 is not lower than that of the gate structure.
In this embodiment, the substrate 1 is a highly doped N-type material, the ion implantation type P column region is a P column region formed by ion implantation, and the ion implantation type P + region is a P + region formed by ion implantation. Specifically, the ion implantation may be self-aligned ion implantation.
Specifically, as shown in fig. 1, in this embodiment, the first pillar region further includes a P-well region 3 and an N + region 4, the N-type drift region 2 is disposed on the substrate 1, the P-well region 3 is disposed on the N-type drift region 2, and the N + region 4 is disposed on the P-well region 3. Alternatively, the first pillar region may be provided with other structures as required.
In this embodiment, the pillar region structure 7 is a dielectric pillar region, as shown in fig. 1, and the gate structure includes a gate electrode 8 in contact with the dielectric pillar region, where a dielectric pillar region exists between the gate electrode 8 and the first pillar region, and the dielectric pillar region between the gate electrode 8 and the first pillar region has the same function as the gate oxide.
Optionally, the material of the dielectric pillar region is an insulating medium, such as SiO 2.
Alternatively, a source electrode may be disposed on the N + region 4 to construct a source.
Optionally, the cell structures are provided in a plurality, and the plurality of cell structures are densely paved on the substrate.
A method for manufacturing an asymmetric super junction MOSFET structure, as shown in fig. 2 to 6, includes the following steps:
s1, constructing an initial MOSFET structure;
s2, constructing a mask 103 on the upper surface of the initial MOSFET structure, and etching the deep trench;
S3, constructing a side wall P column region 51 at one side of the N-type drift region 2 by carrying out first ion implantation on one side of the deep trench, wherein the side wall P column region 51 and the corresponding N-type drift region 2 are in charge balance;
S4, constructing a side wall P + region 6 on the side wall P column region 51 by carrying out second ion implantation on one side of the deep trench;
S5, removing the mask;
S6, filling the deep trench to form a column region structure 7;
and S7, constructing a grid structure on the top of each column region structure 7.
In this embodiment, as shown in fig. 2, the initial MOSFET structure in S1 includes a substrate 1, an N-type drift region 2, a P-well region 3, and an N + region 4, where the N-type drift region 2 is disposed on the substrate 1, the P-well region 3 is disposed on the N-type drift region 2, and the N + region 4 is disposed on the P-well region 3. The structure of the initial MOSFET structure is a prior art, and the present application is not repeated. The described construction of the initial MOSFET structure may also be commercially available. The initial MOSFET structure may also be selected as desired.
As shown in fig. 3, in this embodiment, the mask 103 in S2 is configured on the upper surface of the N + region 4, and the deep trench penetrates through the N-type drift region 2. Specifically, the etching method may be ICP etching. In this embodiment, the deep trench is a through trench to form two separated first column regions in one cell.
In this embodiment, a mask 103 is required for ion implantation, and as shown in fig. 4, the mask 103 for the first ion implantation in S3 is the mask 103 obtained in S2. The first ion implantation is performed on the same side of the deep trench and is performed at a small angle and a low dose. The sidewall P pillar region 51 is formed at the lower end of the N-type drift region 2 side.
Meanwhile, as shown in fig. 4, in this embodiment, the mask 103 in the second ion implantation in S4 is also the mask 103 obtained in S2. The second ion implantation is also a high-angle high-dose angled implantation on the same side as the first ion implantation to construct sidewall P + region 6 on sidewall P pillar region 51. The large angle is larger than the inclination angle in the first ion implantation. The depth of the sidewall P + region 6 is not lower than the depth of the gate structure, in this embodiment, the distance between the sidewall P + region 6 and the substrate 1 is smaller than the distance between the gate structure and the substrate 1.
The present application can avoid the upper portion or upper surface of the N + region 4 from being implanted with ions as well by using the mask 103 when etching the deep trench.
Specifically, the ion implantation mode may be inclined self-aligned implantation, which is a special ion implantation technology, combines the advantages of self-aligned technology and inclined implantation, and is not described in detail in the prior art.
The step of removing the mask in S5 is performed after the sidewall P pillar region 51 and the sidewall P + region 6 are constructed, so as to implement reuse of the mask 103, and save manufacturing cost.
In this embodiment, as shown in fig. 5, three deep trenches are etched, and the S6 fills all deep trenches to form three pillar structures 7.
In this embodiment, the pillar region structure 7 is a dielectric pillar region, and the filling of the deep trench to form the pillar region structure 7 includes the following steps:
And depositing dielectric medium in the deep trench to form a dielectric medium column region.
In particular, the dielectric is an insulating medium, such as SiO 2.
As shown in fig. 6 and 1, in this embodiment, S7 includes:
Etching a gate trench at the top of each dielectric pillar region, wherein a remaining dielectric pillar region serving as a gate oxide remains between the etched gate trench and the first pillar region in the embodiment;
A gate electrode 8 is filled in the gate trench to form a gate structure.
The application can control the charge balance of the side wall P column region 51 and the corresponding N-type drift region 2 more accurately through the side wall P column region 51 implanted by deep groove ions, and meanwhile, the PN junction position of the super junction is far away from the etching interface, so that the electric field at the defect interface is reduced, the reliability of the product is improved, multiple epitaxy is avoided, and the manufacturing cost of the super junction MOSFET is saved.
Furthermore, the ion implantation method with different inclination angles in the deep trench is adopted, and the vertical depth of the formed P column region is only related to the inclination angle of ion implantation and the depth of the trench, namely the height of the P column region formed in the mode is not limited by the maximum implantation energy and the implantation depth of the implanter.
Meanwhile, the side wall P + region 6 formed synchronously with the side wall P column region 51 can reduce the electric field at the bottom of the gate oxide 9, play a role in protecting the gate oxide 9, and realize the asymmetric super junction MOSFET structure design with low cost, high performance and high reliability.
In the MOSFET structure provided by the application, when in blocking, the side wall P column region 51 and the N type drift region 2 form a super junction structure, and the vertical electric field distribution is changed from triangular distribution of a conventional device to rectangular-like distribution, so that high withstand voltage is realized.
Meanwhile, the electric field in the gate oxide is restrained through the side wall P + region 6, and at the moment, the high electric field is transferred to the bottom of the side wall P + region 6, so that the reliability of the device is improved. In the forward conduction, a channel is formed in the P-well region 3 by the gate oxide on the other side symmetrical to the side wall P + region 6, and the current is conducted.
Example two
As shown in fig. 7, the present embodiment differs from the first embodiment in that:
The column region structure 7 is a semiconductor column region, the gate structure comprises a gate oxide 9 in contact with the semiconductor column region and a gate electrode 8 in contact with the gate oxide 9, the gate oxide 9 is also in contact with the first column region or the third column region, and the gate electrode 8 is not in contact with the semiconductor column region, the first column region or the third column region. The gate oxide 9 is a gate oxide.
Optionally, the material of the semiconductor column region includes an intrinsic semiconductor or a low-doped semiconductor.
During the preparation, the deep trench is filled in the S6 to form a pillar region structure 7, which includes the following steps:
And forming a semiconductor column region in all the deep trenches by an epitaxial backfilling process, wherein the semiconductor column region is an intrinsic semiconductor column region in the embodiment. The epitaxial backfill process is the prior art, and the application is not repeated.
The gate structure is constructed on top of each pillar structure 7 in S7, which includes the following steps:
In the embodiment, a dielectric column region is not arranged between the side wall of the gate trench and the first column region;
A gate oxide 9 is deposited in the gate trench and a gate electrode 8 is filled in the gate oxide. Wherein the bottom of the gate oxide 9 is in contact with the semiconductor column region, the side is in contact with the first column region or the third column region, and the gate electrode 8 is not in contact with the semiconductor column region and the first column region.
The deposited gate oxide and the filled gate electrode 8 are conventional techniques, and the present application will not be described in detail.
Example III
As shown in fig. 8, the difference between the present embodiment and the first or second embodiment is that:
an N-type drift layer 101 is further disposed on the substrate 1, and the first, second and third column regions are located on the N-type drift layer 101.
During preparation, the depth of the deep trench etched in the S2 is smaller than the height of the N-type drift region 2.
Further, this embodiment is also different from the first or second embodiment in that:
The bottom P-pillar region 52 is disposed in the N-type drift layer 101, the bottom P-pillar region 52 is disposed on top of the N-type drift layer 101, and the bottom P-pillar region 52 is an ion implantation type P-pillar region. Optionally, the inclination angle of the bottom P-pillar region 52 during ion implantation is equal to the inclination angle of the sidewall P-pillar region 51 during ion implantation, and the bottom P-pillar region 52 and the sidewall P-pillar region 51 are formed during the same ion implantation.
During preparation, when the first ion implantation is performed on one side of the deep trench in the step S3, the method further comprises:
A bottom P-pillar region 52 is formed on top of the N-type drift layer 101, and a sidewall P-pillar region 51 is formed on one side of the N-type drift region 2, and the bottom P-pillar region 52 is connected to the sidewall P-pillar region 51. The sidewall P pillar regions 51 are charge balanced with the corresponding N-type drift region 2.
Specifically, the bottom P-pillar region 52 and the sidewall P-pillar region 51 may be connected by adjusting the tilt angle at the time of ion implantation, so that one ion implantation is simultaneously formed. Alternatively, the bottom P-pillar region 52 and the sidewall P-pillar region 51 may be formed by two ion implantations.
Optionally, this embodiment is further different from the first embodiment or the second embodiment in that:
The first pillar region further includes a current diffusion layer 102, the N-type drift region 2 is disposed on the substrate 1 or the N-type drift layer 101, the current diffusion layer 102 is disposed on the N-type drift region 2, the P-well region 3 is disposed on the current diffusion layer 102, and the N + region 4 is disposed on the P-well region 3.
When the initial MOSFET structure is formed in S1, the method further includes forming a current diffusion layer 102. This is the prior art, and the present application is not described in detail.
As shown in fig. 9 and 10, the present application suppresses the electric field in the gate oxide through the sidewall P + region 6, so that the high electric field is transferred to the bottom of the sidewall P + region 6, thereby improving the reliability of the device. Wherein FIG. 9 shows the electric field intensity of each structure represented by colors in the range of 0MV/cm to 3MV/cm. Fig. 10 shows the electric field strength corresponding to the vertical position of the line in fig. 9.
Example IV
As shown in fig. 11, this embodiment is different from the first, second or third embodiments in that one of the cell structures includes one of the first column regions surrounding the second column region and one of the second column regions not separating the first column regions on both sides thereof. The third column region is disposed on one side of the second column region and between the second column region and the first column region. The sidewall P pillar regions 51 of the third pillar region are in charge balance with the associated N-type drift region 2.
In this embodiment, the deep trench etched in S2 is blind hole. The side wall P column region and the side wall P+ region are obtained by carrying out ion implantation on one side of the deep trench. Specifically, in this embodiment, at least two surfaces inside the N-type drift region are implanted during the first ion implantation, and the number of implanted surfaces during the second ion implantation is the same as that during the first ion implantation.
Optionally, the shape of the cellular structure is a right quadrangular prism. The shape of the cellular structure in the top view is rectangular, the shape of the second column region in the top view is rectangular, the combined shape of the first column region and the third column region in the top view is hollow rectangular, and the shape of the third column region in the top view is half of the hollow rectangular.
Example five
As shown in fig. 12, the difference between the present embodiment and the fourth embodiment is that the shape of the cell structure is a straight hexagonal prism.
Specifically, in this embodiment, three surfaces inside the N-type drift region are implanted in the first ion implantation, and the number of implanted surfaces in the second ion implantation is the same as that in the first ion implantation.
Optionally, the shape of the cellular structure in the top view is a regular hexagon, the shape of the second column region in the top view is a regular hexagon, the combined shape of the first column region and the third column region in the top view is a hollowed regular hexagon, and the shape of the third column region in the top view is half of the hollowed regular hexagon.
It will be understood that the application has been described in terms of several embodiments, and that various changes and equivalents may be made to these features and embodiments by those skilled in the art without departing from the spirit and scope of the application. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the application without departing from the essential scope thereof. Therefore, it is intended that the application not be limited to the particular embodiment disclosed, but that the application will include all embodiments falling within the scope of the appended claims.
Furthermore, it should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is provided for clarity only, and that the disclosure is not limited to the embodiments described in detail below, and that the embodiments described in the examples may be combined as appropriate to form other embodiments that will be apparent to those skilled in the art.
Claims (15)
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