CN119152900B

CN119152900B - On-chip terminal control circuit and memory

Info

Publication number: CN119152900B
Application number: CN202310685781.1A
Authority: CN
Inventors: 邵亚年; 严允柱
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2023-06-08
Filing date: 2023-06-08
Publication date: 2025-09-19
Anticipated expiration: 2043-06-08
Also published as: CN119152900A

Abstract

The present disclosure provides an on-chip terminal control circuit and memory. The on-chip terminal control circuit includes a decoder, a mode signal generating circuit, and a control signal generating circuit. The decoder is used to receive a command/address signal, and decode the command/address signal in the first clock cycle after the chip select signal corresponding to the command/address signal is at a valid level to generate an on-chip terminal command signal; the mode signal generating circuit is used to receive a chip select signal and an external clock signal, and based on the external clock signal, samples the level value of the chip select signal in the second clock cycle after the chip select signal is at a valid level to generate an on-chip terminal mode signal; the control signal generating circuit is coupled to the decoder and the mode signal generating circuit, and is used to receive an on-chip terminal command signal and an on-chip terminal mode signal, and generate an on-chip terminal control signal according to the on-chip terminal command signal and the on-chip terminal mode signal. The embodiment of the present disclosure can shorten the delay time of the ODT signal output.

Description

On-chip terminal control circuit and memory

Technical Field

The disclosure relates to the technical field of memories, and in particular relates to a terminal-on-chip control circuit and a memory using the same.

Background

On-Die Termination (ODT) techniques are used to match the Termination impedance of DRAM signals to the output impedance of the memory device to eliminate interference and distortion caused by signal reflections, providing better signal integrity and reliability for high speed memory systems.

In DDR5, the ODT signal is generated from a write command in a target mode, a write command in a non-target mode, or a read command in a non-target mode. In circuit design, it is necessary to match the ODT signal generation and transmission path (ODT path for short) with the DLL path. The DLL (Delay Locked Loop ) is a clock synchronization technique, and in a DDR5 memory, the DLL generates a phase difference through a feedback line and returns the phase difference to an input reference clock, and performs synchronization according to the feedback phase difference or signal delay, so as to ensure synchronization between an input clock and an output clock, and prevent a memory system from clock offset and timing distortion. The timing of the DLL paths needs to be consistent with the timing of the memory controller (ODT), and DRAM memory to achieve high speed data transfer and higher memory bandwidth.

In the related art, the delay time of the ODT path is much longer than that of the DLL path. Therefore, shortening the delay time of the ODT path is a challenge in DDR5 circuit design.

It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

An object of the present disclosure is to provide a terminal-on-chip control circuit and a memory for shortening the generation of ODT signals in the memory and the delay time of a transmission path.

According to a first aspect of the present disclosure, there is provided a terminal-on-chip control circuit applied to a memory, the terminal-on-chip control circuit including a decoder for receiving a command/address signal and decoding the command/address signal in a first clock period after receiving a chip select signal corresponding to the command/address signal to generate a terminal-on-chip command signal, a mode signal generating circuit for receiving the chip select signal and an external clock signal and sampling and detecting a pulse width of the chip select signal based on the external clock signal to generate a terminal-on-chip mode signal, wherein the terminal-on-chip mode signal indicates that the memory is in a target ODT mode or a non-target ODT mode, and a control signal generating circuit coupled to the decoder and the mode signal generating circuit for receiving the terminal-on-chip command signal and the terminal-on-chip mode signal and generating the terminal-on-chip control signal according to the terminal-on-chip command signal and the terminal-on-chip mode signal to cause the memory to perform a corresponding ODT operation according to the terminal-on-chip control signal.

In one exemplary embodiment of the present disclosure, the on-chip termination mode signal indicates that the memory is in the target ODT mode when the sampling detects that the pulse width of the chip select signal is one clock period of the external clock signal, and indicates that the memory is in the non-target ODT mode when the sampling detects that the pulse width of the chip select signal is two clock periods of the external clock signal.

In one exemplary embodiment of the present disclosure, the mode signal generating circuit includes a signal buffer for receiving a chip select signal and driving-amplifying the chip select signal to output, and a signal identifier connected to the signal buffer for receiving the driving-amplified chip select signal, the signal identifier being configured to output an on-chip termination mode signal in a first state to indicate that the memory is in a target ODT mode when it is determined that a pulse width of the chip select signal is only one clock period of an external clock signal, and to output an on-chip termination mode signal in a second state to indicate that the memory is in a non-target ODT mode when it is determined that the pulse width of the chip select signal is two clock periods of the external clock signal.

In an exemplary embodiment of the disclosure, the signal identifier includes a first sampling unit, a signal input end of the first sampling unit is used for receiving a chip selection signal after driving amplification, a clock input end of the first sampling unit is used for receiving an odd clock signal, the first sampling unit samples and outputs a level value of the chip selection signal in a clock period of a first external clock signal after receiving the chip selection signal based on the odd clock signal, a second sampling unit, a signal input end of the second sampling unit is connected with the signal input end of the first sampling unit and is used for receiving the chip selection signal after driving amplification, a clock input end of the second sampling unit is used for receiving an even clock signal, the second sampling unit samples and outputs the level value of the chip selection signal in a clock period of a second external clock signal after receiving the chip selection signal based on the even clock signal, the even clock signal and the odd clock signal have a frequency which is half of the external clock signal, the even clock signal is an inverted signal of the odd clock signal, and a logic processing unit is respectively connected with the first sampling unit and the second sampling unit and is used for carrying out a logic processing mode on a second sampling result or a first sampling terminal.

In an exemplary embodiment of the disclosure, the first sampling unit and the second sampling unit are both implemented by a D flip-flop, and the logic processing unit includes a nor gate, two input ends of the nor gate being connected to an output end of the first sampling unit and an output end of the second sampling unit, respectively, a SR latch, a first input end of the SR latch being connected to an output end of the nor gate, a second input end of the SR latch being configured to receive a reset signal, and an output end of the SR latch being configured to output an on-chip termination mode signal.

In an exemplary embodiment of the present disclosure, the logic processing unit further includes a clock counter having a first input terminal for receiving the command/address signal, a second input terminal for receiving the external clock signal, the clock counter for counting clock cycles of the external clock signal after the command/address signal is in an active state, and outputting a reset signal in the active state through the output terminal when the count value of the clock cycles reaches a preset value.

In one exemplary embodiment of the present disclosure, the decoder is further configured to generate an internal read/write command signal based on the command/address signal, and the control signal generation circuit determines a category of the on-chip termination command signal based on the internal read/write command signal.

In one exemplary embodiment of the present disclosure, the on-chip termination control signal includes a non-target read ODT signal, a non-target write ODT signal, and a target write ODT signal, the control signal generating circuit includes a logic unit having an input terminal, two control terminals, and three output terminals, the input terminal of the logic unit being configured to receive an on-chip termination command signal, the two control terminals of the logic unit being configured to receive an on-chip termination mode signal and an internal read/write command signal, the logic unit outputting the on-chip termination command signal from one of the three output terminals in response to the internal read/write command signal and the on-chip termination mode signal, and a signal processing unit respectively connected to the three output terminals of the logic unit for processing the on-chip termination command signal according to the output terminal outputting one of the non-target read ODT signal, the non-target write ODT signal, and the target write ODT signal.

In one exemplary embodiment of the present disclosure, a logic unit includes a read on die termination command gate unit having an input for receiving an on die termination command signal, a control for receiving an internal read/write command signal for outputting the on die termination command signal as an on die termination command signal when a read operation is performed on the internal read/write command signal, a write on die termination command gate unit having an input for receiving the internal read/write command signal, for outputting the on die termination command signal as an on die termination command signal when a write operation is performed on the internal read/write command signal, a first gate having an input for receiving the on die termination command signal, a control for receiving the on die termination mode signal when the on die termination mode signal is in a non-target mode, a first output for outputting the on die termination command signal as a non-target read initiation signal from a first output thereof, and a second output for outputting the on die termination command signal as a non-target ODT initiation signal when the on die termination command signal is in a non-target mode, a second gate having an input for receiving the on die termination command signal, a first output for outputting the on die termination command signal as an ODT termination signal from a second output for outputting the on die termination command signal when the on die termination command signal is in a non-target mode, a second gate for outputting the on die termination command signal from the on die termination signal when the on die termination command signal is in a non-target mode, and outputting the terminal command signal on the write chip as a target write ODT initial signal from a second output end of the terminal command signal on the write chip, wherein the first output end of the second gating device is a second output end of the logic unit, and the second output end of the second gating device is a third output end of the logic unit.

In an exemplary embodiment of the present disclosure, the signal processing unit includes three signal processing subunits, where the three signal processing subunits are connected to three output terminals of the logic unit in a one-to-one correspondence manner, and are configured to receive the non-target read ODT initial signal, the non-target write ODT initial signal, and the target write ODT initial signal, and perform pulse width adjustment and offset calibration on the non-target read ODT initial signal, the non-target write ODT initial signal, and the target write ODT initial signal, and then output the non-target read ODT signal, the non-target write ODT signal, and the target write ODT signal correspondingly.

In one exemplary embodiment of the present disclosure, the decoder includes a buffer for receiving and buffering command/address signals according to an external clock signal, and a command decoder connected to the buffer for decoding the command/address signals to generate on-chip terminal command signals.

According to a second aspect of the present disclosure there is provided a memory comprising an on-chip terminal control circuit as claimed in any one of the preceding claims.

According to the embodiment of the disclosure, the chip selection signal is used for judging whether the current command/address signal corresponds to the non-target ODT mode or the target ODT mode, and then the control signal generating circuit is used for processing the on-chip terminal command signal output by the decoder, so that the judgment of the command/address signal is executed in parallel, the output speed of the on-chip terminal control signal (ODT control signal) is improved, and the delay time of an ODT path is reduced.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort.

Fig. 1 is a schematic diagram of a configuration of an on-chip terminal control circuit in an exemplary embodiment of the present disclosure.

Fig. 2 is a schematic diagram of a chip select signal in one embodiment of the present disclosure.

Fig. 3 is a schematic diagram of a mode signal generation circuit in one embodiment of the present disclosure.

Fig. 4 is a schematic diagram of a signal identifier in one embodiment of the present disclosure.

FIG. 5 is a schematic diagram of a logic processing unit in one embodiment of the present disclosure.

Fig. 6 is a timing diagram of the logic processing unit shown in fig. 5.

Fig. 7 is a schematic diagram of a logic processing unit in another embodiment of the present disclosure.

Fig. 8 is a schematic diagram of a signal identifier in another embodiment of the present disclosure.

Fig. 9 is a timing diagram of the signal identifier shown in fig. 8.

Fig. 10 is a schematic diagram of a control signal generation circuit in one embodiment of the present disclosure.

FIG. 11 is a schematic diagram of a logic cell in one embodiment of the present disclosure.

Fig. 12 is a circuit diagram of a selector in one embodiment of the present disclosure.

Fig. 13 is a schematic diagram of a decoder in one embodiment of the present disclosure.

Fig. 14 is a schematic diagram of an on-chip termination control circuit in one embodiment of the present disclosure.

Fig. 15 is a timing difference diagram of on-chip termination command signals before and after application of an embodiment of the present disclosure.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many forms and should not be construed as limited to the examples set forth herein, but rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the present disclosure. One skilled in the relevant art will recognize, however, that the aspects of the disclosure may be practiced without one or more of the specific details, or with other methods, components, devices, steps, etc. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.

Furthermore, the drawings are only schematic illustrations of the present disclosure, in which the same reference numerals denote the same or similar parts, and thus a repetitive description thereof will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software or in one or more hardware modules or integrated circuits or in different networks and/or processor devices and/or microcontroller devices.

The following describes example embodiments of the present disclosure in detail with reference to the accompanying drawings.

Referring to fig. 1, the on-chip terminal control circuit 100 may include:

a decoder 1, configured to receive the command/address signal CA, and decode the command/address signal CA in a first clock period after the chip select signal CS corresponding to the command/address signal CA is at an active level, to generate an on-chip terminal command signal CODT;

A mode signal generating circuit 2 for receiving the chip select signal CS and the external clock signal CLK, and sampling a level value of a second clock period after the chip select signal CS is at an active level based on the external clock signal CLK to generate an on-chip termination mode signal S0, wherein the on-chip termination mode signal S0 indicates whether the memory is in a target ODT mode or a non-target ODT mode;

A control signal generation circuit 3 coupled to the decoder 1 and the mode signal generation circuit 2 for receiving the on-chip termination command signal CODT and the on-chip termination mode signal S0 and generating an on-chip termination control signal SODT according to the on-chip termination command signal CODT and the on-chip termination mode signal S0 to perform a corresponding ODT operation according to the on-chip termination control signal SODT.

In the DDR5 technology, a memory controller (controller) sends a chip select signal CS and a command/address signal CA to a memory (DRAM), where the chip select signal CS carries read/write command flag information, where the read/write command flag information is used to identify whether a read/write command in the command/address signal CA belongs to a non-target read/write command or a target read/write command. Wherein the non-target read-write commands include a non-target write command and a non-target read command, and the target read-write commands include a target write command.

The Non-target write command (Non-TARGET WRITE) is opposite the target write command (TARGET WRITE). The target write command refers to writing data to a memory address, while the non-target write command refers to writing data to other memory areas that are not target addresses. In DDR5 memory, non-target write commands may be used to pre-initiate the data transfer for the next access to increase the efficiency of the data exchange. Meanwhile, because the data in the memory can be processed in other areas, the non-target write command is also beneficial to reducing the requirement of memory access bandwidth and improving the overall performance of the memory system.

The Non-target read command (Non-TARGET READ) can read other relevant positions at the same time when the memory is read, and the transmission of the next target address is not required to be completed, so that the memory reading efficiency can be improved, the occupation of the memory bus bandwidth is reduced, and the overall performance of the memory is improved. With non-target read techniques, DDR5 memory may provide higher throughput at the same clock frequency, more than 50% higher than DDR4 memory.

Referring to fig. 2, in one embodiment, the chip select signal CS (labeled cs_nt) occupies two clock cycles of the external clock signal CLK, namely, the first clock cycle T1 and the second clock cycle T2, when the read/write command in the command/address signal CA belongs to a non-target read/write command, and occupies one clock cycle of the external clock signal CLK, namely, the first clock cycle T1, when the read/write command in the command/address signal CA belongs to a target read/write command.

In the embodiment shown in fig. 2, the active state of the chip select signal CS is a low level, and in other embodiments, the chip select signal CS may also be in other forms, so long as the chip select signal CS carries the read/write command flag information through the number of occupied clock cycles, which can all apply the technical solutions of the embodiments of the disclosure.

The embodiment of the present disclosure determines the chip select signal CS by using the mode signal generating circuit 2, outputs the on-chip termination mode signal S0 for indicating whether the memory is in the target ODT mode or the non-target ODT mode, and when the sampling detects that the pulse width of the chip select signal CS is a clock period of one external clock signal, the on-chip termination mode signal S0 indicates that the memory is in the target ODT mode, and when the sampling detects that the pulse width of the chip select signal CS is a clock period of two external clock signals, the on-chip termination mode signal S0 indicates that the memory is in the non-target ODT mode.

The control signal generating circuit 3 processes the on-chip termination command signal CODT output from the decoder 1 according to the on-chip termination mode signal S0 to output an on-chip termination control signal SODT, wherein the on-chip termination control signal SODT can be classified into three types of non-target read ODT signal, non-target write ODT signal, and target write ODT signal.

Next, the improved principle will be described in detail.

Referring to fig. 3, in one embodiment, the mode signal generating circuit 2 may include:

A signal buffer 21 for receiving the chip select signal CS, driving and amplifying the chip select signal, and outputting the chip select signal CS;

The input end of the signal identifier 22 is connected with the signal buffer 21 and is used for receiving the chip selection signal CS after driving and amplifying. The signal identifier 22 is configured to determine that the pulse width of the chip select signal CS is a few clock cycles, and output the on-chip terminal mode signal S0 in the first state when the pulse width of the chip select signal CS is determined to be only one clock cycle, and output the on-chip terminal mode signal S0 in the second state when the pulse width of the chip select signal CS is determined to be two clock cycles. The following clock periods refer to the clock periods of the external clock signal CLK, unless specifically emphasized.

The signal buffer 21 (buffer) is used for performing timing adjustment on the chip select signal CS, driving and amplifying the chip select signal CS, and outputting the chip select signal CS so as to align the chip select signal CS to the clock edge of the circuit, thereby ensuring that the chip select signal CS is in the correct clock period. Thus, the signal buffer 21 also receives the external clock signal CLK. In addition, the signal buffer 21 may amplify the chip select signal CS to increase its level change rate, reduce the influence of clock jitter on the signal, and the like, adjust the amplitude of the signal, to ensure the reliability of the chip select signal CS. Finally, the signal buffer 21 can protect the subsequent circuits from the influence of external environment, such as temperature change, electromagnetic signal interference and the like, and can also introduce an isolation region to protect devices from electrostatic discharge and voltage fluctuation, so that the signal transmission time sequence of the chip selection signal CS is ensured to be accurate, the error rate is reduced, and the reliability of the system is improved. The signal buffer 21 may be implemented by various circuits, and will not be described in detail in this disclosure.

It will be appreciated that the signal output by the signal buffer 21 is the chip select signal CS after adjustment and optimization, and the received chip select signal CS belongs to the same signal with different signal quality, and the signal output by the signal buffer 21 is still referred to as the chip select signal CS.

The signal identifier 22 may identify the duration of the active state (e.g., low level as described above) of the drive amplified chip select signal CS output by the signal buffer 21. In one embodiment, the signal identifier 22 uses the odd clock signal CLKE and the even clock signal CLKO to identify the duration of the active state of the chip select signal CS.

Fig. 4 is a schematic diagram of a signal identifier 22 in one embodiment of the present disclosure.

Referring to fig. 4, in one embodiment, the signal identifier 22 may comprise:

the first sampling unit 221, the signal input end of the first sampling unit 221 is used for receiving the chip selection signal CS, the clock input end of the first sampling unit 221 is used for receiving the odd clock signal CLKE, and the level value of the chip selection signal CS is sampled and output based on the odd clock signal CLKE in the first clock period T1;

The second sampling unit 222, the signal input end of the second sampling unit 222 is used for receiving the chip selection signal CS, the clock input end of the second sampling unit 222 is used for receiving the even clock signal CLKO, and the level value of the chip selection signal CS is sampled and output based on the even clock signal CLKO in the second clock period T2;

The logic processing unit 223 is connected to the output end of the first sampling unit 221 and the output end of the second sampling unit 222, and is configured to output the on-chip terminal mode signal S0 in the first state or the second state after performing logic processing based on the sampling results in the first clock period T1 and the second clock period T2.

In one embodiment, both the first sampling unit 221 and the second sampling unit 222 are implemented by D flip-flops. The D flip-flop has a data input D, a clock input and an output Q. When the rising edge of the level of the clock input signal arrives, the output Q of the D flip-flop will save the current signal state in a flip-flop element called a memory cell, depending on the state of the level of its input D. Since the D flip-flop is a synchronous flip-flop, an input signal can be recorded only when a rising edge of a clock signal arrives, so that stability and reliability of the sequential circuit can be ensured.

In the embodiment shown in fig. 4, the clock input of the D flip-flop of the first sampling unit 221 receives the Odd clock signal CLKE (CLK Even) to sample the chip select signal CS in the first clock period T1, and the clock input of the D flip-flop of the second sampling unit 222 receives the even clock signal CLKO (CLK Odd) to sample the chip select signal CS in the second clock period T2.

The kinds of clock signals in DDR5 may include a general external clock signal CLK, and an odd clock signal CLKE and an even clock signal CLKO generated according to odd and even bits of the external clock signal CLK, wherein the even clock signal CLKO and the odd clock signal CLKE are each half of the external clock signal CLK in frequency, and the even clock signal CLKO is an inverted signal of the odd clock signal CLKE. DDR5 memory clock frequencies have been very high, up to 4800MT/s, and the amount of data that needs to be transferred at the same time is reduced in order to ensure adequate signal stability and electrical performance. The clock signals are divided into even number bits and odd number bits, so that the mutual interference of the clock signals on different bits can be reduced, and the accuracy and the reliability of the time sequence circuit are improved. In addition, the clock signal speed of DDR5 works at double frequency, so that the frequency of the clock signal can be higher, the transmission delay of the clock edge of a small signal is avoided, the transmission rate and efficiency are improved, the bandwidth of a bus is increased, the delay and the waiting time of data transmission are effectively reduced, the memory transmission speed and the system performance can be improved, the power consumption is reduced, the memory transmission performance is optimized, and the system performance is improved.

The embodiment shown in fig. 4 uses the odd clock signal CLKE and the even clock signal CLKO to control two sampling units, and samples the chip select signal CS in two clock cycles to determine the extension time of the valid state of the chip select signal CS, so that the embodiment can effectively work when the valid state of the chip select signal CS is in both low level or high level, and increases the circuit adaptability.

Referring to fig. 5, in one embodiment, the logic processing unit 223 may include:

The NOR gate NOR has two input ends connected to the output end of the first sampling unit 221 and the output end of the second sampling unit 222, respectively;

The first input end of the SR latch TG is connected with the input end of the NOR gate NOR, the second input end of the SR latch TG is used for receiving a reset signal, and the output end of the SR latch TG is used for outputting an on-chip terminal mode signal S0.

The SR latch TG may be implemented by a flip-flop composed of two nor gates.

Fig. 6 is a timing diagram of the logic processing unit shown in fig. 5. The operation principle of the logic processing unit shown in fig. 5 is explained below with reference to the timing chart shown in fig. 6.

Referring to the left side of fig. 6, when the active state of the chip select signal CS is low and the chip select signal CS occupies one clock period (the first clock period T1), the sampling result S211 of the first sampling unit 221 is 0 before the next rising edge of the odd clock signal CLKE arrives, the sampling result S222 of the second sampling unit 222 is always 1, the output signal SNOR of the NOR gate NOR is always 0, and the sr latch TG outputs s0=1 when the reset signal Rst is in an inactive state, i.e., the on-chip terminal mode signal S0 in the first state.

Referring to the right side of fig. 6, when the active state of the chip select signal CS is low and the chip select signal CS occupies two clock cycles (the first clock cycle T1 and the second clock cycle T2), the sampling result S221 of the first sampling unit 221 is 0 before the next rising edge of the odd clock signal CLKE comes, the sampling result S222 of the second sampling unit 222 is 0 before the next rising edge of the even clock signal CLKO comes, the output signal SNOR of the NOR gate NOR is 1 between the rising edge of the even clock signal CLKO and the next rising edge of the odd clock signal CLKE, and the sr latch TG starts outputting s0=0 at the rising edge of the even clock signal CLKO when the reset signal Rst is in the inactive state, that is, the on-chip termination mode signal S0 of the second state. The SR latch TG can adjust the state of the on-chip termination mode signal S0 again based on the output signal SNOR of the NOR gate NOR only when the reset signal Rst is in an active state. That is, the reset signal Rst may be used to maintain the state duration of the on-chip termination mode signal S0.

As can be seen from the timing chart shown in fig. 6, the on-chip termination mode signal S0 can be output before the end of the second clock cycle after the chip select signal CS is in an active state, and the signal output speed is fast.

In one embodiment, the logic processing unit 223 may further include a circuit that controls the reset signal Rst.

Referring to fig. 7, in another embodiment, the logic processing unit 223 may further include a clock counter CN, a first input terminal of the clock counter CN is configured to receive the command/address signal CA, a second input terminal of the clock counter CN is configured to receive the clock signal CLK, count clock cycles of the external clock signal CLK after the command/address signal CA is in an active state, and output a reset signal Rst in an active state through an output terminal when the count value of the clock cycles reaches a preset value.

Wherein the preset value is, for example, equal to 128. That is, the reset signal Rst is in an active state at the 129 th clock period after the command/address signal CA is in an active state. In conjunction with the timing diagram shown in fig. 6, the state of the on-chip termination mode signal S0 is maintained unchanged after the output signal of the NOR gate NOR is changed and before the reset signal Rst is in an active state, so that the control signal generating circuit 3 has enough time to output the on-chip termination control signal SODT based on the state of the on-chip termination mode signal S0.

In other embodiments of the present disclosure, the first input terminal of the clock counter CN may further receive the chip select signal CS, count clock cycles of the external clock signal CLK after the chip select signal CS is in an active state, and output the reset signal Rst in an active state through the output terminal when the count value of the clock cycles reaches a preset value.

In addition to sampling the chip select signal CS for two clock cycles, in another embodiment, the signal identifier 22 may sample the chip select signal CS for a second clock cycle (e.g., phase T2 shown in fig. 2) after the chip select signal CS is in an active state. If the sampling of the chip select signal CS during the second clock period T2 shows that the chip select signal CS is in an active state (e.g., low level), the signal identifier 22 may output the on-chip termination mode signal S0 in the second state to indicate that the on-chip termination command signal CODT belongs to a non-target read-write command or to indicate that the on-chip termination control signal is in a non-target ODT mode. If the sampling result of the chip select signal CS shows that the chip select signal CS is in an inactive state (e.g., high level) during the second clock period, the signal identifier 22 may output the on-chip termination mode signal S0 in the first state to indicate that the on-chip termination command signal CODT belongs to the target read-write command or to indicate that the on-chip termination control signal is in the target ODT mode.

Referring to fig. 8, in another embodiment, the signal identifier 22 may include a second sampling unit 222, an SR latch TG, and an inverter OP. The second sampling unit 222 has a signal input for receiving the chip select signal CS and a clock input for receiving the even clock signal CLKO, and the second sampling unit 222 samples the chip select signal CS during the second clock period T2. The first input terminal of the SR latch TG is connected to the output terminal of the second sampling unit 222, and the second input terminal is used for receiving the reset signal. The input end of the inverter OP is connected to the output end of the SR latch TG for outputting the on-chip termination mode signal S0.

The structure of the SR latch TG may be the same as the embodiment shown in fig. 5, or may be different from the embodiment shown in fig. 5, and when the structure of the SR latch TG is the same as the embodiment shown in fig. 5 and the definition of the first state and the second state of the on-chip termination mode signal S0 is the same as the embodiment shown in fig. 5, the output terminal of the SR latch TG may be connected to an odd number of inverters OP to ensure that the first state and the second state of the on-chip termination mode signal S0 correctly correspond to the sampling result of the second sampling unit 222.

Fig. 9 is a timing diagram of the signal identifier shown in fig. 8.

Referring to fig. 9, in the embodiment shown in fig. 8, when the active state of the chip select signal CS is low and the chip select signal CS occupies one clock cycle (the first clock cycle T1), the sampling result S222 of the second sampling unit 222 is always 1, the output signal STG of the sr latch TG is always 0, and the inverter OP always outputs s0=1, i.e., the on-chip terminal mode signal S0 in the first state.

When the active state of the chip select signal CS is low and the chip select signal CS occupies two clock cycles (a first clock cycle T1 and a second clock cycle T2), the sampling result S222 of the second sampling unit 222 is 0 between two rising edges of the even clock signal CLKO, the output signal of the sr latch TG starts to be 1 at the first rising edge of the even clock signal CLKO, and at the same time, the inverter OP outputs s0=1, i.e. the on-chip terminal mode signal S0 in the second state. When the reset signal Rst is in an inactive state, the output signal state of the SR latch TG is unchanged, and when the reset signal Rst is in an active state, the SR latch TG can adjust the state of the output signal STG again based on the sampling result S222 of the second sampling unit 222. Wherein the reset signal Rst may be used to maintain the state duration of the on-chip termination mode signal S0. The generation circuit of the reset signal Rst may be, for example, a circuit shown in fig. 7.

As can be seen from the timing chart shown in fig. 9, the on-chip termination mode signal S0 can be output before the end of the second clock cycle after the chip select signal CS is in an active state, and the signal output speed is fast.

The embodiment shown in fig. 8 samples the chip select signal CS only in the second clock period T2 after the chip select signal CS is in the active state, so that circuit configuration can be saved, and power consumption and layout area can be reduced. But this approach can only correspond to the case where the active state of the chip select signal CS is fixed.

In the embodiment of the present disclosure, the decoder 1 is further configured to generate an internal read/write command signal RW based on the command/address signal CA, and the control signal generating circuit 3 determines the category of the on-chip termination command signal CODT according to the internal read/write command RW signal.

Referring to fig. 10, in one embodiment, the control signal generation circuit 3 may include:

A logic unit 31 having an input terminal, two control terminals and three output terminals, the input terminal of the logic unit 31 being connected to the decoder 1 for receiving the on-chip terminal command signal CODT, the two control terminals of the logic unit 31 being connected to the decoder 1 and the connection mode signal generating circuit 2, respectively, for receiving the internal read/write command signal RW and the on-chip terminal mode signal S0, the logic unit 31 being adapted to output the on-chip terminal command signal CODT from one of the three output terminals based on the internal read/write command signal RW and the on-chip terminal mode signal S0;

the signal processing unit 32 is connected to three output terminals of the logic unit 31, and is configured to process the on-chip terminal command signal CODT according to the output terminal outputting the on-chip terminal command signal CODT, so as to output one of the non-target read ODT signal, the non-target write ODT signal, and the target write ODT signal.

In the embodiment shown in fig. 10, the signal processing unit 32 may be connected to three output terminals of the logic unit 31 through three sub-units, namely, a first sub-unit 321, a second sub-unit 322 and a third sub-unit 323, where the first sub-unit 321 is configured to process a non-target read ODT initial signal output by the logic unit 31, perform pulse width adjustment and offset calibration on the non-target read ODT initial signal to output a non-target read ODT signal, the second sub-unit 322 is configured to process a non-target write ODT initial signal, perform pulse width adjustment and offset calibration on the non-target write ODT initial signal to output a non-target write ODT signal, and the third sub-unit 323 is configured to process a target write ODT initial signal, and perform pulse width adjustment and offset calibration on the target write ODT initial signal to output a target write ODT signal.

The first sub-unit 321, the second sub-unit 322, and the third sub-unit 323 each have a delay offset (LATENCY SHIFTS) function and an offset generation (Offset generation) function. The delay offset (LATENCY SHIFTS) function can dynamically adjust the timing parameters of the DRAM memory to optimize the response speed and data throughput of the memory system. The technology can dynamically adjust the delay (Latency) of the DRAM according to the change of the memory load, thereby adapting to the access requirements of the memory under different loads and improving the overall performance and response speed of the memory system. Specifically, the delay offset function may improve read performance by reducing read latency of the DRAM memory or improve write performance by increasing latency. In addition, the delay offset function can also adjust functions of the write and read galleries of the memory system according to the change of the CPU load. By dynamically adjusting the memory delay, the delay offset function can improve the flexibility and adaptability of the memory system, thereby optimizing memory access performance and improving the overall efficiency and reliability of the system. The offset generation function is used for generating an offset in the memory access command. The offset is a pointer value that indicates the difference between the memory address and the location of the read and write data. When the CPU requests to read or write data at one of the relative addresses, an offset will be added to the basic address of the memory to derive the actual physical address. Because DDR5 memory is typically high density, high speed, the offset needs to be handled frequently in order to achieve a corresponding memory access latency when processing large amounts of data. The offset generation function can reduce the load of the CPU and improve the memory access performance and efficiency. Meanwhile, the offset generation function can help to create an efficient address mapping table so as to optimize stack management and page table access of the memory storage and improve the performance and reliability of the memory system.

When the types of the internal read/write command signals RW are different and the states of the on-chip terminal mode signals S0 are different, the logic unit 31 outputs the on-chip terminal command signals CODT through only one output terminal at a time, that is, only one of the first subunit 321, the second subunit 322, and the third subunit 323 receives the on-chip terminal command signal CODT for one CA signal transmission, processes and outputs the on-chip terminal command signal CODT, processes the on-chip terminal command signals CODT differently, and the control signal generating circuit 3 outputs the on-chip terminal control signals SODT differently in output paths, thereby identifying that the types of the on-chip terminal control signals SODT are different.

Referring to fig. 11, in one embodiment, the logic unit 31 may include:

The on-chip terminal command strobe unit 311 has an input end for receiving the on-chip terminal command signal CODT, and a control end for receiving the internal read/write command signal RW, and outputting the on-chip terminal command signal CODT as the on-chip terminal command signal R-CODT when the internal read/write command signal RW indicates to perform a read operation;

The on-chip terminal command strobe unit 312 has an input end for receiving the on-chip terminal command signal CODT, and a control end for receiving the internal read/write command signal RW, and outputting the on-chip terminal command signal CODT as the on-chip terminal command signal W-CODT when the internal read/write command signal RW indicates that a write operation is performed;

the first gate 313 has an input end, a control end, a first output end and a second output end, wherein the input end of the first gate 313 receives the read on-chip termination command signal R-CODT, the control end of the first gate 313 receives the on-chip termination mode signal S0, and the first gate 313 is used for outputting the read on-chip termination command signal R-CODT as a non-target read ODT initial signal from the first output end thereof when the on-chip termination mode signal S0 indicates that the read on-chip termination mode signal is in a non-target ODT mode;

The second gate 314 has an input terminal, a control terminal, a first output terminal and a second output terminal, the input terminal of the second gate 314 receives the on-die termination command signal W-CODT, the control terminal of the second gate receives the on-die termination mode signal S0, the second gate 314 is used for outputting the on-die termination command signal W-CODT as a non-target ODT initiation signal from the first output terminal thereof when the on-die termination mode signal S0 indicates a non-target ODT mode, the second gate 314 is also used for outputting the on-die termination command signal W-CODT as a target ODT initiation signal from the second output terminal thereof when the on-die termination mode signal S0 indicates a target ODT mode, wherein the first output terminal of the second gate 314 is the second output terminal of the logic unit 31, and the second output terminal of the second gate 314 is the third output terminal of the logic unit 31.

Wherein the on-chip termination mode signal S0 is used to control whether the first gate 313 outputs the read on-chip termination command signal R-CODT to the signal processing unit 32 or control the second gate 314 to output the write on-chip termination command signal W-CODT to the signal processing unit 32 through the first input terminal of the second gate 314 or the second output terminal of the second gate.

When the internal read/write command signal RW is a read command, the on-chip terminal command strobe unit 311 performs a transcoding process on the on-chip terminal command signal CODT and outputs the on-chip terminal command signal R-CODT, for example, performs a burst length generation process (Burst lenth generation, BLG). BLG is an important function in DDR5 memory controllers for generating Burst Length information in memory commands. The Burst Length refers to the number of data blocks contained in the data transmitted continuously by the memory data channel. The BLG dynamically generates optimal Burst Length information according to a specific data mode requested by the processor by reading a memory mapping table in the memory so as to optimize the access efficiency and response speed of the memory system. Because the Burst Length is used, a plurality of memory access requests can be combined together, the transmission times of a memory bus can be greatly reduced, and the transmission efficiency and the bandwidth of the memory are greatly improved. In addition, by using the BLG function, the latency of the memory bus can be reduced, making memory access faster and more efficient.

The BLG is performed by the on-chip termination command strobe unit 311, which mainly widens the pulse width of the on-chip termination command signal CODT, because burst length needs to serially read/write a string of data, and it needs to be ensured that the corresponding ODT signal should remain valid, i.e. a sufficient pulse width needs to be ensured, when a string of data is read/written.

Correspondingly, the first gate 313 can receive an input signal (read on-chip terminal command signal R-CODT) and the second gate 314 cannot receive an input signal (write on-chip terminal command signal W-CODT). Since the control terminal of the first gate 313 is connected to the output terminal of the mode signal generating circuit 2, the first gate 313 outputs the received on-chip terminal command signal R-CODT through the first output terminal when the on-chip terminal mode signal S0 is in the first state (s0=1, indicating the non-target read-write mode), and the first gate 313 can output the on-chip terminal command signal R-CODT through the second output terminal thereof when the on-chip terminal mode signal S0 is in the second state (s0=0, indicating the target read-write mode), but since the signal of the target read mode does not need to be processed in this link, the second output terminal of the first gate 313 is empty.

When the internal read/write command signal RW is a write command, the on-chip terminal command strobe unit 312 performs a transcoding process on the on-chip terminal command signal CODT and outputs the on-chip terminal command signal W-CODT), for example, a burst length generation process. Correspondingly, the first gate 313 cannot receive an input signal (read on-chip terminal command signal R-CODT) and the second gate 314 can receive an input signal (write on-chip terminal command signal W-CODT). Since the control terminal of the second gate 314 is connected to the output terminal of the mode signal generating circuit 2, when the on-chip terminal mode signal S0 is in the first state (s0=1, indicating the non-target read/write mode), the second gate 314 outputs the received on-chip terminal command signal W-CODT through its first output terminal to indicate that the on-chip terminal command signal W-CODT is in the non-target write mode, and when the on-chip terminal mode signal S0 is in the second state (s0=0, indicating the target read/write mode), the second gate 314 outputs the received on-chip terminal command signal W-CODT through its second output terminal to indicate that the on-chip terminal command signal W-CODT is in the target write mode.

The BLG is performed by the on-chip terminal command strobe unit 312, and mainly widens the pulse width of the on-chip terminal command signal CODT, which is the same as that of the on-chip terminal command strobe unit 311, and will not be described again.

The signal processing unit 32 performs signal processing using different sub-units according to different ports of the received signal to output the on-chip terminal control signal SODT.

Fig. 12 is a circuit diagram of a selector in one embodiment of the present disclosure. The first gate 313 and the second gate 314 in the embodiment shown in fig. 11 may be implemented by using the gate structure shown in fig. 12.

Referring to fig. 12, the gate 1200 includes a first and gate A1, a second and gate A2, and an inverting unit O1, wherein first input terminals of the first and gate A1 and the second and gate A2 each receive an input signal S, a second input terminal of the first and gate A1 receives a control signal CON, and a second input terminal of the second and gate A2 receives an inverted signal \con of the control signal CON processed by the inverting unit O1. The inverting unit O1 may be implemented by any circuit having a signal inverting function.

When the control signal CON is 1, the signal at the second input end of the first AND gate A1 is 1, the output signal of the first AND gate A1 changes along with the input signal S, the signal at the second input end of the second AND gate A2 is 0 output by the inverting unit O1, and the second AND gate A2 constantly outputs 0. In this case, when the input signal S has a high level pulse, the high level pulse can be output through the output terminal of the first and gate A1, and the output terminal of the second and gate A2 has no pulse output.

When the control signal CON is 0, the signal at the second input end of the first and gate A1 is 0, the output signal of the first and gate A1 is constant 0, the signal at the second input end of the second and gate A2 is 1 output by the inverting unit O1, and the output signal of the second and gate A2 varies with the input signal S. In this case, when the input signal S has a high level pulse, the high level pulse can be output through the output terminal of the second and gate A2, and the output terminal of the first and gate A1 has no pulse output.

Thus, by setting the value of the control signal CON to be different, the output signal S can be set to be output from a certain output terminal (the output terminal of the first and gate A1 or the output terminal of the second and gate A2) of the gate 1200, and signal gating is achieved.

In addition to the circuit shown in fig. 12, the gate can be implemented by two transmission gates. For example, the input ends of the first transmission gate and the second transmission gate are set to receive the input signal S, and the control signals of the first transmission gate and the second transmission gate are set to be opposite in phase, so that the first transmission gate can output the signal S when the control signal is a first value, the second transmission gate can output the signal S when the control signal is a second value, and the first transmission gate can output no signal. In this embodiment, one input of the transmission gate is in a high-impedance state, and no output signal is generated.

The implementation manner of the transmission gate can be various, and those skilled in the art can set the transmission gate according to the actual situation, which is not particularly limited in this disclosure.

Referring to fig. 13, in one embodiment, the decoder 1 may include:

a buffer 11 for receiving and buffering a command/address signal CA according to an external clock signal CLK;

The command decoder 12 is connected to the output of the buffer 11 for decoding the command/address signal CA to generate the on-chip terminal command signal CODT.

The buffer 11 may be divided into a command/address signal buffer 111 and an external clock signal buffer 121 to adjust and optimize a command/address signal CA and an external clock signal CLK, the decode flip-flop 12 is composed of a plurality of D flip-flops (DFFs) connected in parallel to receive and buffer the command/address signal CA according to the external clock signal CLK, the command decoder 12 judges whether the command/address signal CA corresponds to a write command or a read command, and generates and outputs an internal read/write command signal RW indicating whether the on-chip terminal command signal CODT is a read type or a write type for further processing by the on-chip terminal command gating unit 311 and the on-chip terminal command gating unit 312 shown in fig. 11, based on the decoding result.

Unlike the related art, the decoder 1 of the embodiment of the present disclosure does not set a function of distinguishing whether the on-chip terminal command signal CODT belongs to a non-target read-write command or a target read-write command, and therefore, the decoder 1 can accelerate the speed of outputting the on-chip terminal command signal CODT and increase the output speed of the overall on-chip terminal control signal SODT.

Fig. 14 is a schematic diagram of an on-chip termination control circuit in one embodiment of the present disclosure. The embodiment shown in fig. 14 includes the decoder 1 of the embodiment shown in fig. 13, the mode signal generation circuit 2 of the embodiment shown in fig. 7, and the control signal generation circuit 3 shown in fig. 11.

In other embodiments of the present disclosure, the decoder 1 may further include other structures, for example, the command decoder 12 in the decoder 1 may be implemented in various known manners, the control signal generating circuit 3 may be implemented by other logic circuits than the logic circuit 31 shown in fig. 11, and various logic circuits may be built according to the logic according to the embodiments of the present disclosure as long as the logic is satisfied that the control signal generating circuit 3 is capable of outputting a non-target read ODT signal when the on-chip terminal mode signal S0 is in the second state and the internal read/write command signal RW is in the read type, the control signal generating circuit 3 is capable of outputting a non-target write ODT signal when the on-chip terminal mode signal S0 is in the second state and the internal read/write command signal RW is in the write type, and the control signal generating circuit 3 is capable of outputting a target write ODT signal when the on-chip terminal mode signal S0 is in the first state and the internal read/write command signal RW is in the write type.

Referring to the left side of fig. 15, before the embodiment of the present disclosure is applied, the on-chip terminal command signal CODT is output at the first clock cycle after the command/address signal CA is completely output, and referring to the right side of fig. 15, after the embodiment of the present disclosure is applied, the on-chip terminal command signal CODT is output at the second clock cycle when the command/address signal CA is at an active level, and the output timing of the on-chip terminal command signal CODT is accelerated by one clock cycle.

For the subsequent control signal generating circuit 3, the received on-chip termination command signal CODT is earlier, and the formation of the on-chip termination mode signal S0 does not occupy the time for the control signal generating circuit 3 to process signals, therefore, the control signal generating circuit 3 can output the earlier on-chip termination control signal SODT based on the earlier on-chip termination command signal CODT to control the subsequent ODT operation earlier, shorten the ODT path delay time, make the ODT path delay and the DLL path delay more match, and optimize the overall timing of the memory.

According to a second aspect of the present disclosure, there is provided a memory, employing the on-chip terminal control circuit of any one of the embodiments above. The memory provided by the embodiment of the disclosure has better timing matching performance.

It should be noted that although in the above detailed description several modules or units of a device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit in accordance with embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into a plurality of modules or units to be embodied.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any adaptations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. An on-chip termination control circuit, characterized in that it is applied to a memory, comprising:

a decoder for receiving a command/address signal and decoding the command/address signal within a first clock cycle after receiving a chip select signal corresponding to the command/address signal to generate an on-chip terminal command signal;

a mode signal generating circuit, configured to receive the chip select signal and an external clock signal, and sample and detect a pulse width of the chip select signal based on the external clock signal to generate an on-chip termination mode signal; wherein the on-chip termination mode signal indicates whether the memory is in a target ODT mode or a non-target ODT mode;

a control signal generating circuit coupled to the decoder and the mode signal generating circuit, configured to receive the on-chip terminal command signal and the on-chip terminal mode signal, and generate an on-chip terminal control signal according to the on-chip terminal command signal and the on-chip terminal mode signal, so as to enable the memory to perform a corresponding ODT operation according to the on-chip terminal control signal.

2. The on-chip termination control circuit according to claim 1 is characterized in that when sampling detects that the pulse width of the chip select signal is one clock cycle of the external clock signal, the on-chip termination mode signal indicates that the memory is in the target ODT mode; when sampling detects that the pulse width of the chip select signal is two clock cycles of the external clock signal, the on-chip termination mode signal indicates that the memory is in the non-target ODT mode.

3. The on-chip termination control circuit according to claim 1 or 2, wherein the mode signal generating circuit comprises:

A signal buffer, configured to receive the chip select signal, drive and amplify the chip select signal, and then output the signal;

A signal identifier is connected to the signal buffer and is used to receive the chip select signal after driving and amplification. The signal identifier is used to output the on-chip termination mode signal in a first state to indicate that the memory is in the target ODT mode when it is determined that the pulse width of the chip select signal is only a clock cycle of the external clock signal, and to output the on-chip termination mode signal in a second state to indicate that the memory is in the non-target ODT mode when it is determined that the pulse width of the chip select signal is two clock cycles of the external clock signal.

4. The on-chip termination control circuit according to claim 3, wherein the signal identifier comprises:

a first sampling unit, wherein a signal input end of the first sampling unit is used to receive the chip select signal after driving and amplification, a clock input end of the first sampling unit is used to receive an odd clock signal, and the first sampling unit samples a level value of the chip select signal within a clock cycle of a first external clock signal after receiving the chip select signal based on the odd clock signal and outputs the sampled value;

a second sampling unit, wherein a signal input end of the second sampling unit is connected to the signal input end of the first sampling unit, and is used to receive the chip select signal after driving and amplification; a clock input end of the second sampling unit is used to receive an even clock signal; the second sampling unit samples the level value of the chip select signal based on the even clock signal within a clock cycle of a second external clock signal after receiving the chip select signal, and then outputs the sampled value; wherein the frequency of the even clock signal and the odd clock signal is half of the external clock signal, and the even clock signal is an inverted signal of the odd clock signal;

A logic processing unit is connected to the first sampling unit and the second sampling unit respectively, and is used to perform logic processing on the sampling results of the first sampling unit and the second sampling unit and then output the on-chip terminal mode signal of the first state or the second state.

5. The on-chip termination control circuit according to claim 4 , wherein the first sampling unit and the second sampling unit are both implemented by D flip-flops, and the logic processing unit comprises:

a NOR gate, wherein two input terminals of the NOR gate are respectively connected to the output terminal of the first sampling unit and the output terminal of the second sampling unit;

An SR latch, wherein a first input end of the SR latch is connected to the output end of the NOR gate, a second input end of the SR latch is used to receive a reset signal, and an output end of the SR latch is used to output the on-chip termination mode signal.

6. The on-chip termination control circuit according to claim 5, wherein the logic processing unit further comprises:

A clock counter, wherein the first input end of the clock counter is used to receive the command/address signal, the second input end of the clock counter is used to receive the external clock signal, and the clock counter is used to count the clock cycles of the external clock signal after the command/address signal is in a valid state, and when the count value of the clock cycle reaches a preset value, output the reset signal in a valid state through the output end.

7. The on-chip terminal control circuit as described in claim 1 is characterized in that the decoder is also used to generate an internal read/write command signal based on the command/address signal, and the control signal generation circuit determines the category of the on-chip terminal command signal according to the internal read/write command signal.

8. The on-chip termination control circuit according to claim 7, wherein the on-chip termination control signal comprises a non-target read ODT signal, a non-target write ODT signal, and a target write ODT signal, and the control signal generating circuit comprises:

a logic unit having an input terminal, two control terminals, and three output terminals, wherein the input terminal of the logic unit is used to receive the on-chip terminal command signal, the two control terminals of the logic unit are used to receive the on-chip terminal mode signal and the internal read/write command signal, and the logic unit outputs the on-chip terminal command signal from one of the three output terminals in response to the internal read/write command signal and the on-chip terminal mode signal;

The signal processing unit is respectively connected to the three output ends of the logic unit, and is used to process the on-chip terminal command signal according to the output end that outputs the on-chip terminal command signal to output one of a non-target read ODT signal, a non-target write ODT signal, and a target write ODT signal.

9. The on-chip termination control circuit according to claim 8, wherein the logic unit comprises:

a read on-chip terminal command strobe unit, having an input end for receiving the on-chip terminal command signal, a control end for receiving the internal read/write command signal, and being configured to output the on-chip terminal command signal as a read on-chip terminal command signal when the internal read/write command signal indicates a read operation;

a write on-chip terminal command strobe unit, having an input end for receiving the on-chip terminal command signal, a control end for receiving the internal read/write command signal, and being configured to output the on-chip terminal command signal as a write on-chip terminal command signal when the internal read/write command signal indicates a write operation;

a first gate having an input terminal, a control terminal, a first output terminal, and a second output terminal, wherein the input terminal of the first gate receives the read on-chip terminal command signal, and the control terminal of the first gate receives the on-chip terminal mode signal; the first gate is configured to output the read on-chip terminal command signal as a non-target read ODT initial signal from its first output terminal when the on-chip terminal mode signal indicates a non-target ODT mode; wherein the first output terminal of the first gate is the first output terminal of the logic unit;

The second gate has an input end, a control end, a first output end and a second output end. The input end of the second gate receives the write on-chip terminal command signal, and the control end of the second gate receives the on-chip terminal mode signal; the second gate is used to output the write on-chip terminal command signal as a non-target write ODT initial signal from its first output end when the on-chip terminal mode signal indicates that it is in a non-target ODT mode; the second gate is also used to output the write on-chip terminal command signal as a target write ODT initial signal from its second output end when the on-chip terminal mode signal indicates that it is in a target ODT mode; wherein the first output end of the second gate is the second output end of the logic unit, and the second output end of the second gate is the third output end of the logic unit.

10. The on-chip termination control circuit according to claim 9, wherein the signal processing unit comprises three signal processing sub-units, which are connected to the three output terminals of the logic unit in a one-to-one correspondence, and are respectively configured to receive the non-target read ODT initial signal, the non-target write ODT initial signal, and the target write ODT initial signal, and respectively output the non-target read ODT signal, the non-target write ODT signal, and the target write ODT signal after performing pulse width adjustment and offset calibration on the non-target read ODT initial signal, the non-target write ODT initial signal, and the target write ODT initial signal.

11. The on-chip termination control circuit according to claim 1 , wherein the decoder comprises:

a buffer, configured to receive and buffer the command/address signal according to an external clock signal;

A command decoder is connected to the buffer, decodes the command/address signal, and generates the on-chip terminal command signal.

12. A memory, comprising the on-chip termination control circuit according to any one of claims 1 to 11.