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CN119149450A - Cache resource allocation device, memory access control device and chip - Google Patents

Cache resource allocation device, memory access control device and chip Download PDF

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Publication number
CN119149450A
CN119149450A CN202411303165.6A CN202411303165A CN119149450A CN 119149450 A CN119149450 A CN 119149450A CN 202411303165 A CN202411303165 A CN 202411303165A CN 119149450 A CN119149450 A CN 119149450A
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China
Prior art keywords
cache
capacity
partition
cacheline
address data
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CN202411303165.6A
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Inventor
张学利
黎勇
吴志伟
李阳
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Shenzhen Yunbao Intelligent Co ltd
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Shenzhen Yunbao Intelligent Co ltd
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Priority to CN202411303165.6A priority Critical patent/CN119149450A/en
Publication of CN119149450A publication Critical patent/CN119149450A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0871—Allocation or management of cache space
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

The application relates to a Cache resource configuration device, a memory access control device and a chip, which comprise an access monitoring module, a partition capacity adjustment module and a capacity adjustment module, wherein the access monitoring module is used for receiving an access request transmitted by a peripheral, acquiring equipment ID and virtual address data according to the access request, counting the access flow of a Cache partition corresponding to the equipment ID in a current period according to the virtual address data, sending the virtual address data to a fully-associative Cache, and sending the access flow to the capacity adjustment module, wherein the fully-associative Cache comprises a plurality of Cache partitions, each Cache partition corresponds to one equipment ID, each peripheral is endowed with a unique equipment ID, and the partition capacity adjustment module is used for dynamically adjusting the allocation capacity of the Cache partitions periodically according to the access flow of the peripheral in the current period. The application can improve the effective utilization rate of the fully-connected Cache resources.

Description

Cache resource allocation device, memory access control device and chip
Technical Field
The application relates to the technical field of integrated circuit development, in particular to a Cache resource allocation device, a memory access control device and a chip.
Background
In a system supporting an Input/output address translation unit (Input/Output Memory Management Unit, IOMMU) or a system address translation unit (System Memory Management Unit, SMMU), the IOMMU or SMMU provides address services to each peripheral (external device), virtual addresses are provided when the peripheral accesses, the virtual addresses are translated into physical addresses by the IOMMU or SMMU, and then access the memory, and the IOMMU or SMMU is introduced in the process to perform address translation.
In order to improve the efficiency of peripheral memory access, a common processing technology is to set an address translation buffer unit (Translation Local Buffer, TLB) in the IOMMU or SMMU, after the IOMMU or SMMU performs an address translation, the information related to the address translation is buffered in the TLB, and when the address translation of the same Page (Page) is performed next time, if the address translation hits in the Entry (Entry) in the TLB, the physical address can be directly obtained to skip the flow of the address translation, so as to reduce the memory access delay caused by the address translation of the peripheral.
In order to increase the hit rate, the TLB is generally configured as a fully associative structure. In use, all peripherals connected to the IOMMU or SMMU may use the TLB, while the densities sent to the transport stream by the various peripherals are different, neither balanced, have temporal and spatial uncertainties, if a less important peripheral bursts a large DMA operation for a certain period of time, it may cause the entire TLB to be fully occupied by the peripheral, which may affect the address translation performance of the remaining peripheral.
Disclosure of Invention
The application aims to provide a Cache resource allocation device, a memory access control device and a chip, so as to improve the effective utilization rate of fully-connected Cache resources.
In order to achieve the above object, according to a first aspect of the present application, there is provided a Cache resource allocation apparatus, including:
the receiving module is used for receiving an access request transmitted by a peripheral, acquiring equipment ID and virtual address data according to the access request, acquiring a DEVID according to the equipment ID, and sending the DEVID and the virtual address data to the access monitoring module;
the access monitoring module is used for receiving the DEVID and the virtual address data, counting the access flow of the Cache partition corresponding to the DEVID in the current period according to the virtual address data, sending the virtual address data to the fully-associative Cache and sending the access flow to the capacity adjustment module, wherein the fully-associative Cache comprises a plurality of Cache partitions;
and the partition capacity adjustment module is used for periodically and dynamically adjusting the allocation capacity of the plurality of cache partitions according to the access flow of the plurality of cache partitions in the current period.
According to a second aspect of the present application, there is provided a memory access control device, including an address translation unit, a fully associative Cache, and a Cache resource allocation device according to the first aspect of the present application;
The address translation unit is used for receiving the access request transmitted by the peripheral equipment and forwarding the access request to the Cache resource allocation device;
The fully-associated Cache comprises a Cache controller and a Cache memory;
The Cache controller is configured to determine physical address data corresponding to the virtual address data in the fully associative Cache according to the virtual address data, if yes, take out hit physical address data from the corresponding group CACHELINE and send the hit physical address data to the memory controller to access the memory, and if no, return a miss result to the address translation unit;
The address translation unit is further configured to obtain virtual address data according to the miss result and the access request, translate the virtual address data into physical address data, send the current translated physical address data to the memory controller to access a memory, and send the current translated physical address data to the Cache controller;
The Cache controller is further configured to store or discard the currently translated physical address data into one of the corresponding banks CACHELINE.
According to a third aspect of the present application, there is provided a chip, including the Cache resource allocation apparatus according to the first aspect of the present application, or including the memory access control apparatus according to the second aspect of the present application.
The implementation of the Cache resource allocation device, the memory access control device and the chip has the following beneficial effects:
the access monitoring module is used for counting the access flow of each peripheral to each Cache partition of the fully-associated Cache, and dynamically adjusting the allocation capacity of the corresponding Cache partition of each peripheral according to the access flow of each Cache partition in the current period, so that the fully-associated Cache resources are dynamically adjusted according to the actual access requirements of a plurality of peripheral, the fully-associated Cache resources can be more reasonably allocated to each peripheral, the situation that the plurality of peripheral share one IOMMU or SMMU can be adapted, and the problem that the Cache of the whole TLB is occupied by the peripheral due to the fact that a certain less important peripheral bursts of large-section DMA operation, and the address translation performance of the subsequent other peripheral is affected is solved.
Drawings
In order to more clearly illustrate the embodiments of the present application, the drawings used in the description of the embodiments or the prior art will be briefly described below, it being obvious that the drawings in the description below are only some embodiments of the present application, and that other drawings may be obtained from these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a framework structure of a Cache resource allocation device according to an embodiment of the present application.
FIG. 2 is a flow chart of a first beat of cache partition allocation capacity adjustment in one embodiment of the application.
FIG. 3 is a flow chart of a second beat of cache partition allocation capacity adjustment in one embodiment of the application.
Fig. 4 is a schematic frame structure of a memory access control device according to an embodiment of the application.
Fig. 5 is a schematic circuit diagram of a memory access control device according to an embodiment of the present application.
FIG. 6 is a schematic diagram of a Cache memory according to an embodiment of the application.
Detailed Description
The detailed description of the drawings is intended as an illustration of some embodiments of the application and is not intended to represent the only forms in which the application may be practiced. It is to be understood that the same or equivalent functions may be accomplished by different embodiments that are intended to be encompassed within the spirit and scope of the application.
Referring to fig. 1, an embodiment of the present application provides a Cache resource allocation apparatus, including an access monitoring module and a partition capacity adjustment module;
The access monitoring module is used for receiving an access request transmitted by a peripheral, acquiring equipment ID and virtual address data according to the access request, counting the access flow of a Cache partition corresponding to the equipment ID in the current period according to the virtual address data, sending the virtual address data to the fully-connected Cache, and sending the access flow to the capacity adjustment module, wherein the fully-connected Cache comprises a plurality of Cache partitions, each Cache partition corresponds to one equipment ID, and each peripheral is endowed with a unique equipment ID.
The access monitoring module is used for monitoring virtual address data of each peripheral sent by the receiving module and carrying out periodic access flow statistics, and comprises a plurality of counters, wherein the equipment ID of each peripheral corresponds to one counter, each counter is respectively used for counting the access flow of the corresponding Cache partition in the current period and corresponding to the equipment ID, and then the counting result (access flow) of each counter is sent to the partition capacity adjusting module.
The partition capacity adjustment module is used for periodically and dynamically adjusting the allocation capacity of the cache partitions according to the access flow of the peripherals in the current period.
Specifically, the Cache resource allocation device may further include a timer, and when the count of the timer is greater than the TIME threshold value with software allocation, the dynamic adjustment of allocation capacity of the plurality of Cache partitions according to the statistics result of each counter is triggered. The allocation capacity of a Cache partition refers to CACHELINE numbers allocated to the Cache partition, CACHELINE is one storage unit of the Cache.
For example, if the access traffic of a certain Cache partition is high, it indicates that the peripheral associated with the Cache partition needs more Cache resources to improve the access efficiency, and thus the partition capacity adjustment module may increase the number CACHELINE of the Cache partition. Conversely, if the access traffic of a certain Cache partition is low, indicating that its currently allocated Cache resources may be excessive, the CACHELINE number of that Cache partition may be reduced, and the excess resources allocated to other partitions that need them more. Such dynamic adjustment may be implemented based on various policies, including but not limited to most frequently used priority (MRU), least Recently Used (LRU), or other custom algorithms.
In some specific embodiments, the partition capacity adjustment module is further configured to:
Acquiring access flow rates of the plurality of cache partitions in the current period according to the access flow of the plurality of cache partitions in the current period;
if the access flow rate of any cache partition in the current period is greater than the access flow rate of any cache partition in the previous period, acquiring a flow rate increment DeltaV of the any cache partition, if DeltaV is larger than DeltaV max, the any cache partition needs to be subjected to capacity increment and the capacity increment is determined, and if DeltaV is smaller than DeltaV min, the any cache partition needs to be subjected to capacity decrement and the capacity decrement is determined, wherein DeltaV max and DeltaV min are preset thresholds;
if the access flow rate of any cache partition in the current period is smaller than the access flow rate of any cache partition in the previous period, the capacity of any cache partition is required to be reduced, and the capacity reduction of any cache partition is determined;
And adjusting the allocation capacity of the plurality of cache partitions according to the capacity increment and the capacity decrement.
Specifically, when the allocation capacity of the plurality of cache partitions is dynamically adjusted according to the statistics result of each counter, the partition capacity adjustment module calculates a real-TIME rate corresponding to each equipment ID, where the rate calculation mode is to divide a real-TIME access flow value of the cache partition corresponding to the equipment ID in a current period by a TIME threshold value adjust_time_th to obtain the real-TIME access flow rate corresponding to the equipment ID, and the adjust_time_th can be understood as adjustment period TIME.
Further, the analysis is performed based on the real-time access traffic rate obtained by calculation, for the i-th device ID, the access traffic rate calculated in real time by the cache partition corresponding to the device ID in the current period is represented by V n, the access traffic rate calculated by the cache partition corresponding to the device ID in the previous period is represented by V f, the V n-Vf value of the i-th device ID is represented by Δv i, the threshold value of the difference between the access traffic rates before and after the capacity allocation needs to be increased is represented by Δv max, and the threshold value of the difference between the access traffic rates before and after the capacity allocation needs to be reduced is represented by Δv min, which includes:
When V f<Vn is calculated, deltaV i＝Vn-Vf is calculated, and when DeltaV i>ΔVmax is calculated, the allocation capacity of the cache partition corresponding to the ith device ID is increased;
When DeltaV min<＝ΔV<＝ΔVmax, the allocation capacity of the buffer memory partition corresponding to the ith equipment ID does not need to be adjusted;
When V f>Vn or (V f<Vn)&&(ΔVi<ΔVmin), it means that the allocation capacity of the buffer partition corresponding to the i-th device ID should be reduced.
It should be noted that the increment and decrement of the allocation capacity may be customized, for example, the capacity of each increment or decrement of the fixed value may be increased or decreased, and the increment or decrement may be obtained based on, for example, multiplying the current allocation capacity by a preset coefficient, which is merely illustrative, and the embodiment is not limited thereto.
In some specific embodiments, the partition capacity adjustment module is further configured to:
Acquiring the allocation capacity of a cache partition corresponding to a preset equipment ID, determining the allocable capacity according to the sum of the allocation capacity of the cache partition corresponding to the preset equipment ID and the capacity decrement of the cache partition needing capacity reduction, and determining the sum of capacity increment according to the capacity increment of the cache partition needing capacity increment;
When the allocable capacity is larger than or equal to the sum of the capacity increments, increasing the allocation capacity of the corresponding cache partition according to the capacity increment of the cache partition needing capacity increase, reducing the allocation capacity of the corresponding cache partition according to the capacity decrement of the cache partition needing capacity reduction, and updating the allocation capacity of the cache partition corresponding to the preset equipment ID;
when the allocable capacity is smaller than the sum of the capacity increments, the allocation capacity of the corresponding cache partition is reduced according to the capacity decrement of the cache partition needing to be reduced, the allocation capacity of the cache partition needing to be increased is kept unchanged, and the allocation capacity of the cache partition corresponding to the preset equipment ID is updated.
Specifically, in this embodiment, a preset device ID is set, where the preset device ID is indicated by a dev_last_id, where the dev_last_id corresponds to a cache partition, but the dev_last_id does not have a peripheral device corresponding to the dev_last_id, and the cache partition corresponding to the dev_last_id is reserved for assisting in dynamically adjusting and controlling the allocation capacity of the cache partition corresponding to each other device ID, that is, CACHELINE of the cache partition corresponding to the dev_last_id may be used for serving as the capacity increase of other cache partitions.
Specifically, at the beginning of each adjustment period, the partition capacity adjustment module first determines the allocation capacity of the buffer partition corresponding to the current dev_last_id, that is, CACHELINE numbers of buffer partitions corresponding to the dev_last_id, which are defined as dev_last_id_t for convenience of description, and further, the partition capacity adjustment module obtains the allocable capacity by adding the dev_last_id_t to the sum of the capacity reductions of all the buffer partitions needing to be reduced, where the buffer partitions needing to be reduced refer to those buffer partitions with low access flow and CACHELINE numbers of buffer partitions needing to be reduced in allocation capacity. Meanwhile, the partition capacity adjustment module calculates the sum of capacity increment of all the cache partitions needing to be increased, wherein the cache partitions needing to be increased refer to those cache partitions with high access flow and CACHELINE numbers of allocation capacity needing to be increased.
The partition capacity adjustment module compares the sum of the allocatable capacity and the capacity increment of the cache partition to be capacity-increased, and the following two possible cases are:
In the first case, the allocable capacity is greater than or equal to the sum of capacity increments, if the allocable capacity is enough, the capacity adjustment can be normally performed, then the partition capacity adjustment module increases the allocated capacity according to the capacity increment of each cache partition needing capacity increase, and meanwhile, the partition capacity adjustment module also decreases the allocated capacity according to the capacity decrement of each cache partition needing capacity decrease. After these adjustments, the partition capacity adjustment module updates the dev_last_id_t to reflect the new allocation.
And secondly, if the allocatable capacity is less than the sum of capacity increment, the partition capacity adjustment module can not increase the allocation capacity of any cache partition needing capacity increment if the allocatable capacity is insufficient to meet the requirements of all the cache partitions needing capacity increment, but can still reduce the allocation capacity according to the capacity decrement of the cache partition needing capacity decrement, so that some capacity is released. After these adjustments, the partition capacity adjustment module also updates dev_last_id_t.
In this way, the partition capacity adjustment module can ensure that the allocation of the Cache resources is balanced, and the Cache resources can be dynamically adjusted according to actual demands in the running process of the whole system, so that the mechanism is beneficial to maximizing the utilization efficiency of the Cache and avoiding resource waste.
In some specific embodiments, the capacity increment and capacity decrement of any cache partition in each period are both Δp, where Δp is a preset integer value and represents the number of CACHELINE that is increased or decreased, and the allocated capacity of the cache partition represents the number of CACHELINE that the cache partition contains.
Specifically, in order to facilitate quick operation, two parameters add_num and dec_num are defined in this embodiment, where add_num×Δp represents the number of up to CACHELINE in the Cache that is not allocated for the next time period after adjustment, dec_num×Δp represents the number of down to CACHELINE in the Cache that is not allocated for the next time period after adjustment, the initial values of add_num and dec_num are 0 during each adjustment, and the functions of the partition capacity adjustment module are described in detail below based on the above parameter definitions, and can be performed in two beats (one beat is one clock period) during capacity adjustment.
The first beat is to preliminarily determine whether the cache partition corresponding to each device ID is increased, unchanged or reduced in size, and the determining process of the increase, unchanged or reduced in size of the cache partition corresponding to each device ID may refer to fig. 2, which includes:
step1.1, judging the size between V n and V f, if V f>Vn,, indicating that the allocation capacity of the buffer partition corresponding to the ith device ID needs to be reduced by ΔP, and meanwhile, adding 1 to ADD_NUM and 1 to DEV_NUM_MAX_N_t=DEV_NUM_MAX_N- ΔP;
step1.2, obtaining the value of DeltaV i＝Vn-Vf corresponding to each equipment ID, judging whether DeltaV i is smaller than DeltaV min, if yes, reducing the allocation capacity of the cache partition corresponding to the equipment ID by DeltaP, adding 1 to ADD_NUM, and adding 1 to DEV_NUM_MAX_N_t=DEV_NUM_MAX_N-DeltaP, otherwise, carrying out step1.3;
step1.3 when ΔV min<＝ΔVi<＝ΔVmax, the allocation capacity of the cache partition corresponding to the device ID remains unchanged, while ADD_NUM remains unchanged;
When Δv i>ΔVmax indicates that the allocation capacity of the cache partition corresponding to the device ID increases by Δp, and simultaneously, dec_num_max_n_t=dev_num_max_n+Δp is added by 1;
Where dev_num_max_n represents the current allocation capacity of the cache partition with device ID N, and dev_num_max_n_t represents the allocation capacity of the cache partition with device ID N after adjustment.
The second beat is used for further determining whether the cache partition corresponding to each device ID increases, does not change or decreases, and the determining process may refer to fig. 3, including:
step2.1, judging whether DEV_LAST_ID_t+ADD_NUM is larger than DEC_NUM;
step2.2, when dev_last_id_t+add_num > = dec_num, indicates that there is enough unallocated cacheline for DEV to be added, when the registers are used for software parameter configuration, the value of dev_num_max_n_t can be updated to the corresponding registers at this time
In the DEV_NUM_MAX_N, meanwhile, the allocation capacity of the buffer area corresponding to the DEV_LAST_ID is updated to DEV_LAST_ID_t+ADD_NUM-DEC_NUM, and the round of adjustment is finished;
step2.3, when DEV_LAST_ID_t+ADD_NUM < DEC_NUM, indicates that there is insufficient remainder CACHELINE for the cache partition to be added, at which point
The value of DEV_NUM_MAX_N_t < DEV_NUM_MAX_N is updated to the corresponding register DEV_NUM_MAX_N, namely the volume reduction adjustment of the cache partition is normally executed, and meanwhile, the value of the allocation capacity of the cache partition corresponding to the DEV_LAST_ID is updated as follows
The number of CACHELINE corresponding to the cache partition to be increased is kept unchanged, and the round of adjustment is ended.
Based on the description of the above embodiments, the Cache resource allocation device in this embodiment counts the access flow of each peripheral to each Cache partition of the fully-associated Cache through the access monitoring module, and periodically dynamically adjusts the allocation capacity of the Cache partition corresponding to each peripheral according to the access flow of each Cache partition in the current period, so as to dynamically adjust the fully-associated Cache resource according to the actual access requirements of a plurality of peripherals, so that the fully-associated Cache resource can be more reasonably allocated to each peripheral, and adapt to the situation that a plurality of peripherals share one IOMMU or SMMU, and solve the problem that the Cache of the whole TLB is fully occupied by the peripheral due to burst of a large-section DMA operation of a certain less important peripheral, thereby affecting the address translation performance of the subsequent other peripheral.
Referring to fig. 4, another embodiment of the present application further provides a memory access control apparatus, including an address translation unit, a fully associative Cache, and a Cache resource allocation apparatus according to the foregoing embodiment;
the fully-associated Cache is an adjustment object aimed at by the Cache resource allocation device of the embodiment, and comprises a plurality of Cache partitions, each Cache partition comprises a plurality of CACHELINE, and each Cache partition corresponds to one equipment ID.
The Cache controller is configured to determine physical address data corresponding to the virtual address data in the fully associative Cache according to the virtual address data, if yes, take out hit physical address data from the corresponding group CACHELINE and send the hit physical address data to the memory controller to access the memory, and if no, output a miss result to the address translation unit, specifically, when the Cache controller receives the virtual address data, the Cache controller checks whether physical address data corresponding to the virtual address data exists in a corresponding Cache partition of the Cache memory, which is referred to as Cache hit check. If physical address data corresponding to the virtual address data is found in the corresponding Cache partition (i.e., a Cache hit), then the Cache controller will fetch the hit physical address data from CACHELINE of that Cache partition. The Cache controller then sends this physical address data to the memory controller, which uses this physical address data to access the data in the memory. If no physical address data corresponding to the virtual address data is found in the corresponding Cache partition (i.e., a Cache miss), the Cache controller will return a miss to the address translation unit, which tells the address translation unit that the physical address data corresponding to the requested virtual address data is not stored in the Cache, and therefore further processing of the access request is required, i.e., translation into physical address data, i.e., address translation functions performed in the background, such as IOMMU or SMMU.
The address translation unit is configured to obtain virtual address data according to the miss result and the access request, translate the virtual address data into physical address data, send the current translated physical address data to the memory controller to access the memory, and send the current translated physical address data to the Cache controller.
Specifically, when the Cache controller notifies the address translation unit of a Cache miss, the address translation unit will take action to process the missed access request, the address translation unit obtains virtual address data, which is the address that the peripheral originally requested access to, and the address translation unit translates the virtual address data into physical address data. Address translation is an important function of memory management, which translates virtual addresses (addresses used by peripherals) into physical addresses (addresses in real memory). The address translation unit sends the translated physical address data to the memory controller, which is the component responsible for actually accessing the physical memory hardware, which uses this physical address to read or write the data in memory. Meanwhile, the address translation unit also sends the translated physical address data to the Cache controller, so that after the memory access is completed, the Cache controller can store the address into the Cache memory, and the corresponding physical address can be directly found in the Cache memory by the same virtual address request in the future, so that the access efficiency is improved.
The Cache controller is further configured to store or discard the currently translated physical address data into one of the corresponding banks CACHELINE.
Specifically, after the address translation unit has completed translating the virtual address to the physical address and has sent the physical address data to the Cache controller, the Cache controller needs to decide whether to store (or fill) this physical address data into one CACHELINE of the fully-associative caches. If it is decided to store, this CACHELINE will record the current translated physical address data so that the Cache can provide fast access when the peripheral accesses the same virtual address again in the future. In some cases, the Cache controller may decide not to store this physical address data, e.g., because of limited Cache space, while current Cache policies (e.g., least Recently Used (LRU) or random replacement) indicate that existing data should be replaced, e.g., the access pattern of the data indicates that it is unlikely to be accessed again, and thus storing in the Cache may not provide performance benefits, e.g., some data may need to be discarded according to particular Cache policies or system requirements in order to maintain Cache consistency.
It should be noted that, the memory access control apparatus described in this embodiment may be regarded as an apparatus similar to an input/output address translation unit (IOMMU) or a system address translation unit (SMMU), where IOMMU and SMMU are hardware components for performing address translation and access control between a device (such as a peripheral) and a system memory, but the memory access control apparatus of this embodiment has the following improvements over the conventional IOMMU or SMMU:
(1) The memory access control device in this embodiment includes a Cache resource allocation device, which allows dynamic adjustment of allocation of fully-associated Cache resources, which means that the allocation of fully-associated Cache resources can be optimized according to actual use conditions of the peripheral, rather than static allocation, and this dynamic performance can improve the utilization rate of the Cache and the overall performance of the system.
(2) By dynamically adjusting the Cache resources, the hit rate of the Cache can be optimized according to the actual access flow of the peripheral, and the condition of Cache miss is reduced, so that the number of times and delay of accessing the memory are reduced. The dynamic Cache resource allocation enables the system to be better adapted to different workloads and access modes, and is also convenient to expand when more peripheral devices or more complex access modes need to be supported in the future.
The improvement enables the memory access control device to be more efficient and flexible in processing the memory access request of the peripheral, and particularly in the scene of multi-peripheral and high concurrent access, the performance and the expandability of the system can be obviously improved.
In some specific embodiments, referring to fig. 5, the memory access control apparatus further includes a scheduling control module;
The Cache controller is further configured to obtain a device ID corresponding to the access request and a device ID corresponding to each CACHELINE in the corresponding Cache partition, further obtain a priority corresponding to the device ID corresponding to the access request and a priority corresponding to the device ID corresponding to each CACHELINE, and output the priority to the scheduling control module, where the device ID corresponding to CACHELINE is a device ID corresponding to the stored data of CACHELINE.
Specifically, the Cache controller obtains the device ID corresponding to the access request (i.e., the device ID corresponding to the peripheral ID) and the device ID corresponding to each CACHELINE in the corresponding Cache partition (i.e., the device ID corresponding to the stored data of CACHELINE). Next, the Cache controller further obtains a priority corresponding to the device ID corresponding to the access request and a priority corresponding to the device ID corresponding to each stripe CACHELINE, where these priority information are used to determine which data should be stored in the Cache, and which data should be replaced when the Cache memory space is insufficient. After the information is acquired, the Cache controller outputs the information to a dispatching control module, and the dispatching control module determines whether to store the physical address data into a Cache memory according to the information.
The scheduling control module is configured to determine whether to store the currently translated physical address data into one CACHELINE of the corresponding group according to the priority corresponding to the device ID corresponding to the access request and the priority corresponding to the device ID corresponding to each CACHELINE, and return a determination result to the Cache controller;
Specifically, the scheduling control module decides whether to store the physical address data in the Cache according to the priority of the device ID corresponding to the access request and the priority of the device ID corresponding to each stripe CACHELINE, where the decision is based on the storage policy of the Cache, for example, but not limited to, least Frequently Used (LFU), most frequently used (LFU), or partition priority policy, and the like, according to the determination result of the scheduling control module.
The Cache controller is further configured to store the physical address data of the current translation into one CACHELINE of the corresponding group or discard the physical address data according to the determination result.
Specifically, the Cache controller decides whether to store the current translated physical address data into one of the corresponding banks CACHELINE or discard this data.
To sum up, in this embodiment, when the Cache controller decides to store new data into the Cache memory, how to process the acquisition of the idle CACHELINE and priority information and how to cooperate with the scheduling control module to decide the storage policy of the data, where the policy can optimize the use efficiency of the fully-associative Cache and reduce the delay of memory access.
In some specific embodiments, the scheduling control module is further configured to determine whether at least one free CACHELINE exists in the corresponding cache partition, if yes, store the currently translated physical address data into any free CACHELINE, and if not, determine to discard the currently translated physical address data when the priority corresponding to the device ID corresponding to the access request is lower than the priority corresponding to the device ID corresponding to any CACHELINE in the corresponding cache partition.
Specifically, the dispatch control module first checks if there is at least one free CACHELINE (i.e., unoccupied CACHELINE) in the corresponding cache partition, and if there is free CACHELINE, meaning that this CACHELINE is not currently storing any valid data and can be used to store new physical address data, the dispatch control module will determine to store the currently translated physical address data into free CACHELINE. Therefore, when the same virtual address request exists again, the Cache can quickly provide physical address data, and the times of accessing the memory are reduced. If there is no spare CACHELINE, further, when the schedule control module receives the device ID and its priority corresponding to the access request provided by the Cache controller, and the device ID and its priority corresponding to each stripe CACHELINE in the corresponding group, it compares these priorities. If the priority of the device ID corresponding to the access request is lower than the priority of the device ID corresponding to any one CACHELINE of the corresponding group, this means that the physical address data of the access request has a lower priority than the data that is currently most needed to be kept in the Cache. In this case, the dispatch control module will decide to discard the currently translated physical address data, meaning that this data will not be stored in the Cache. The decision can avoid storing low-priority data into the Cache, so that the data in the Cache is kept to be the most needed high-priority data at present, the Cache resource can be ensured to be most effectively utilized, and meanwhile, the Cache miss condition caused by storing the low-priority data is reduced. With this strategy, the system can process access requests more efficiently because the data in the Cache is the most likely data to be accessed, which helps to improve the overall performance and response speed of the system.
In some specific embodiments, the scheduling control module is further configured to select, when a priority corresponding to the device ID corresponding to the access request is higher than or equal to a priority corresponding to the device ID corresponding to the at least one CACHELINE of the corresponding cache partitions, at least one CACHELINE with a lowest priority from the at least one CACHELINE, and select, from the at least one CACHELINE with a lowest priority, one CACHELINE with a minimum number of uses in a last preset time, for storing the currently translated physical address data.
Specifically, when the dispatch control module receives the device ID and its priority corresponding to the access request provided by the Cache controller, and the device ID and its priority corresponding to each of the CACHELINE in the corresponding group, it compares these priorities. If the priority of the device ID corresponding to the access request is higher than or equal to the priority of the device ID corresponding to at least one CACHELINE in the corresponding group, this means that the data priority of the access request is higher, and needs to be kept in the Cache preferentially. In this case, the scheduling control module may select CACHELINE with the lowest priority from the at least one CACHELINE, where CACHELINE with the lowest priority means that the data stored by it is not the data that is currently most needed to be kept in the Cache, and at this time, there may be one or at least two CACHELINE with the lowest priority. If there is only one lowest priority CACHELINE, then the lowest priority CACHELINE is determined to be used for storing the current translated physical address data, if there are at least two lowest priority CACHELINE, the scheduling control module selects the one CACHELINE with the least number of uses in the latest preset time from the at least two lowest priority CACHELINE, namely, determines the CACHELINE to be replaced and stored based on the least use (LRU) policy, and finally, the scheduling control module returns the selected CACHELINE information to the Cache controller to tell the Cache controller to store the current translated physical address data into the CACHELINE with the least number of uses. By the method, the data in the Cache can be ensured to be the most likely accessed data, and meanwhile, the Cache replacement strategy is followed, so that the efficiency and the performance of the Cache are maintained.
In some specific embodiments, the Cache memory further includes a priority data module, where the priority data module is configured to store priority information corresponding to each device ID, and an LRU module, where the LRU module is configured to store a number of times each stripe CACHELINE is used in a last preset time.
Specifically, as shown in fig. 6, each stripe CACHELINE includes a Tag, data, and a device ID, where the Tag is used to store all information (i.e. Tag 0-Tag n in fig. 6) that can uniquely identify each peripheral transport stream, each stripe CACHELINE corresponds to one Tag, the Data is used to store valid Data, i.e. translated physical address Data (i.e. Data 0-Data n in fig. 6), in the Data stream, and the device ID is used to store a device ID (i.e. DEVID 0-DEVID n in fig. 6) corresponding to the cached Data of each CACHELINE. The LRU module is used for recording the latest use times M of each piece CACHELINE, when CACHELINE is needed to be replaced, CACHELINE with the latest use times M is replaced preferentially according to the record in the LRU module, the priority data module is used for storing priority information corresponding to each equipment ID, the priority data module can be formed by a RAM, the depth of the RAM is the maximum number of supported equipment IDs, and the Cache controller can read the priority information of the corresponding equipment IDs from the priority data module and the CACHELINE use times record from the LRU module and then send the priority information to the scheduling control module to carry out CACHELINE replacement storage decision.
In some specific embodiments, the scheduling control module is further configured to determine the priority corresponding to each device ID according to the allocated capacity and the actual used capacity of the storage partition corresponding to each device ID, and the unallocated capacity.
Specifically, in this embodiment, a parameter dev_num_n is further set, where dev_num_n represents the number CACHELINE actually occupied by the Cache partition with the device ID N, and the scheduling control module counts the value of dev_num_n in real time, and sets, according to the size relationship between the value in dev_num_max_n and dev_num_n, a priority dev_pri_n corresponding to each device ID, where the value of the priority is buffered together with data into a priority data module (DEV PRI RAM) of the corresponding CACHELINE when performing Cache allocation, where the priority setting manner is as shown in table 1 below:
TABLE 1
For parameter configuration of the hardware circuit, the apparatus of the present embodiment further includes a status register module (CSR) for storing status values of various parameters of the hardware circuit, which includes
A plurality of status registers such as dev_num_max_ (N), adjust_time_th, dev_num_ (N), dev_pri_ (N), and the like, as shown in table 2 below:
TABLE 2
The timer counts TIME, compares with the adjust_time_th set in the status register module, and when the TIME is greater than the adjust_time_th, sends a pulse signal to the allocation capacity adjustment module, triggers the capacity allocation adjustment of each cache partition, and then the timer starts counting again from 0 for a new round.
Based on the priorities defined in table 2 and the status registers defined in table 1, the working flows of the Cache controller and the dispatch control module of this embodiment are further described, which specifically includes the following steps:
step3.1, when unoccupied CACHELINE exists in the corresponding Cache partition of the Cache, directly distributing the physical address data of the current translation to unoccupied CACHELINE, adding 1 to the corresponding DEV_NUM_N value, and ending the distribution of the physical address data of the current translation, otherwise, performing step3.2;
The step3.2 includes:
When CACHELINE in the Cache is occupied, reading the device ID corresponding to each CACHELINE stored data in the Cache, thereby obtaining the priority DEV_PRI of each CACHELINE, and meanwhile, obtaining the self DEV_PRI_N from the status register module through the newly received device ID (assumed to be N) of the access request, and then judging as follows:
(a) When DEV_PRI_N=1, reading out the statistical count M of all LRU modules corresponding to CACHELINE which are the same as the equipment ID of the access request in the Cache, replacing the current translated physical address data into CACHELINE with the minimum M value according to the LRU algorithm, wherein all state registers do not need to be changed;
(b) When dev_pri_n=2, it is found whether CACHELINE of dev_pri_i=1 exists in the Cache. If the DEV_PRI_i=1 corresponding to CACHELINE, reading out the statistical count M of the LRU module, replacing the current translated physical address data into CACHELINE with the minimum M value according to the LRU algorithm, adding 1 to the DEV_NUM_N value corresponding to the equipment ID of the access request, and subtracting 1 from the replaced DEV_NUM_i value corresponding to CACHELINE;
(c) When dev_pri_n=2 and CACHELINE of dev_pri_i=1 does not exist in the Cache, the statistical count M of all LRU modules corresponding to CACHELINE in the Cache is read out, the physical address data of the current translation is replaced into CACHELINE with the minimum M value according to the LRU algorithm, the dev_num_n value corresponding to the device ID of the access request is added by 1, and the dev_num_i value corresponding to the replaced CACHELINE is subtracted by 1.
The application also provides a chip, which comprises the Cache resource allocation device according to the embodiment.
Another embodiment of the present application further provides a chip, including a memory access control device according to the foregoing embodiment.
The foregoing description of embodiments of the application has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the technical improvements in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims (11)

1.一种Cache资源配置装置，其特征在于，包括：1. A cache resource configuration device, comprising: 访问监控模块，用于接收外设传输的访问请求，根据所述访问请求获取设备ID和虚拟地址数据，根据所述虚拟地址数据统计所述设备ID对应的缓存分区在当前周期的访问流量，将所述虚拟地址数据发送至全相联Cache，并将所述访问流量发送至容量调整模块；其中，所述全相联Cache包括多个缓存分区，每个缓存分区对应一个设备ID，每个外设赋予一个唯一的设备ID；An access monitoring module is used to receive an access request transmitted by a peripheral device, obtain a device ID and virtual address data according to the access request, count the access traffic of the cache partition corresponding to the device ID in the current cycle according to the virtual address data, send the virtual address data to the fully associative cache, and send the access traffic to the capacity adjustment module; wherein the fully associative cache includes multiple cache partitions, each cache partition corresponds to a device ID, and each peripheral device is assigned a unique device ID; 分区容量调整模块，用于周期性地根据多个外设在当前周期的访问流量对所述多个缓存分区的分配容量进行动态调整。The partition capacity adjustment module is used to periodically and dynamically adjust the allocated capacity of the multiple cache partitions according to the access traffic of multiple peripherals in the current cycle. 2.根据权利要求1所述的Cache资源配置装置，其特征在于，所述分区容量调整模块，进一步用于：2. The cache resource configuration device according to claim 1, wherein the partition capacity adjustment module is further used to: 根据所述多个缓存分区在当前周期的访问流量获取所述多个缓存分区在当前周期的访问流量速率；Acquire access traffic rates of the multiple cache partitions in the current cycle according to the access traffic of the multiple cache partitions in the current cycle; 若任一缓存分区在当前周期的访问流量速率大于其在上一周期的访问流量速率，则获取该任一缓存分区的流量速率增量ΔV，若ΔV>ΔVmax，则该任一缓存分区需进行增容，并确定其容量增量；若ΔV<ΔVmin，则该任一缓存分区需进行减容，并确定其容量减量；其中，ΔVmax和ΔVmin为预设的阈值；If the access traffic rate of any cache partition in the current cycle is greater than the access traffic rate in the previous cycle, the traffic rate increment ΔV of any cache partition is obtained. If ΔV>ΔV max , the capacity of any cache partition needs to be increased, and its capacity increment is determined; if ΔV<ΔV min , the capacity of any cache partition needs to be reduced, and its capacity reduction is determined; wherein ΔV max and ΔV min are preset thresholds; 若任一缓存分区在当前周期的访问流量小于其在上一周期的访问流量速率，则该任一缓存分区需进行减容，并确定其容量减量；If the access traffic rate of any cache partition in the current cycle is less than the access traffic rate in the previous cycle, the capacity of any cache partition needs to be reduced, and the capacity reduction is determined; 根据所述容量增量和容量减量对所述多个缓存分区的分配容量进行调整。The allocated capacities of the plurality of cache partitions are adjusted according to the capacity increment and the capacity decrement. 3.根据权利要求2所述的Cache资源配置装置，其特征在于，所述分区容量调整模块，进一步用于：3. The cache resource configuration device according to claim 2, wherein the partition capacity adjustment module is further used to: 获取预设设备ID对应的缓存分区的分配容量，根据所述预设设备ID对应的缓存分区的分配容量和需减容的缓存分区的容量减量之和确定可分配容量，并根据需增容的缓存分区的容量增量确定容量增量之和；Obtain the allocated capacity of the cache partition corresponding to the preset device ID, determine the allocatable capacity according to the sum of the allocated capacity of the cache partition corresponding to the preset device ID and the capacity reduction of the cache partition to be reduced, and determine the sum of the capacity increment according to the capacity increment of the cache partition to be increased; 当所述可分配容量大于等于所述容量增量之和时，根据需增容的缓存分区的容量增量对对应缓存分区的分配容量进行增大设置，并根据需减容的缓存分区的容量减量对对应缓存分区的分配容量进行减小设置，并更新所述预设设备ID对应的缓存分区的分配容量；When the allocatable capacity is greater than or equal to the sum of the capacity increments, the allocated capacity of the corresponding cache partition is increased according to the capacity increment of the cache partition to be increased, and the allocated capacity of the corresponding cache partition is decreased according to the capacity reduction of the cache partition to be reduced, and the allocated capacity of the cache partition corresponding to the preset device ID is updated; 当所述可分配容量小于所述容量增量之和时，根据需减容的缓存分区的容量减量对对应缓存分区的分配容量进行减小设置，需增容的缓存分区的分配容量保持不变，并更新所述预设设备ID对应的缓存分区的分配容量。When the allocatable capacity is less than the sum of the capacity increments, the allocated capacity of the corresponding cache partition is reduced according to the capacity reduction of the cache partition that needs to be reduced, the allocated capacity of the cache partition that needs to be increased remains unchanged, and the allocated capacity of the cache partition corresponding to the preset device ID is updated. 4.根据权利要求3所述的Cache资源配置装置，其特征在于，任一缓存分区在每个周期的容量增量和容量减量均为ΔP；其中，ΔP为预设的整数值，表示增加或减少的Cacheline数目，所述缓存分区的分配容量表示缓存分区包含的Cacheline数目。4. The cache resource configuration device according to claim 3 is characterized in that the capacity increase and capacity decrease of any cache partition in each cycle are both ΔP; wherein ΔP is a preset integer value, representing the number of cachelines increased or decreased, and the allocated capacity of the cache partition represents the number of cachelines contained in the cache partition. 5.一种内存访问控制装置，其特征在于，包括地址翻译单元、全相联Cache以及根据权利要求1～4中任一项所述的Cache资源配置装置；5. A memory access control device, characterized by comprising an address translation unit, a fully associative cache and a cache resource configuration device according to any one of claims 1 to 4; 所述全相联Cache包括Cache控制器和Cache存储器；The fully associative Cache includes a Cache controller and a Cache memory; 所述Cache控制器，用于根据所述虚拟地址数据确定所述全相联Cache中与所述虚拟地址数据对应的物理地址数据，若是，则从对应的组的Cacheline中取出命中的物理地址数据并发送至内存控制器以访问内存，若否，则输出未命中结果给所述地址翻译单元；The cache controller is used to determine the physical address data corresponding to the virtual address data in the fully associative cache according to the virtual address data, and if yes, take out the hit physical address data from the cacheline of the corresponding group and send it to the memory controller to access the memory, and if no, output a miss result to the address translation unit; 所述地址翻译单元，用于根据所述未命中结果，根据所述访问请求获取虚拟地址数据，将所述虚拟地址数据翻译为物理地址数据，将当前翻译的物理地址数据发送至所述内存控制器以访问内存，并将当前翻译的物理地址数据发送至所述Cache控制器；The address translation unit is used to obtain virtual address data according to the access request based on the miss result, translate the virtual address data into physical address data, send the currently translated physical address data to the memory controller to access the memory, and send the currently translated physical address data to the cache controller; 所述Cache控制器，进一步用于将所述当前翻译的物理地址数据存储至所述对应的组的一条Cacheline中或丢弃。The cache controller is further configured to store the currently translated physical address data in a cacheline of the corresponding group or discard it. 6.根据权利要求5所述的内存访问控制装置，其特征在于，所述内存访问控制装置还包括调度控制模块；6. The memory access control device according to claim 5, characterized in that the memory access control device further comprises a scheduling control module; 所述Cache控制器，进一步用于获取所述访问请求对应的设备ID以及对应缓存分区中的各条Cacheline对应的设备ID，进一步获取所述访问请求对应的设备ID对应的优先级以及所述各条Cacheline对应的设备ID对应的优先级，并输出至所述调度控制模块；其中，所述Cacheline对应的设备ID为Cacheline的存储数据对应的设备ID；The cache controller is further used to obtain the device ID corresponding to the access request and the device ID corresponding to each cacheline in the corresponding cache partition, further obtain the priority corresponding to the device ID corresponding to the access request and the priority corresponding to the device ID corresponding to each cacheline, and output them to the scheduling control module; wherein the device ID corresponding to the cacheline is the device ID corresponding to the storage data of the cacheline; 所述调度控制模块，用于根据所述访问请求对应的设备ID对应的优先级以及所述各条Cacheline对应的设备ID对应的优先级，确定是否将所述当前翻译的物理地址数据存储至所述对应的组的一条Cacheline中，并将确定结果返回给所述Cache控制器；The scheduling control module is used to determine whether to store the currently translated physical address data in a cacheline of the corresponding group according to the priority corresponding to the device ID corresponding to the access request and the priority corresponding to the device ID corresponding to each cacheline, and return the determination result to the cache controller; 所述Cache控制器，进一步用于根据所述确定结果将当前翻译的物理地址数据存储至所述对应的组的一条Cacheline中或丢弃。The cache controller is further configured to store the currently translated physical address data in a cacheline of the corresponding group or discard it according to the determination result. 7.根据权利要求6所述的内存访问控制装置，其特征在于，所述调度控制模块，进一步用于确定对应缓存分区中是否存在至少一个空闲的Cacheline，若是，则将所述当前翻译的物理地址数据存储至任一空闲的Cacheline中；若否，则当所述访问请求对应的设备ID对应的优先级低于对应缓存分区中的任一条Cacheline对应的设备ID对应的优先级时，确定将所述当前翻译的物理地址数据丢弃。7. The memory access control device according to claim 6 is characterized in that the scheduling control module is further used to determine whether there is at least one free cacheline in the corresponding cache partition. If so, the currently translated physical address data is stored in any free cacheline; if not, when the priority corresponding to the device ID corresponding to the access request is lower than the priority corresponding to the device ID corresponding to any cacheline in the corresponding cache partition, it is determined to discard the currently translated physical address data. 8.根据权利要求6所述的内存访问控制装置，其特征在于，所述调度控制模块，进一步用于当所述访问请求对应的设备ID对应的优先级高于或等于对应缓存分区中的至少一条Cacheline对应的设备ID对应的优先级时，从该至少一条Cacheline中选择优先级最低的至少一条Cacheline，并从所述优先级最低的至少一条Cacheline中选择在最近预设时间内的使用次数最少的一条Cacheline，用于存储所述当前翻译的物理地址数据。8. The memory access control device according to claim 6 is characterized in that the scheduling control module is further used to select at least one cacheline with the lowest priority from the at least one cacheline when the priority corresponding to the device ID corresponding to the access request is higher than or equal to the priority corresponding to the device ID corresponding to at least one cacheline in the corresponding cache partition, and select a cacheline with the least number of uses within a recent preset time from the at least one cacheline with the lowest priority to store the currently translated physical address data. 9.根据权利要求8所述的内存访问控制装置，其特征在于，所述Cache存储器还包括优先级数据模块和LRU模块，所述优先级数据模块用于存储各个设备ID对应的优先级信息，所述LRU模块用于存储各条Cacheline在最近预设时间内的使用次数。9. The memory access control device according to claim 8 is characterized in that the cache memory also includes a priority data module and an LRU module, the priority data module is used to store the priority information corresponding to each device ID, and the LRU module is used to store the number of times each cacheline is used within a recent preset time. 10.根据权利要求6～9中任一项所述的内存访问控制装置，其特征在于，所述调度控制模块，进一步用于根据各个设备ID对应的存储分区的分配容量和实际使用容量，以及所述未分配容量确定各个设备ID对应的优先级。10. The memory access control device according to any one of claims 6 to 9 is characterized in that the scheduling control module is further used to determine the priority corresponding to each device ID based on the allocated capacity and actual used capacity of the storage partition corresponding to each device ID, and the unallocated capacity. 11.一种芯片，包括根据权利要求1～4中任一项所述的Cache资源配置装置，或者，包括根据权利要求5～10中任一项所述的内存访问控制装置。11. A chip, comprising the cache resource configuration device according to any one of claims 1 to 4, or comprising the memory access control device according to any one of claims 5 to 10.
CN202411303165.6A 2024-09-19 2024-09-19 Cache resource allocation device, memory access control device and chip Pending CN119149450A (en)

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