CN119148122A

CN119148122A - FPGA-based rapid radar tracking signal detection and data communication device

Info

Publication number: CN119148122A
Application number: CN202411206865.3A
Authority: CN
Inventors: 管雪元; 王彦懿
Original assignee: Nanjing University of Science and Technology
Current assignee: Nanjing University of Science and Technology
Priority date: 2024-08-30
Filing date: 2024-08-30
Publication date: 2024-12-17

Abstract

The invention discloses a fast radar tracking signal detection and data communication device based on FPGA, optimizes the flow of FPGA related calculation algorithm, aims to solve the problems of low efficiency and high delay of the traditional related detection method, adopts a modularized pipeline structure by using a sending end and a receiving end based on FPGA, the signal LFM-MSK signal modulation is carried out at the transmitting end, the synchronization and demodulation of the LFM-MSK signal are carried out at the receiving end, the parallel computing algorithm structure is adopted at the radar tracking signal detection part, the computing speed is improved by a plurality of times compared with the traditional correlation detection method, and the time required by signal synchronization is greatly reduced while the computing precision is not influenced. The method can be widely applied to the technical field of radar communication, and provides high-efficiency performance support for a radar communication system.

Description

FPGA-based rapid radar tracking signal detection and data communication device

Technical Field

The invention relates to the technical field of wireless communication, in particular to a rapid radar tracking signal detection and data communication device based on an FPGA.

Background

In radar applications, accurately detecting and acquiring the arrival time of a received signal in real time is a critical issue. The radar can only completely receive the received signal without losing useful information if the arrival time of the received signal is correctly detected. For various radar systems, especially for high-precision and high-real-time application scenarios, such as military radar, air control radar, weather radar, etc., efficient radar signal detection algorithms are particularly important.

The existing radar signal detection method mainly comprises a frequency domain detection method and a time domain detection method. The frequency domain detection method relates to Fourier transform and inverse Fourier transform, is large in calculated amount and remarkable in time delay, consumes a large amount of hardware resources, is unfavorable for the realization of a hardware FPGA, and is not suitable for real-time signal detection.

In contrast, the time domain detection method utilizes the frequency characteristic of the radar signal to locally generate the same reference signal as the radar signal, and the energy of the pulse signal is continuously accumulated through the correlation accumulation of the two signals in the time domain, and finally a peak value appears, so that the arrival time and the end time of the signal are determined. The method has lower calculation complexity and lower hardware resource consumption, and is more suitable for radar systems with high real-time requirements.

Correlation detection is an important technique in time domain detection methods for detecting a target signal by calculating correlation between a received signal and a known reference signal. The basic principle is that the arrival time of the received signal is judged by calculating the correlation function of the known reference signal and the received signal by utilizing the similarity between the known reference signal and the received signal. The method comprises the following specific steps:

filtering and denoising the received signal to reduce the influence of noise and interference;

performing correlation operation on the received signal and a known reference signal to obtain a correlation function, wherein the correlation function reflects the similarity of the signals under different time delays;

searching a peak value in the correlation function, wherein the position and the height of the peak value respectively reflect the arrival time and the intensity of the signal;

and judging whether a target signal exists or not according to the analysis result of the correlation function. If there is a significant peak in the correlation function, indicating that there is a received signal similar to the reference signal at that delay, it may correspond to the target echo signal.

Although the correlation detection method has obvious advantages in the hardware field compared with the frequency domain detection method and is widely applied to practical application, the traditional correlation detection method still has lower calculation efficiency and higher time delay. In order to solve the problems, the real-time performance and accuracy of radar signal detection are improved, and a rapid synchronous detection algorithm is provided. The algorithm realizes more efficient signal detection and synchronization by optimizing the related calculation and signal processing flow, can obviously improve the real-time performance and accuracy of radar signal detection, and provides guarantee for efficient operation of a radar system.

Disclosure of Invention

The invention aims to provide a rapid radar tracking signal detection and data communication device based on an FPGA.

The communication system based on the FPGA for the linear frequency modulation rapid synchronization method comprises an LFM-MSK signal generating end based on the FPGA, an LFM-MSK signal receiving end based on the FPGA and an LFM-MSK signal receiving end based on the FPGA, wherein the LFM-MSK signal generating end is used for simulating radar signal output, and the LFM-MSK signal receiving end is used for verifying synchronous demodulation effect of radar signals;

the LFM-MSK signal generating end based on the FPGA comprises a code element generating module, an LFM-MSK signal modulating module and a radio frequency module, wherein the code element generating module is used for carrying out binary code modulation on an information source, the code modulation comprises differential coding and serial-parallel conversion;

the LFM-MSK signal receiving end based on the FPGA comprises a radio frequency receiving module, a radar signal detecting module based on the FPGA, a coherent demodulation module and a differential decoding module, wherein the radio frequency receiving module is used for converting a radio signal into a digital signal, the radar signal detecting module based on the FPGA obtains carrier synchronization information, the coherent demodulation module is responsible for carrying out carrier synchronization and MSK demodulation processes, a coherent square ring demodulation method is adopted to demodulate the digital signal containing a carrier into a binary signal with one bit width, and the differential decoding module is used for decoding the binary signal to obtain final source code information.

Compared with the prior art, the invention has the remarkable advantages that:

(1) In the radar signal detection part, a parallel computing algorithm structure is adopted, the computing speed is improved by a plurality of times compared with that of the traditional correlation detection method, and the time required by signal synchronization is greatly reduced while the computing precision is not influenced;

(2) The parallel parameters can be adjusted, the running speed can be increased by increasing the number of parallel structures according to actual demands, or the power consumption can be reduced by reducing the number of parallel structures, the degree of freedom is extremely high, and the internal resources of the FPGA can be fully utilized;

(3) The method can be widely applied to the technical field of radar communication, and provides high-efficiency performance support for a radar communication system.

Drawings

Fig. 1 is an overall configuration diagram of a communication system.

Fig. 2 is a diagram of a conversion relationship between a source code signal and two orthogonal signals.

Fig. 3 is a schematic diagram of LFM-MSK signal generation.

Fig. 4 is a diagram of the result of an FPGA implementation of the digital information modulation process.

Fig. 5 is a final signal diagram of the I and Q paths.

Fig. 6 is a block diagram of a radar signal detection module.

Fig. 7 shows simulation test results of the radar signal detection module.

Detailed Description

At present, although the correlation detection method is applied to an actual radar system and has obvious advantages in the hardware field compared with the frequency domain detection method, the calculation efficiency of the existing correlation detection method is still lower, and the time delay is higher. In order to solve the problems, the real-time performance and accuracy of radar signal detection are improved, and a rapid synchronous detection algorithm is provided. The algorithm optimizes the related calculation and the signal processing flow by exerting the parallel processing characteristic of the FPGA, optimizes the linear calculation into the 'face' calculation, more efficiently realizes the signal detection and synchronization, can remarkably improve the real-time performance and accuracy of the radar signal detection, aims to solve the problems of low efficiency and serious delay of the traditional related detection method, and provides guarantee for the efficient operation of a radar system.

The invention optimizes the FPGA related calculation algorithm flow, designs a rapid radar signal detection and data communication device based on the FPGA, and aims to solve the problems of low efficiency and serious delay of the traditional related detection method.

The communication device is shown in fig. 1, and comprises a Linear Frequency Modulation (LFM) -minimum frequency shift keying (MSK) signal generating end based on an FPGA, which is used for simulating radar signal output, and an LFM-MSK signal receiving end based on the FPGA, which is used for verifying synchronous demodulation effect of radar signals.

The LFM-MSK signal generating end based on the FPGA comprises a code element generating module based on the FPGA, an LFM-MSK signal modulating module and a radio frequency transmitting module.

The FPGA code element generating module is used for carrying out differential coding on data to be transmitted in a 2-system mode through a specific rule and carrying out serial-parallel conversion;

The differential coding aims to solve the problem of phase ambiguity generated when a signal receiving end carries out carrier recovery on a modulated signal.

Further, the differential encoding expression is:

Wherein a _k is the kth bit of the data source code, and b _k is the data of a _k after differential coding.

The serial-to-parallel conversion divides the output signal after differential encoding into I, Q two paths by using a serial-to-parallel converter, and interleaves one symbol width T _b, and fig. 2 illustrates the rules of differential encoding and serial-to-parallel conversion.

The LFM-MSK signal modulation module processes the signal output by the symbol modulation module into a digital signal with minimum frequency shift, continuous phase, linear change of carrier frequency and carrying information, and fig. 3 shows a schematic diagram of LFM-MSK signal generation process.

The LFM-MSK signal modulation module firstly carries out weighting treatment on two paths of data after differential coding by using a weighting function generated by DDS respectively;

The weighting functions are expressed as:

Where T is time and T _b is symbol period;

only half-period carrier signals are in the period of each symbol, when the transmission data is 0, the phase of the signals is 180 degrees deflected, and when the transmission data is 1, the phase of the signals is unchanged. This transformation of the carrier phase carries the digital signal. Fig. 4 shows the FPGA implementation result of the digital information modulation process, where msk_i is the result of modulating the I branch, and msk_q is the result of modulating the Q branch.

The two weighted signals are modulated and superimposed using chirped quadrature carrier signals cos (ω _ct+πμt²) and sin (ω _ct+πμt²), respectively.

Where ω _c is the initial carrier frequency, μ is the chirp coefficient, expressed as the frequency rate of the chirp signal.

The modulated signal is the LFM-MSK signal carrying symbol information, and the expression S _LFM-MSK is:

Wherein I _k,Q_k ε { + -1 } and carry symbol information.

The resulting signal multiplied by the carrier signal is shown in fig. 5, where msk_lfm_i is the I-branch modulated resulting signal and msk_lfm_q is the Q-branch modulated resulting signal.

The filter module, DAC module and antenna module of the radio frequency transmitting module belong to hardware circuit part and are responsible for converting digital signals into radio form.

The LFM-MSK signal receiving end based on the FPGA comprises a radio frequency receiving module, a radar signal detecting module based on the FPGA, a coherent demodulation module and a differential decoding module;

the antenna module, the ADC module and the filter module of the radio frequency receiving module belong to hardware circuit parts and are responsible for converting radio signals into digital signals.

Through the antenna module, a radio signal in space can be received and sent to the ADC module in the form of an analog signal;

and the ADC module converts the analog signal into a digital signal, and the digital signal is subjected to extraction and filtering by the filter module and is sent to the FPGA for signal processing.

The radar signal detection module based on the FPGA adopts a correlation detection method, the basic principle of the correlation detection method is to detect a target signal by using the similarity between a known reference signal and a received signal, an algorithm is calculated based on a correlation function between signals, and the correlation function reflects the similarity degree of the signals under different time delays.

For a radar system, the correlation function between the local reference signal s (t) and the received signal r (t) is defined as:

Since the signals received by the FPGA are clock-based, discrete, finite-length digital signals, in the digital circuitry, the continuous signals s (t) and r (t) are replaced by discrete signals x (N) and y (N), respectively, of length N, the above equation becomes

The radar signal detection module is based on the algorithm, the structure is shown in fig. 6, and the operation in the FPGA uses the following steps:

Before the program runs, generating a linear frequency modulation reference signal y (n) with the same carrier frequency and linear frequency modulation coefficient as those of a transmitting end by using matlab, and storing the linear frequency modulation reference signal y (n) into an FPGA (field programmable gate array) internal rom;

The program STARTs running and the system initializes with a WAIT-to-START delay (start_wait) to ensure that all components are ready to run. After the initialization phase is completed, the input signal (din) is continuously sampled and stored in the FPGA internal RAM. After a complete pulse is stored, the signal input lock flag bit (din_lock) is pulled high, and the input signal is not stored any more in the running period, so that new data is prevented from entering the processing pipeline. This ensures that the data being processed is consistent and will not be altered during the computation process;

After the signal input lock flag (din_lock) register becomes high level and the input signal is not updated any more, the reference signal is read from ROM, the received signal information is read from RAM, and the received signal information is stored in the input signal memory buffer array (rec_dat) and the reference signal memory buffer array (ref_dat) respectively, wherein the depth of the array register is equal to the depth of the reference signal. The input signal and the reference signal data used by each group of correlation calculation are respectively preloaded into another array register, and the depth of the array register is equal to the number of the reference signals;

When the correlation calculation is carried out, the two groups of registers, from which the input signal (rac_dat) and the reference signal (ref_dat) are read, are firstly equidistantly divided into a plurality of groups, the data of different groups are calculated in parallel, in the same group, the multiplication result of the input signal (rac_dat) and the data of the same address of the reference signal (ref_dat) are multiplied, the multiplication result of the multiplication result is added with the multiplication result of the next period, the calculation is carried out sequentially every clock period until the multiplication and addition of the data of each group in each group are finished, and the obtained result is added to the result array register (sum_phase);

After the multiplication and addition calculation is completed, the sum of each bit of the result part of each stage, namely the result array register (sum_phase), is further accumulated, and the obtained final result is a group of relevant calculation results of input data and reference signals;

When a group of correlation calculation processes are completed, adding one bit to the read address of the input signal register (ram), putting the read new data into the input signal array register, and then calculating the correlation value of the new group of data until the whole reference data set is processed;

Simultaneously with the previous group of steps, when a group of correlation calculation processes are completed, the correlation values are output to a peak detection module, the peak detection module is responsible for judging the input correlation values, reserving the maximum value, and when the correlation calculation of all input signals is completed, outputting the address information of the peak value so as to obtain accurate signal arrival time and ending time;

The system also includes a intra-module reset mechanism (rst_internal) to ensure that all components are restored to the original state at the end of the computation except for the peak detection result. Triggering the reset once all the stored external pulse signals are processed, so that the system can detect radar signals of the next group of pulses without external reset signals;

The radar signal detection module can accurately obtain carrier synchronization information, a simulation test result is shown in fig. 7, the carrier frequency of the signal generation end starts to be linearly modulated at 8000 th position, a sum_final signal in the figure obtains a correlation calculation maximum value at 8000 th position, and the calculation result is obviously higher than other positions, so that the characteristic of strong anti-interference performance of the algorithm is also proved. And carrying out a carrier removal synchronization process, namely a coherent demodulation process, on the basis of the calculation result.

The coherent demodulation module carries out carrier removal synchronization and MSK demodulation processes on the LFM-MSK digital signals received by the ADC based on the obtained carrier synchronization information, and the coherent square ring demodulation method is designed to be adopted to demodulate the digital signals containing the carriers into binary signals with the bit width of one.

And decoding the demodulated signal by a differential decoding module to obtain source code information. The expression of differential decoding is: Wherein a _k is the kth bit after differential encoding and decoding, and b _k is the differential encoded data obtained after demodulation.

Claims

1. A fast radar tracking signal detection and data communication device based on FPGA, characterized in that it includes an LFM-MSK signal generating end based on FPGA for simulating radar signal output, and an LFM-MSK signal receiving end based on FPGA for verifying the synchronous demodulation effect of the radar signal;

The FPGA-based LFM-MSK signal generating end includes a symbol generation module, an LFM-MSK signal modulation module and a radio frequency transmission module; the symbol generation module is used to perform binary coding modulation on the information source, and the coding modulation includes differential coding and serial-to-parallel conversion; the LFM-MSK signal modulation module is used to process the signal output by the symbol modulation module into a digital signal with minimum frequency shift, continuous phase, linear carrier frequency change and information carrying; the radio frequency transmission module includes a filter module, a DAC module, and an antenna module, which is responsible for converting the digital signal into a radio form;

The FPGA-based LFM-MSK signal receiving end includes a wireless signal receiving end including a radio frequency receiving module, a radar signal detection module based on FPGA, a coherent demodulation module, and a differential decoding module; the radio frequency receiving module is used to convert the radio signal into a digital signal; the FPGA-based radar signal detection module obtains the carrier synchronization information; the coherent demodulation module is responsible for performing the de-carrier synchronization and MSK demodulation process, and adopts the coherent square ring demodulation method to demodulate the digital signal containing the carrier into a binary signal with a bit width of one; the binary signal is decoded by the differential decoding module to obtain the final source code information.

2. The FPGA-based fast radar tracking signal detection and data communication device according to claim 1 is characterized in that the code element generation module inside the FPGA performs differential encoding of the data to be transmitted in binary according to specific rules and performs serial-to-parallel conversion;

The differential encoding expression is: Where a _k is the kth bit of the data source code, and b _k is the data after differential encoding;

The serial-to-parallel conversion is to use a serial/parallel converter to divide the output signal after differential encoding into two paths, and to interleave them with one symbol width T _b .

3. The FPGA-based fast radar tracking signal detection and data communication device according to claim 1 is characterized in that the LFM-MSK signal modulation module first uses a weighting function to perform weighted processing on the two paths of data after differential encoding; the weighting functions are respectively expressed as: Where, t is time, T _b is the symbol period;

The two weighted signals are respectively orthogonally modulated and superimposed using linear frequency modulation orthogonal carrier signals; the linear frequency modulation orthogonal carrier signals are respectively expressed as: cos(ω _c t+πμt ² ), sin(ω _c t+πμt ² ), wherein ω _c is the initial carrier frequency, μ is the linear frequency modulation coefficient, and is expressed as the frequency change rate of the linear frequency modulation signal;

The modulated signal is the LFM-MSK signal carrying the code element information, and its expression S _LFM-MSK is:

Among them, I _k , Q _k ∈{±1} and carry code element information.

4. The FPGA-based fast radar tracking signal detection and data communication device according to claim 1, characterized in that the radio frequency receiving module includes an antenna module, an ADC module, and a filter module, which is responsible for converting the radio signal into a digital signal;

The antenna module receives the radio signal in space and sends it to the ADC module in the form of an analog signal. The ADC module converts the analog signal into a digital signal, which is extracted and filtered by the filter module and sent to the FPGA for signal processing.

5. The FPGA-based fast radar tracking signal detection and data communication device according to claim 1 is characterized in that the radar signal detection module adopts a correlation detection method, and the calculation inside the FPGA includes the following steps:

Before the program is run, a linear frequency modulation reference signal y(n) having the same carrier frequency and linear frequency modulation coefficient as the transmitting end is generated and stored in the FPGA;

When the program starts running, the system initializes by waiting for the startup delay to ensure that all components are ready to run; after the initialization phase is over, the input signal is continuously sampled and stored in the memory buffer; after ensuring that a complete pulse is stored, the signal input lock flag is pulled high, and the input signal is no longer saved during the operation cycle;

Calculate the correlation value of the stored input signal and the reference signal; each group of input signal and reference signal data used in the correlation calculation is pre-loaded into another array register respectively, the depth of the array register is equal to the number of reference signals, when performing the correlation calculation, the two array registers that read the input signal and the reference signal are first divided into several groups at equal intervals, and the data of different groups are calculated in parallel. In the same group, the data of the same address of the input signal and the reference signal are multiplied, and the multiplication result is added to the multiplication result of the next cycle. The calculation is performed in turn in each clock cycle until the data in each group and each group are multiplied and added, and the result is assigned to the result array register;

After the multiplication and addition calculations are completed, the result part of each stage, that is, the sum of each bit of the result array register, is further accumulated, and the final result obtained is a set of related calculation results of the input data and the reference signal;

When a set of correlation calculation processes is completed, the read address of the input signal register is increased by one bit, the read new data is placed in the input signal array register, and then the correlation value of the new set of data is calculated until the entire reference data set is processed;

At the same time as the previous set of steps, when a set of correlation calculation processes is completed, the correlation value will be output to the peak detection module. The peak detection module is responsible for judging the input correlation value and retaining the maximum value. When the correlation calculations of all input signals are completed, the address information of the peak value is output to obtain the accurate signal arrival time and end time;

The system also includes an internal reset mechanism to ensure that all components except the peak detection results are restored to their initial state at the end of the calculation; once all stored external pulse signals have been processed, this reset is triggered to ensure that the system can perform radar signal detection on the next set of pulses without the need for an external reset signal.

6. The FPGA-based fast radar tracking signal detection and data communication device according to claim 1 is characterized in that the coherent demodulation module, based on the obtained carrier synchronization information, performs carrier synchronization and MSK demodulation processes on the LFM-MSK digital signal received by the ADC, and is designed to adopt a coherent square ring demodulation method to demodulate the digital signal containing the carrier into a binary signal with a bit width of one.

7. The FPGA-based fast radar tracking signal detection and data communication device according to claim 1 or 6, characterized in that the demodulated signal is decoded by a differential decoding module to obtain source code information; the expression of differential decoding is: Among them, a _k is the kth bit after differential coding decoding, and b _k is the differential coding data obtained after LFM-MSK demodulation.