CN119127094A - Data access method, heterogeneous system, electronic device, medium and program product - Google Patents
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Abstract
本发明提供一种数据访问方法、异构系统、电子设备、介质和程序产品，应用于异构系统数据访问技术领域，其中访问发起方登录访问响应方在本地操作系统上创建的虚拟串口设备；虚拟串口设备为访问响应方通过本地虚拟串口驱动创建的设备，虚拟串口驱动基于预设可编程逻辑器件中数据缓存器的目标访问通道的通道数量创建；向访问响应方的本地操作系统发起访问请求，以便访问响应方从本地获取与访问请求对应的目标响应数据，并通过目标访问通道将目标响应数据写入数据缓存器；通过目标访问通道从数据缓存器中获取目标响应数据，以完成相应的数据访问操作。由此可见，本发明满足访问发起方直接通过内部通道访问访问响应方的需求，并扩大应用场景。
The present invention provides a data access method, a heterogeneous system, an electronic device, a medium and a program product, which are applied to the field of heterogeneous system data access technology, wherein an access initiator logs in to a virtual serial port device created by an access responder on a local operating system; the virtual serial port device is a device created by the access responder through a local virtual serial port driver, and the virtual serial port driver is created based on the number of channels of a target access channel of a data buffer in a preset programmable logic device; an access request is initiated to the local operating system of the access responder, so that the access responder obtains the target response data corresponding to the access request from the local, and writes the target response data to the data buffer through the target access channel; the target response data is obtained from the data buffer through the target access channel to complete the corresponding data access operation. It can be seen that the present invention meets the needs of the access initiator to directly access the access responder through an internal channel, and expands the application scenario.
Description
Technical Field
The present invention relates to the field of heterogeneous system data access technologies, and in particular, to a data access method, a heterogeneous system, an electronic device, a medium, and a program product.
Background
Along with the advancement of the digital process in China, the demand for computing power is increased, the data center is gradually evolved into a computing center, and the computing power becomes new productivity. However, in the face of progressive failure of moore's law, relying on a central processor alone has not been able to meet the enormous computational power demands of a computing center. Under the background, heterogeneous computing has been rapidly developed, and various heterogeneous systems generated by fusing a plurality of types of acceleration hardware such as a central processing unit, an image processor, a system on chip, a field programmable gate array and the like have a great pushing effect on the computing power improvement of a data center.
The heterogeneous system taking the field programmable gate array as a core has the advantages in the aspects of network communication, algorithm acceleration and the like by the characteristics of high bandwidth, low delay, parallel processing, reconfigurability and the like, but is inferior to a system on a chip in the aspects of generality and complex logic operation. Therefore, such systems are often a combination of a field programmable gate array and a system on a chip, in which an embedded operating system is run in the system on a chip, so as to implement functions such as algorithm updating, running state monitoring of the field programmable gate array, and partial task unloading. However, in the heterogeneous system of the current field programmable gate array+system on chip, the host and the system on chip have no direct data path, and if the host is required to access the operating system on the system on chip, the host needs to access the gigabit port through a network or access the heterogeneous system by using a universal serial bus to serial port mode, so that the hardware cost of the heterogeneous system is increased. And because the host computer and the system on a chip in the heterogeneous system have no direct connection data path, the application of many scenes is limited. Meanwhile, under the structure, the internal part of the field programmable gate array is connected with the system on the chip through the network, so that more resources in the field programmable gate array can be occupied as a whole.
It can be seen how to construct a direct data path between a host and a system on a chip is a problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The embodiment of the invention aims to provide a data access method, a heterogeneous system, electronic equipment, a medium and a program product, which can solve the problems of increasing the hardware cost of the heterogeneous system, occupying a large amount of field programmable gate array resources and having smaller application scenes of the current system caused by the fact that a host and the system on a chip are not provided with a direct connection data path in the prior art.
In order to solve the above technical problems, in one aspect, an embodiment of the present invention provides a data access method, applied to an access initiator, including:
The virtual serial device is a device created by the access response party through a local virtual serial driver, and the virtual serial driver is created based on the channel number of a target access channel of a data buffer in a preset programmable logic device;
Initiating an access request to a local operating system of an access response party so that the access response party obtains target response data corresponding to the access request from the local and writes the target response data into a data buffer through a target access channel;
and acquiring target response data from the data buffer through the target access channel so as to finish corresponding data access operation.
In some embodiments, before logging in the virtual serial device created on the local operating system, the access responder further comprises:
determining the number of channels of a target access channel from a data buffer based on user requirements, wherein the target access channel is a channel used by an access initiator for accessing an access responder;
the number of channels is configured to the access responder such that the access responder creates a virtual serial port driver based on the number of channels.
In some embodiments, configuring the number of channels to the access responder such that the access responder creates a virtual serial port driver based on the number of channels comprises:
the number of channels is configured to the access responder by dual access random access memory in the programmable logic device such that the access responder creates a virtual serial port driver based on the number of channels.
In some embodiments, the access responder creates a virtual serial port driver based on the number of channels, comprising:
based on the embedded driving architecture and the number of channels of the target access channel, creating a virtual serial port driver in a software implementation mode.
In some embodiments, the process of accessing a virtual serial device created by a responder includes:
loading the virtual serial port drive to the local according to the number of channels configured by the access initiator;
creating virtual serial equipment on a local operating system by using a locally loaded virtual serial driver;
wherein the number of virtual serial devices is one or more.
In some embodiments, before the access responder loads the virtual serial port driver locally, further comprising:
executing a local first initialization operation, registering a corresponding operating system console after the first initialization operation is finished, and configuring a corresponding console environment;
Correspondingly, after creating the virtual serial device on the local operating system by using the locally loaded virtual serial driver, the method further comprises:
adding a virtual serial device to the operating system console.
In some embodiments, the first initialization operation includes enabling a local serial reception interrupt and configuring a local serial reception processing function.
In some embodiments, further comprising:
performing a second initialization operation after loading the virtual serial port driver locally and before adding the virtual serial port device to the operating system console;
the second initialization operation is to configure the hardware serial port address information between the second initialization operation and the preset programmable logic device.
In some embodiments, loading virtual serial drivers locally according to the number of channels configured by the access initiator includes:
Judging whether the number of channels configured by the access initiator is a non-zero value or not;
And if the number of the channels configured by the access initiator is a non-zero value, loading the virtual serial port drive to the local, otherwise, prohibiting loading the virtual serial port drive to the local.
In some embodiments, if the preset programmable logic device includes at least two data buffers, the method further includes:
judging whether read-write clocks among all the data buffers are consistent;
If the read-write clocks among the data buffers are inconsistent, the read-write clocks among the data buffers are adjusted to be consistent in a preset synchronous mode.
In some embodiments, the predetermined synchronization pattern includes a pattern by delaying a clock cycle or a pattern by gray code conversion.
In some embodiments, the data buffer is a buffer implemented based on an internal register of the preset programmable logic device, and the data buffer adopts a first-in first-out data read-write strategy.
In some embodiments, writing the target response data to the data buffer through the target access channel includes:
monitoring whether a full writing signal sent by a data buffer is received or not;
if the full writing signal sent by the data buffer is not monitored, the target response data is written into the data buffer through the target access channel, otherwise, the target response data is forbidden to be written into the data buffer.
In some embodiments, the process of creating the virtual serial device by the access responder further comprises:
configuring corresponding device indexes for each created virtual serial device, and establishing corresponding relations between different virtual serial devices and different target access channels;
correspondingly, writing the target response data into the data buffer through the target access channel comprises the following steps:
determining a target device index corresponding to the virtual serial device logged in by the current access initiator;
and writing the target response data into the data buffer by utilizing the target access channel corresponding to the target equipment index in each target access channel.
In some embodiments, further comprising:
Reading target response data in a data buffer by using a target access channel through a preset data receiving tool, and forwarding the read target response data to target virtual serial equipment; the target virtual serial device is a virtual serial device corresponding to a target access channel for transmitting target response data, which is determined from the virtual serial devices;
Correspondingly, the target response data is obtained from the data buffer through the target access channel, which comprises the following steps:
and acquiring target response data read by a preset data receiving tool through a corresponding target access channel from target virtual serial equipment.
In some embodiments, reading, by the preset data receiving tool, the target response data in the data buffer using the target access channel includes:
monitoring whether a non-air break signal sent by a data buffer is received or not;
if the non-air break signal sent by the data buffer is monitored, the target response data in the data buffer is read by using the target access channel through the preset data receiving tool, otherwise, the data is forbidden to be read from the data buffer.
In some embodiments, the access initiator is a host and the access responder is a system-on-chip, or the access initiator is a system-on-chip and the access responder is a host.
In another aspect, the present invention provides a data access method, applied to an access responder, including:
The virtual serial device is a device which is created in advance on a local operating system through a local virtual serial driver by an access response party, and the virtual serial driver is created based on the number of channels of a target access channel of a data buffer in a preset programmable logic device;
And obtaining target response data corresponding to the access request from the local, and writing the target response data into the data buffer through the target access channel so that the access initiator obtains the target response data from the data buffer through the target access channel.
On the other hand, the invention also provides a heterogeneous system which comprises an access initiator, an access responder and a preset programmable logic device, wherein,
The method comprises the steps that a programmable logic device is preset and used for constructing a target access channel between an access initiator and an access responder through a data buffer of the programmable logic device;
The access initiator is used for logging in the virtual serial device created by the access responder on the local operating system, initiating an access request to the local operating system of the access responder, and acquiring target response data corresponding to the access request from the data buffer through a target access channel;
the access response party is used for locally acquiring target response data corresponding to the access request, and writing the target response data into the data buffer through the target access channel;
the access initiator is a host and the access responder is a system on chip, or the access initiator is a system on chip and the access responder is a host.
In another aspect, the present invention also provides an electronic device, including:
A memory for storing a computer program;
And a processor for executing the computer program to implement the steps of the data access method described above.
On the other hand, the invention also provides a nonvolatile storage medium, wherein the nonvolatile storage medium stores a computer program, and the computer program realizes the steps of the data access method when being executed by a processor.
In another aspect, the invention also provides a computer program product comprising computer programs/instructions which when executed by a processor implement the steps of the data access method described above.
The technical scheme shows that the data access method is applied to an access initiator and comprises the steps of logging in virtual serial equipment created on a local operating system by an access responder, creating equipment for the access responder through a local virtual serial driver, creating the virtual serial driver based on the channel number of target access channels of a data buffer in a preset programmable logic device, initiating an access request to the local operating system of the access responder so that the access responder can obtain target response data corresponding to the access request locally, writing the target response data into the data buffer through the target access channel, and obtaining the target response data from the data buffer through the target access channel to complete corresponding data access operation. Therefore, the invention logs in the virtual serial device created by the access response party on the local operating system, which is equivalent to constructing a direct communication path between the access initiator and the access response party, can meet the requirement that the access initiator directly accesses the access response party through an internal channel, and can realize the common firmware update, algorithm upgrading and state monitoring requirements of the access initiator on the access response party in the access mode. In addition, the virtual serial port driver is created based on the number of channels, so that the invention can achieve the aim of multi-user access without increasing resources, and further expands the application scene of the data access method provided by the invention.
Drawings
For a clearer description of embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described, it being apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
FIG. 1 is a flow chart of a data access method according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a first configuration of a prior art heterogeneous system;
FIG. 3 is a second schematic diagram of a prior art heterogeneous system;
FIG. 4 is a frame diagram of a virtual serial port driver according to an embodiment of the present invention;
fig. 5 is a flow chart for creating a virtual serial device according to an embodiment of the present invention;
FIG. 6 is a logic diagram of a data buffer for implementing data transmission according to an embodiment of the present invention;
FIG. 7 is a flow chart of data writing according to an embodiment of the present invention;
FIG. 8 is a flow chart of data reading according to an embodiment of the present invention;
FIG. 9 is a system frame diagram provided by an embodiment of the present invention;
FIG. 10 is a flowchart of a data access method according to an embodiment of the present invention;
Fig. 11 is a block diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without making any inventive effort are within the scope of the present invention.
The terms "comprising" and "having" in the description of the invention and in the above-described figures, as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements but may include other steps or elements not expressly listed.
In order to better understand the aspects of the present invention, the present invention will be described in further detail with reference to the accompanying drawings and detailed description.
Next, a data access method provided by the embodiment of the present invention is described in detail. Fig. 1 is a flowchart of a data access method provided by an embodiment of the present invention, where the data access method applied to an access initiator includes the following steps:
and S10, logging in virtual serial equipment created on a local operating system by an access response party, wherein the virtual serial equipment is equipment created by the access response party through a local virtual serial driver, and the virtual serial driver is created based on the channel number of target access channels of a data buffer in a preset programmable logic device.
And S11, initiating an access request to a local operating system of the access response party so that the access response party obtains target response data corresponding to the access request from the local and writes the target response data into the data buffer through a target access channel.
And S12, acquiring target response data from the data buffer through a target access channel so as to complete corresponding data access operation.
In some embodiments, the architecture diagrams of the conventional heterogeneous systems are shown in fig. 2 and fig. 3, in two conventional heterogeneous System forms, a HOST (HOST) and a System On Chip (SOC) have no direct connection data paths, if the HOST accesses an operating System on the System on Chip, the HOST needs to access a gigabit port through a network or access the System by using a universal serial bus to a serial port, so that the hardware cost of the heterogeneous System is increased, and in two conventional heterogeneous System forms, the HOST and the System on Chip have no direct connection data paths, mainly pass through a field programmable gate array and pass through a network connection System on Chip, as a whole, more resources in the field programmable gate array can be occupied, and the HOST accesses the System on Chip only by using an algorithm upgrade, firmware upgrade, an execution command and the like, so that a high-bandwidth network is not needed. Therefore, the invention provides a data access method that the host can directly access the system on chip through the direct communication channel on the basis, in the data access method provided by the invention, the host can directly access the system on chip through the direct communication channel due to the construction of the direct communication channel, and in the same way, the system on chip can also access the host through the direct communication channel. The invention therefore classifies hosts and systems-on-chip as access initiators or access responders, and field programmable gate arrays as preset programmable logic devices. The data access method provided by the invention comprises the specific steps that an access response party creates a corresponding virtual serial port based on the channel number of a target access channel determined by an original data buffer in a preset programmable logic device, creates virtual serial port equipment corresponding to a virtual serial port driver based on a software and hardware combination mode on the basis of the virtual serial port driver, and can be simply understood as a platform. The access initiator logs in the virtual serial device created by the access responder at the moment, namely logs in the platform of the current access responder, and because the access initiator needs to access the access responder, the access initiator needs to initiate an access request (the access request can be understood as a data access request) to a local operating system of the access responder, when the access responder receives the access request, the access initiator specifically analyzes the data which is characterized by the access request and needs to be accessed, namely determines target response data corresponding to the access request, then writes the target response data into a data buffer in a preset programmable logic device, and reads the target response data in the data buffer after the target response data is stored in the data buffer in the preset programmable logic device, so that the access initiator accesses one data of the access responder.
It should be noted that, the number of channels determined according to the data buffer in the preset programmable logic device is determined according to the requirement of the user, but the sum of the widths of the channel signals corresponding to the number of channels under the requirement needs to be smaller than the signal width corresponding to the data buffer.
It should be further noted that, the target access channel is constructed according to a data buffer in a preset programmable logic device, and is used for connecting an access initiator and an access responder, and is characterized by being a virtual channel, and is not a channel formed according to a specific physical connection line.
The invention is not limited to a particular hardware selection of the access initiator, the access responder, and the pre-programmed logic device, which in some embodiments is a HOST, the access responder is a system on a chip, the pre-programmed logic device is a field programmable gate array (Field Programmable GATE ARRAYS, FPGA), the data buffer is a data buffer (FIRST IN FIRST Out, FIFO) with a first-in first-Out read-write policy, or in some embodiments, the access initiator is an SOC, the access responder is an HOST, the pre-programmed logic device is an FPGA, and the data buffer is a FIFO. It should be noted that, the embodiment provided by the present invention is only one implementation manner, but is not limited to only this implementation manner, and may be set according to the needs of the user.
For example, when the access initiator is HOST, the access responder is SOC, the preset programmable logic device is FPGA, and the data buffer is FIFO, and specific data access is realized, HOST firstly logs in the virtual serial device created by the SOC, then sends an access request corresponding to the data currently required to be accessed to the SOC, at this time, the SOC determines the data (target response data) required to be accessed by HOST according to the currently received access request, and writes the target response data into the FIFO, then HOST reads the target response data written in the FIFO, and at this time, the data access of HOST to the SOC is completed.
For example, when the access initiator is SOC, the access responder is HOST, the preset programmable logic device is FPGA, and the data buffer is FIFO, and at this time, when implementing specific system upgrade access, the SOC logs in the virtual serial device created by HOST, then sends an access request corresponding to the current need of system upgrade to HOST, at this time, the HOST determines a corresponding upgrade code or data (target response data) based on the access request, and writes the target response data into FIFO, then the SOC reads the target response data written in FIFO, and performs system upgrade according to the read data, at this time, the system upgrade access of the SOC to HOST is completed.
The technical scheme shows that the data access method is applied to an access initiator and comprises the steps of logging in virtual serial equipment created on a local operating system by an access responder, creating equipment for the access responder through a local virtual serial driver, creating the virtual serial driver based on the channel number of target access channels of a data buffer in a preset programmable logic device, initiating an access request to the local operating system of the access responder so that the access responder can obtain target response data corresponding to the access request locally, writing the target response data into the data buffer through the target access channel, and obtaining the target response data from the data buffer through the target access channel to complete corresponding data access operation. Therefore, the invention logs in the virtual serial device created by the access response party on the local operating system, which is equivalent to constructing a direct communication path between the access initiator and the access response party, can meet the requirement that the access initiator directly accesses the access response party through an internal channel, and can realize the common firmware update, algorithm upgrading and state monitoring requirements of the access initiator on the access response party in the access mode. In addition, the virtual serial port driver is created based on the number of channels, so that the invention can achieve the aim of multi-user access without increasing resources, and further expands the application scene of the data access method provided by the invention.
In some embodiments, since the specific number of virtual serial devices is related to the number of channels, before the virtual serial devices are created, the number of channels of the target access channel, which is the channel used by the access initiator to access the access responder, needs to be determined from the data buffer based on the user requirements. Then after the access initiator determines the number of channels, the number of channels is configured to the access responder through a dual access random access memory in the programmable logic device, so that the number of channels of the access responder is ensured to be the same as that of the access initiator, and the channels can be in one-to-one correspondence. After the access response party determines the current channel number, a virtual serial port driver is created through a software implementation mode based on the embedded driving architecture of the access response party.
The framework for creating the virtual serial port drive is shown in fig. 4, and mainly comprises a serial port drive and an embedded drive framework, wherein in the serial port drive, signal processing for receiving interrupt signals exists between a starting serial port function and a preset programmable logic device, the starting serial port function and the starting function in the embedded drive framework and the starting function in a user space are in a mutually configured relation, the relation mainly realizes one translation action of the interrupt signals, the receiving processing function in the serial port drive and the reading function in the embedded drive framework and the starting function in the user space are in a mutually configured relation, the relation mainly realizes the reading action of data, and the data transmitting function in the serial port drive and the writing function in the embedded drive framework and the starting function in the user space are in a mutually configured relation, and the relation mainly realizes the writing action of the data.
The embedded driving framework can be a tty framework in a Linux embedded system, wherein the tty framework comprises a tty core and a line procedure and is realized by a kernel. When the embedded driving architecture is a tty architecture in a Linux embedded system, the starting serial function is start up, the receiving processing function is vtty _uart_handle_rx, the data sending function is start_tx, the starting function in the embedded driving architecture is N_tty_open, the reading function is N_tty_read, the writing function is N_tty_write, and the starting function in the user space is tty_open.
The invention mainly defines and realizes the structures such as the uart_driver, the uart_ops, the uart_port and the like, and initializes according to the conditions of hardware and driving. The system comprises a virtual serial port device name, a virtual serial port drive name, a primary and secondary device number, a serial port control console and other information, wherein a driver registers the virtual serial port device name, the virtual serial port drive name, the primary and secondary device number, the serial port control console and other information to a system through a virtual register driver, the virtual port structure is used for describing information such as an I/O port or an I/O memory address of a universal asynchronous receiver-transmitter (UART) port, the size of a data buffer, the type of the port and the like, the virtual port structure is used for adding the port through a virtual add_one_port function, the virtual add_ops structure is related to underlying hardware and is also an interface (such as a PCIE interface and the like) cooperated with software and hardware in the system, and specifically comprises a start-serial port setting, an initialization data buffer, a data buffer receiving interrupt processing function and the like, and calling a vtty _uart_handle_rx function to receive target response data after the driver receives the interrupt and transmit the target response data to an application layer of an initiator through a tty_flip_buffer_push function in the structure.
After creating the virtual serial port driver, the access responder needs to create virtual serial port equipment according to the locally created virtual serial port driver so as to ensure that the access initiator can log in. The method comprises the steps of enabling local serial port receiving interruption to be started and configuring a local serial port receiving processing function (first initialization operation) to ensure that the serial port receiving processing function and the receiving interruption under the current serial port meet the requirements of the current use scene, registering a corresponding operating system console and configuring a corresponding console environment, loading virtual serial port drivers to the local according to the number of channels configured by an access initiator after registering the corresponding operating system console, specifically defining the number of the current channels, and creating corresponding virtual serial port devices on a local operating system by utilizing the locally loaded virtual serial port drivers, wherein the number of the virtual serial port devices is one or more, and the virtual serial port devices need to be added into the operating system console after being created as the virtual serial port devices so as to form a whole.
The method comprises the steps of creating a virtual serial device on a local operating system by utilizing a locally loaded virtual serial driver, wherein hardware mounting behavior exists in the process of creating the virtual serial device on the local operating system, so that normal construction and use of the system are guaranteed, and the method further comprises the step of configuring hardware serial address information between the virtual serial device and a preset programmable logic device, namely initializing hardware (second initializing operation) after the virtual serial device is loaded locally and before the virtual serial device is added to an operating system console.
It should be noted that, in the process of loading the virtual serial port driver to the local according to the number of channels configured by the access initiator, it needs to determine whether the number of channels configured by the current access initiator is a non-zero value, and only when the number of channels configured by the access initiator is a non-zero value, the virtual serial port driver can be loaded to the local, otherwise, the virtual serial port driver is forbidden to be loaded to the local, which is because, when the number of channels is a zero value, it indicates that there is no channel between the access initiator and the access responder, so that corresponding virtual serial port and virtual serial port equipment cannot be constructed according to the channels. Wherein the number of channels is determined according to the running script of the access responder.
Wherein configuring the corresponding console environment specifically includes:
1. modifying the file/etc/default/grub to add the virtual serial device to the console, wherein the content= vtty-x,1500000n81;
2. Regenerating a linux start bootstrap program, wherein different operating system commands are different, and the fedora operating system is taken as an example, and the commands are grub 2-mkconfig-o/boot/EFI/EFI/fedora/grub.cfg;
3. The virtual serial driver is loaded manually on the access responder, e.g. 6 serial devices are created, insmod vtty. Ko 6, and the virtual serial devices are checked, ls/dev/vtty, and it is verified on the access responder if the operating system console contains a virtual serial device cat/sys/devices/virtual/tty/con-hole/active.
In summary, the creation flow of the virtual serial device is shown in fig. 5, and includes the following steps:
S20, virtual serial port driving.
And S21, executing a first initialization operation (vyyt _init).
S22, registering an operating system console (register_control).
And S23, registering a driver (player_driver_register).
S24, realizing hardware mounting (vtty _probe).
And S25, executing a second initialization operation (vtty _dev_init).
S26, adding virtual serial port equipment (uart_add_one_port).
S27, finishing.
Since the steps S20 to S27 correspond to the above embodiments, the present invention is not described herein.
The invention provides a complete set of processes of constructing a virtual serial port driver and creating virtual serial port equipment, under the process, a complete set of access channels are constructed for an access initiator and an access responder, under the channels, the requirements of the access initiator on the access responder directly through an internal channel can be met, the common firmware update, algorithm upgrading and state monitoring requirements of the access initiator on the access responder are realized under the access mode, and the application scene is further enlarged.
In some embodiments, at least two data buffers may exist in the preset programmable logic device, and when at least two data buffers exist, read-write clocks of the data buffers may not be consistent, so that metastability of the whole system is improved. Therefore, when the read-write clocks among the data buffers are not consistent, the read-write clocks among the data buffers are adjusted to be consistent in a preset synchronous mode, so that the metastable state of the system is reduced. The read-write clock consistency between the data buffers can be achieved by delaying the clock period (i.e. taking X beats) or by gray code conversion.
It should be noted that, since the data buffer functions as writing data and reading data, its data read-write strategy with first-in first-out is in accordance with the current data transmission requirement, so the data buffer can be selected as the data buffer with first-out read-write strategy.
The invention provides a selection mode of a data buffer, and when a plurality of data buffers are adopted, the synchronous mode is adopted to realize that the reading and writing among the plurality of data buffers are consistent all the time, so that the internal stability of a programmable logic device is improved, and the stability of writing data and reading data in the data buffer is ensured.
In some embodiments, as shown in fig. 6, the specific step of writing the target response data into the data buffer through the target access channel is to monitor whether a full signal sent by the data buffer is received, if the full signal sent by the data buffer is not monitored, writing the target response data into the data buffer through the target access channel, otherwise, prohibiting writing the target response data into the data buffer. That is, before the access responder writes the target response data into the data buffer through the target access channel, it needs to ensure that a space in which the data can be written is reserved in the current data buffer, that is, the current data buffer is in an unfinished state. Therefore, when the full signal sent by the data buffer is not monitored, the current data buffer is in an unfilled state, and the target response data can be written into the data buffer through the target access channel. In addition, in the process of writing target response data, the dual access random access memory is required to perform a reset operation on the data buffer.
It should be clear that the target response data written at present is specifically formed according to the reference number corresponding to the current target access channel and the data to be transmitted corresponding to the current target access channel. That is, since the present invention provides a multi-channel access manner, each channel of the multi-channel access manner may perform access operations, etc., but when two channels simultaneously perform access, the data transmitted through the channels cannot determine which channel needs to perform which access request at the access initiator, so when the access responder writes the data into the data buffer, the written data includes the reference number corresponding to the currently transmitted target access channel.
The method comprises the specific steps of obtaining channel labels corresponding to target access channels, obtaining data to be transmitted corresponding to the target access channels, and combining the data to be transmitted with the corresponding channel labels to obtain target response data corresponding to the target access channels. The specific combination mode comprises the steps of obtaining a target data byte corresponding to current data transmission, obtaining a data byte corresponding to data to be transmitted, filling the data to be transmitted into continuous empty bytes in the target data byte when the data byte to be transmitted is smaller than the target data byte, and filling channel marks corresponding to the current data to be transmitted into the residual empty bytes in the current target data byte so as to obtain target response data corresponding to a target access channel.
In addition, the process of creating the virtual serial device by the access response party further comprises the steps of configuring corresponding device indexes for each created virtual serial device and establishing corresponding relations between different virtual serial devices and different target access channels, so that target response data are written into the data buffer through the target access channels, and further comprises the steps of determining target device indexes corresponding to the virtual serial devices logged in by the current access initiator, and writing the target response data into the data buffer by utilizing the target access channels corresponding to the target device indexes in each target access channel. The main purpose of the current step is to establish a one-to-one correspondence relationship among the target access channel, the virtual serial port and the virtual serial port device, and specifically, the target access channel corresponding to the virtual serial port device logged in by the current access initiator is used as a writing channel, and target response data of the target access channel is written into the data buffer.
On the basis, as shown in fig. 6, the target response data is acquired from the data buffer through the target access channel, which comprises the steps of monitoring whether the non-air break signal sent by the data buffer is received or not, if the non-air break signal sent by the data buffer is monitored, the target response data in the data buffer is read through the target access channel, otherwise, the data is forbidden to be read from the data buffer. The access initiator can only acquire the target response data from the data buffer through the target access channel when the target response data is included in the data buffer, and can not read the target response data from the data buffer when the target response data is not stored in the data buffer. Therefore, only when the off-air signal sent by the data buffer is detected, the target response data is still stored in the data buffer, the target response data in the data buffer is read through the target access channel, and when the off-air signal sent by the data buffer is not detected, the condition that the target response data is not stored in the data buffer is indicated, and the data is forbidden to be read from the data buffer.
The method comprises the specific steps of obtaining target response data from a data buffer through a target access channel due to equipment indexes, wherein the specific steps of reading the target response data in the data buffer through a preset data receiving tool by utilizing the target access channel and forwarding the read target response data to target virtual serial equipment, and the target virtual serial equipment is virtual serial equipment which is determined from the virtual serial equipment and corresponds to the target access channel for transmitting the target response data. The preset data receiving tool can specifically determine the target access channel and the virtual serial device corresponding to the current target response data, so that the virtual serial device corresponding to the current target response data can be used as the target virtual serial device by using the preset data receiving tool, the target response data is sent to the corresponding target virtual serial device through the corresponding target access channel, and one-to-one correspondence of the target response data, the target access channel and the virtual serial device is realized.
In summary, as shown in fig. 7, the writing of the target response data into the data buffer by the multiple channels specifically includes the following steps:
and S30, writing (transmitting) data in multiple channels.
S31, inquiring the virtual serial device index.
And S32, adjusting and determining target response data.
S33, writing the recombined target response data into a data buffer.
S34, finishing.
As shown in fig. 8, the target response data in the multi-channel acquired data buffer specifically includes the following steps:
s40, multi-channel read (receive) data.
S41, determining a target access channel according to the target response data.
S42, determining the target virtual serial device according to the preset data receiving tool.
And S43, sending the target response data to the target virtual serial device through the target access channel.
S44, finishing.
Since the specific embodiments of the steps of fig. 7 and 8 are the same as the above embodiments, the present invention is not repeated here.
In summary, the above embodiment takes the host as an access initiator, the system on chip as an access responder, and the field programmable gate array as a preset programmable logic device, where the data buffer is set to be 16-bit wide (where bit0 to bit7 are data, bit8 to bit10 are channel numbers, and bit11 to bit15 are reserved), and it supports 8 user channels at most. When the internal serial port is configured by adopting an n81 protocol, the conventional transmission bits are respectively 1 start bit, 8 data bits and one stop bit, and the bandwidth is 1500000/10/1024/1024 MB/s (approximately equal to 1.43 MB/s) on the premise that the baud rate is set to 1500000 bps. Because the invention supports 8 channels at most, the total bandwidth is about to transmit according to 16 bitsMB/s. A system framework for the application of the present invention in its current configuration is shown in fig. 9. And it can be seen that the present invention, when implemented to create a channel between a host and a system-on-chip, multiplexes a high-speed serial bus (interface) (e.g., PCIE/axi/Avalon) between the host/system-on-chip and the field-programmable gate array.
In summary, the above embodiment and the system frame shown in fig. 9, and a specific flow of the data access method provided by the present invention is shown in fig. 10, and includes the following steps:
S50, powering up the heterogeneous system.
And S51, powering up the host.
S52, the field programmable gate array program is automatically loaded.
S53, judging whether the data buffer is initialized.
And S54, if yes, performing data writing or reading operation, and if not, returning to the step S53.
S55, judging whether the number of channels acquired by the system-on-chip running script is non-zero.
S56, if yes, loading virtual serial port drive by the system on chip according to the number of channels, and if not, returning to the step S55.
S57, creating a virtual serial device.
S58, processing related operation after the host logs in.
S59, initializing a data buffer by the host.
S60, loading the virtual serial port driver by the host.
S61, the host configures the number of channels to the system on chip according to the user requirement.
S62, opening the serial port tool to log in the virtual serial port device and accessing the system on chip operating system.
It should be noted that, the specific embodiments corresponding to S50-S62 are the same as the above embodiments, so the disclosure is not repeated here.
It should be noted that, the embodiment provided by the present invention is only one implementation manner, but is not limited to only this implementation manner, and may be set according to the needs of the user.
The dashed lines in the drawings are configuration lines.
According to the technical scheme, the invention does not occupy a large amount of resources of the preset programmable device, can efficiently complete data transmission by multiplexing the high-speed bus interface through the data buffer, and has the highest communication rate of 1MB/s+. The low-speed communication requirement is met on the premise of not increasing the cost and reducing the occupation of resources. The invention realizes the operations of terminal login, algorithm upgrading, firmware upgrading, command execution and the like of the access initiator in the access responder through the cooperation of the virtual serial port drive and the preset programmable device. The invention realizes the serial port multi-terminal login by attaching the channel number to the data, and solves the problem that only a single serial port can log in the existing serial port solution without increasing resources.
On the other hand, the invention also provides a data access method, which is applied to the access response party and comprises the following steps:
The virtual serial device is a device which is created in advance on a local operating system through a local virtual serial driver by an access response party, and the virtual serial driver is created based on the number of channels of a target access channel of a data buffer in a preset programmable logic device;
And obtaining target response data corresponding to the access request from the local, and writing the target response data into the data buffer through the target access channel so that the access initiator obtains the target response data from the data buffer through the target access channel.
However, it should be noted that, since the embodiments of the present invention are the same as the above embodiments, the disclosure is not repeated here.
In addition, the invention also provides a heterogeneous system which comprises an access initiator, an access responder and a preset programmable logic device, wherein,
The method comprises the steps that a programmable logic device is preset and used for constructing a target access channel between an access initiator and an access responder through a data buffer of the programmable logic device;
The access initiator is used for logging in the virtual serial device created by the access responder on the local operating system, initiating an access request to the local operating system of the access responder, and acquiring target response data corresponding to the access request from the data buffer through a target access channel;
the access response party is used for locally acquiring target response data corresponding to the access request, and writing the target response data into the data buffer through the target access channel;
the access initiator is a host and the access responder is a system on chip, or the access initiator is a system on chip and the access responder is a host.
However, it should be noted that, since the embodiments of the present invention are the same as the above embodiments, the disclosure is not repeated here.
FIG. 11 is a block diagram of an electronic device according to an embodiment of the present invention, as shown in FIG. 11, the electronic device includes a memory 60 for storing a computer program;
A processor 61 for implementing the steps of the data access method of the above embodiment when executing a computer program.
The electronic device provided in this embodiment may include, but is not limited to, a smart phone, a tablet computer, a notebook computer, a desktop computer, or the like.
Processor 61 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 61 may be implemented in at least one hardware form of Digital Signal Processing (DSP), field-Programmable gate array (fieldprogrammable GATE ARRAY, FPGA), programmable logic array (Programmable Logic Array, PLA). The processor 61 may also include a main processor, which is a processor for processing data in a wake-up state, also referred to as a central processor (Central Processing Unit, CPU), and a coprocessor, which is a low-power processor for processing data in a standby state. In some embodiments, the processor 61 may be integrated with an image processor (Graphics Processing Unit, GPU) for rendering and rendering of content to be displayed by the display screen. In some embodiments, the processor 61 may also include an artificial intelligence (ARTIFICIAL INTELLIGENCE, AI) processor for processing computing operations related to machine learning.
Memory 60 may include one or more computer-readable storage media, which may be non-transitory. Memory 60 may also include high-speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In this embodiment, the memory 60 is at least used for storing a computer program 601, which, when loaded and executed by the processor 61, is capable of implementing the relevant steps of the data access method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 60 may further include an operating system 602, data 603, and the like, where the storage manner may be transient storage or permanent storage. Operating system 602 may include Windows, unix, linux, among other things.
In some embodiments, the electronic device may further include a display 62, an input-output interface 63, a communication interface 64, a power supply 65, and a communication bus 66.
Those skilled in the art will appreciate that the structure shown in fig. 11 is not limiting of the electronic device and may include more or fewer components than shown.
It will be appreciated that the data access method of the above embodiments, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on this understanding, the technical solution of the present invention may be embodied essentially or in part or in whole or in part in the form of a software product stored in a storage medium for performing all or part of the steps of the method according to the embodiments of the present invention. The storage medium includes a U disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), an electrically erasable programmable ROM, a register, a hard disk, a removable magnetic disk, a CD-ROM, a magnetic disk, or an optical disk, etc. which can store program codes.
Based on this, the embodiment of the invention also provides a nonvolatile storage medium, on which a computer program is stored, which when executed by a processor, implements the steps of the data access method as described above.
The invention also provides a computer program product comprising computer programs/instructions which when executed by a processor implement the steps of the data access method as described above.
The above describes in detail an electronic device provided by the embodiment of the present invention. In the description, each embodiment is described in a progressive manner, and each embodiment is mainly described by the differences from other embodiments, so that the same similar parts among the embodiments are mutually referred. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The above description is provided for a data access method, heterogeneous system, electronic device, medium and program product of the present invention. The principles and embodiments of the present invention have been described herein with reference to specific examples, the description of which is intended only to facilitate an understanding of the method of the present invention and its core ideas. It should be noted that it will be apparent to those skilled in the art that various modifications and adaptations of the invention can be made without departing from the principles of the invention and these modifications and adaptations are intended to be within the scope of the invention as defined in the following claims.
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| CN116886751A (en) * | 2023-09-04 | 2023-10-13 | 浪潮(北京)电子信息产业有限公司 | High-speed communication method and device of heterogeneous equipment and heterogeneous communication system |
| US20240031457A1 (en) * | 2023-09-29 | 2024-01-25 | Intel Corporation | Programmable Device-Based Accelerator Framework for Virtualized Environments |
| CN118819873A (en) * | 2024-09-21 | 2024-10-22 | 珠海星云智联科技有限公司 | Virtual function management method, computer equipment, medium and system |
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