CN119126920A - A method and system for automatically obtaining MCU clock frequency by a host computer - Google Patents
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Abstract
本发明涉及MCU技术领域，具体涉及一种适用上位机自动获取MCU时钟频率的方法及系统，步骤包括：连接目标芯片，下载倍频系数评测程序，配置最低倍频系数；运行评测程序，获取结果，调整倍频系数；下载捕获解析程序，配置倍频系数及JTAG_TDI脚产生固定PWM频率；捕获解析程序初始化，读取PWM引脚电平状态；解析时钟频率并保存；上位机连接目标芯片获取并保存时钟频率。本发明通用性强、无需额外硬件、实现简单。自动获取时钟频率，减少人为设置异常，通讯等待时间更精准，可系统时钟诊断。
The present invention relates to the field of MCU technology, and in particular to a method and system for a host computer to automatically obtain an MCU clock frequency, the steps comprising: connecting a target chip, downloading a frequency multiplication coefficient evaluation program, and configuring a minimum frequency multiplication coefficient; running the evaluation program, obtaining results, and adjusting the frequency multiplication coefficient; downloading a capture and analysis program, configuring the frequency multiplication coefficient and the JTAG_TDI pin to generate a fixed PWM frequency; initializing the capture and analysis program, reading the PWM pin level state; analyzing the clock frequency and saving it; the host computer connects to the target chip to obtain and save the clock frequency. The present invention has strong versatility, does not require additional hardware, and is simple to implement. The clock frequency is automatically obtained, the abnormalities of artificial settings are reduced, the communication waiting time is more accurate, and the system clock diagnosis can be performed.
Description
Technical Field
The invention relates to the technical field of MCU (micro control Unit), in particular to a method and a system for automatically acquiring MCU clock frequency by an upper computer.
Background
MCU type chip, as a general programmable device, often needs to carry out program burning and debugging verification many times in the process of program development. When the Flash program is burnt, the time sequence is set based on the input clock of the MCU or the frequency of the system clock as a time base. Therefore, during the program burning process, the user needs to carefully search the hardware circuit to determine the input clock frequency of the target chip, and configure the main burning frequency accordingly. This process requires manual implementation by the user.
For the first type of MCU, there is no integrated on-chip clock source module. In this case, the host debugging software will provide a default clock frequency. The user needs to configure according to the input clock at the hardware board level, setting the clock frequency manually. Although this approach may meet the needs in some cases, the user needs to have some hardware knowledge and debugging experience.
For the second class of MCUs, the clock source module is already integrated in-chip. In this case, the host computer will select a known clock frequency within the chip by default and the user cannot configure it. Although this processing method simplifies the operation, the flexibility is not high, and the requirements of all users may not be satisfied. Therefore, when selecting an MCU, the user needs to decide which type of MCU to select according to his specific requirements and application scenario.
Disclosure of Invention
Aiming at the defects of the prior art, the invention discloses a method and a system for automatically acquiring the MCU clock frequency by using an upper computer, which are used for solving the problems.
The invention is realized by the following technical scheme:
In a first aspect, the present invention provides a method for automatically obtaining a clock frequency of an MCU suitable for an upper computer, including the following steps:
the upper computer is connected with the target chip, downloads the frequency multiplication coefficient evaluation program to the target chip, and configures the lowest frequency multiplication coefficient;
Running a frequency multiplication coefficient evaluation program and evaluating, wherein the upper computer acquires an evaluation result, judges whether the program passes or not, if so, enters the next step, and if not, adjusts the frequency multiplication coefficient;
downloading a capturing analysis program to a target chip, configuring a frequency multiplication coefficient, and simultaneously configuring an emulator JTAG_TDI pin to generate a fixed known PWM frequency;
initializing a capture analysis program, identifying a capture mode variable, configuring CAP and GPIO registers, and continuously reading the level state of a PWM pin to a data RAM;
Analyzing the clock frequency, generating a program end mark and storing the mark in a data RAM, and connecting an upper computer with a target chip to acquire and store the clock frequency.
Furthermore, in the method, a synchronous protocol based on the MCU-JTAG simulation debugging interface is adopted in the process of connecting the upper computer with the target chip. The upper computer is connected with the simulator through a USB interface, and further establishes a communication link with the target chip so as to realize read-write operation on a Micro Controller (MCU) register and a Random Access Memory (RAM).
Furthermore, in the method, the frequency multiplication coefficient evaluation program aims at carrying out data transmission and logic operation on the target chip and generating a marker bit of termination of operation. The operation result and the termination flag bit are stored in a predetermined data RAM area.
Furthermore, in the method, after the upper computer receives the evaluation result, if the evaluation result fails to meet the passing standard, the frequency multiplication coefficient should be reduced by 2 units, and the new frequency multiplication coefficient is used as a new frequency multiplication coefficient of the capturing and analyzing program.
Further, in the method, first, the lowest frequency multiplication coefficient is set for performance evaluation. Subsequently, the frequency multiplication factor is gradually increased after each test, and the cycle is continued. If an abnormality occurs in the calculation result during the test or an end flag bit is not generated, this indicates that the current frequency multiplication coefficient has exceeded the maximum dominant frequency of the microcontroller unit (MCU). At this time, the upper computer should read the configuration value of the Phase Locked Loop (PLL) frequency multiplication register.
Furthermore, in the method, the upper computer is responsible for downloading and analyzing the program, setting the entry address of the target chip program and sending out the operation instruction. In the JTAG interface, TMS and TCK pins should be configured to be in a low state, while other pins should remain in a high impedance state to maintain an idle state.
Further, in the method, the capture analysis program starts an initialization stage, and the upper computer sends an instruction to the simulator to configure TMS and TCK pins of the JTAG interface to be in a low level state. At the same time, the TDI pin outputs a stable Pulse Width Modulation (PWM) frequency signal that is used as a reference time for Microcontroller (MCU) clock frequency calculation. The relationship between the clock frequency and the reference time base will be set according to a clock frequency resolution algorithm.
Furthermore, in the method, the upper computer is responsible for reading the program termination flag bit and the clock frequency value of the microcontroller unit (MCU). If the termination flag bit is invalid, the analysis process of the clock frequency is not successfully executed, otherwise, if the termination flag bit is valid, the clock frequency is read and stored.
Still further, in the method, the number of Pulse Width Modulation (PWM) level periods read should be not less than three.
In a second aspect, the present invention provides a system for automatically acquiring an MCU clock frequency by an upper computer, where the system is configured to implement the method for automatically acquiring an MCU clock frequency by an upper computer according to the first aspect, including
The upper computer is used for running at the PC end, simulating debugging and sending instruction programs;
the simulator is used for realizing the USB-JTAG protocol and generating PWM frequency;
JTAG port, which is used to realize the communication protocol interface of simulation debugging;
The kernel CPU is used for realizing system control and algorithm functions;
The program RAM is used for providing a frequency multiplication coefficient evaluation program and capturing an analysis program running space;
The data RAM is used for providing IO capture level data cache space;
GPIO, which is used for realizing IO multiplexing, input and output and IO state caching functions;
CAP, which is used to realize the function of automatic capturing PWM period and pulse width by edge triggering;
And the PLL is used for realizing frequency multiplication of the input clock frequency and providing a system and peripheral clocks.
The beneficial effects of the invention are as follows:
The invention has strong universality, no need of additional hardware support and simple realization. The Flash program burning software automatically acquires the clock frequency, and frequency setting abnormality caused by human factors is reduced. By automatically acquiring the clock, the communication waiting time of the upper computer is more accurate, and the state flag polling is reduced. System clock diagnostics may be implemented.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic step diagram of a method for automatically acquiring MCU clock frequency by an upper computer;
FIG. 2 is a flow chart of a method for automatically acquiring MCU clock frequency by a host computer;
FIG. 3 is a schematic block diagram of an MCU-CAP capture mode of an embodiment of the present invention;
FIG. 4 is a clock diagram of the MCU-CPU read mode according to an embodiment of the invention
FIG. 5 is a diagram of a CPU data migration program according to an embodiment of the present invention;
FIG. 6 is a program diagram of a clock frequency software algorithm in accordance with an embodiment of the present invention;
fig. 7 is a schematic block diagram of a system for automatically acquiring the clock frequency of an MCU by a host computer.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In one embodiment, referring to fig. 1, a method for automatically obtaining a clock frequency of an MCU by a host computer is provided, including the following steps:
the upper computer is connected with the target chip, downloads the frequency multiplication coefficient evaluation program to the target chip, and configures the lowest frequency multiplication coefficient;
Running a frequency multiplication coefficient evaluation program and evaluating, wherein the upper computer acquires an evaluation result, judges whether the program passes or not, if so, enters the next step, and if not, adjusts the frequency multiplication coefficient;
downloading a capturing analysis program to a target chip, configuring a frequency multiplication coefficient, and simultaneously configuring an emulator JTAG_TDI pin to generate a fixed known PWM frequency;
initializing a capture analysis program, identifying a capture mode variable, configuring CAP and GPIO registers, and continuously reading the level state of a PWM pin to a data RAM;
Analyzing the clock frequency, generating a program end mark and storing the mark in a data RAM, and connecting an upper computer with a target chip to acquire and store the clock frequency.
In the embodiment, the upper computer is connected with the target chip, namely, firstly, the APP1 program is downloaded to the target chip, and the lowest frequency multiplication coefficient is set.
In the embodiment, the APP1 program is operated and evaluated, namely, the upper computer starts the APP1 program and waits for a period of time after operation. And then, the upper computer acquires an evaluation result, judges whether the program passes or not, and adjusts the frequency multiplication coefficient if the program fails.
In the embodiment, the frequency multiplication coefficient is optimized, namely if the APP1 evaluation fails, the frequency multiplication coefficient is subtracted by 2 and then used as the frequency multiplication coefficient of the APP2 program. Subsequently, the upper computer increments the frequency multiplication factor and resets the APP1 program.
In this embodiment, the APP2 program is configured and operated by downloading the APP2 program to the target chip and configuring the optimal frequency multiplication factor. And after running APP2, disconnecting JTAG.
In this embodiment, the PWM frequency acquisition configuration configures the emulator JTAG_TDI pin to generate a fixed known PWM frequency and waits for the APP2 system initialization to complete.
In this embodiment, CAP Capture mode and register configuration after APP2 identifies the Capture mode variable, CAP and GPIO registers are configured to enable CAP Capture and wait for Capture to complete.
In this embodiment, the GPIO register is configured to continuously read the PWM pin level state to the data RAM.
In this embodiment, the clock frequency analysis and data storage are performed by analyzing the clock frequency using a clock analysis algorithm and generating a program end flag to store the program end flag in a specific data RAM.
In the embodiment, the clock frequency of the upper computer is acquired, namely the upper computer enables the JTAG mode to be connected with the target chip after waiting for the designated time, and the clock frequency is acquired and stored.
In one embodiment, the MCU-JTAG emulation debugging interface (the protocol is synchronous) is utilized, the upper computer is connected with the emulator through the USB, and further, communication is established with the target MCU-JTAG to realize read-write operation of MCU registers and RAM, and the upper computer reads and identifies specific registers of the target MCU or reads and writes the RAM to ensure the normal of hardware physical connection and the online state of the target MCU.
In one embodiment, the APP1 has the functions of realizing on-chip data transmission and logic operation by cooperation of a microcontroller unit (MCU) and a Central Processing Unit (CPU) and generating a marker bit of ending operation. The result of the operation and the end flag bit are stored in a designated data Random Access Memory (RAM) area. After development, debugging and verification are completed, the APP1 needs to convert the program execution file into a machine code and store the machine code in an upper computer.
In view of the input clock frequency being unknown (the maximum dominant frequency of the known MCU), the initial evaluation should be configured as the lowest multiplication factor. Subsequently, the test was performed by increasing the frequency multiplication factor stepwise, forming a cycle. If the calculation result is abnormal or the ending zone bit is not generated in a certain test, the current frequency multiplication coefficient is indicated to exceed the maximum main frequency of the MCU. At this time, the upper computer will read the configuration value of the Phase Lock Loop (PLL) frequency multiplication register.
In this embodiment, the main frequency of the microcontroller unit (MCU) in actual operation should not exceed its nominal highest main frequency. When determining the reserved frequency allowance, factors such as the application environment of the MCU, the power consumption of the chip and the heat dissipation performance must be comprehensively considered. By subtracting an appropriate value from the evaluation coefficient of APP1, the frequency multiplication coefficient of APP2 can be obtained. In general, the higher the main frequency is, the higher the corresponding detection accuracy is.
In this embodiment, after the host computer finishes downloading the APP2 program, the host computer configures the entry address of the MCU-PC program, and issues an instruction for full-speed operation. Then, TMS and TCK pins of JTAG interface are set to low level state, while other pins are adjusted to high impedance mode, so as to ensure JTAG interface is in idle state.
In this embodiment, the application APP2 starts executing the initialization program. The host computer sends instructions to the emulator causing the TMS and TCK pins of the JTAG interface of the emulator to be set to a low state. At the same time, the TDI pin generates a fixed, known Pulse Width Modulation (PWM) frequency that will be used as a reference time for the Microcontroller (MCU) clock frequency calculation.
In this embodiment, the initialization time of the MCU-APP2 system must exceed the time required for the JTAG interface TDI to output the PWM configuration to ensure that the PWM signal is stably established before the MCU-APP2 program enters the capture mode.
In this embodiment, the user can set a variable tag in APP2, and the tag is stored in the data RAM. The Central Processing Unit (CPU) of the Microcontroller (MCU) will read this tag to identify and decide what capture mode to use.
In one embodiment, as shown in FIG. 3, in MCU-CAP capture mode, the JTAG_TDI pin of the microcontroller unit (MCU) is required to be capable of being configured to Capture (CAP) input signals. This mode should support a 32-bit counter and allow configuration of the edges of CAP1, CAP2, CAP3 and CAP4 capture sub-modules. When an edge of the input signal triggers, the capture unit will save the current counter value. For example, if CAP1 and CAP2 are configured as rising edge triggers, once acquisition is complete, the difference between CAP2 and CAP1 will represent the number of system clock cycles in the input signal period.
In one embodiment, the MCU-CPU read mode, a fast assembler instruction must be selected for data stacking to achieve uniform cycle and maximized speed per read Pulse Width Modulation (PWM) level. In determining the duration of the read level, the capacity of the data Random Access Memory (RAM), the multiple of the signal frequency and the system clock frequency should be considered, and the number of periods of the read PWM level should be ensured to be not less than 3 periods. The clock circuit of which is shown in fig. 4.
In one embodiment, referring to fig. 2, a method for automatically obtaining the clock frequency of the MCU by using the upper computer is as follows:
1. Initial connection and program download:
-the host computer establishes a connection with the target chip.
Download APP1 program to target chip and set initial frequency multiplication factor (assumed to be the lowest value).
2. APP1 program evaluation and adjustment:
the upper computer starts the APP1 program and waits for a period of time after running to collect the profile.
If the evaluation result shows that APP1 fails, the frequency multiplication factor is automatically adjusted (subtracted by 2) and the program is ready for re-downloading.
If the frequency multiplication factor adjustment is valid, proceeding to the next step, otherwise continuing to adjust the frequency multiplication factor until a preset maximum is reached or a valid setting is found.
3. APP2 program preparation and operation:
-downloading the APP2 program to the target chip using the optimized frequency multiplication coefficients.
-Configuring the optimal frequency multiplication coefficients for use by the APP2 program.
-Running APP2 program and disconnecting JTAG connection after the program running is stable.
4. PWM frequency acquisition preparation:
After disconnecting the JTAG connection, configuring the JTAG_TDI pins by other means (e.g., emulator settings) generates a fixed known PWM frequency.
-Ensuring that the APP2 system has been initialized to completion ready for PWM frequency acquisition.
5. CAP Capture mode configuration and waiting:
after the APP2 program recognizes the capture mode variable, the CAP and GPIO registers are configured to enable the CAP capture function.
Waiting for CAP acquisition to complete ensures that the frequency information of the PWM signal has been properly acquired.
6. GPIO register reading and data processing:
-configuring the GPIO register to continuously read the level state of the PWM pin and save the data into the data RAM.
-Preparing a software algorithm to process the data to resolve the clock frequency.
7. Clock frequency analysis and preservation:
Resolving the clock frequency using software algorithm 1 and algorithm 2, respectively, verifying the accuracy and consistency of the results.
-Saving the parsed clock frequency data to a specific data RAM location and setting a program end flag.
8. And (3) acquiring data of an upper computer:
The host reestablishes the JTAG connection after a specified time, accessing the target chip.
-Reading and saving the clock frequency data obtained from the data RAM for subsequent analysis or processing.
In this embodiment, the parameters used in the algorithm are described as follows:
n cap CAP captures a PWM period corresponding to the CAP module counter difference and the CAP capture value.
F pwm the emulator provides a known fixed frequency.
And F clkin, inputting a clock frequency and an unknown value by the MCU.
A pll_mult PLL frequency multiplication coefficient, known value.
T mov the number of cycles required to assemble the move instruction, a known value.
The formula of the clock frequency algorithm 1 of the MCU-CAP mode in the embodiment is as follows:
it is required that the MCU chip integrates CAP and JTAG related pins can be configured as input pins of CAP modules.
F sysclk= Fclkin* Apll_mult// equation 1 CAP counter input frequency is configured as system frequency
The CAP captured PWM period value is equal to the known PWM period value to obtain the following formula
(1/F sysclk) * Ncap=1/ Fpwm// equation 2)
Substitution of equation 1 into equation 2 yields
N cap/(Fclkin* Apll_mult)= 1/ Fpwm gives F clkin= Ncap* Fpwm/ Apll_mult.
MCU-CPU mode clock frequency algorithm 2 formula:
the requirement is that the number of the PWM level periods is > =3, and an assembly shift instruction is recommended, the original address is unchanged, the destination address is increased, and the PWM level periods are stacked by a plurality of repeated instructions.
Sequentially and continuously reading PWM pin level to data RAM, comparing data in RAM, finding RAM position of 1-0 or 0-1 and storing its address A n
Continuously reading the space value of the data RAM, comparing to find the 0-1 or 1-0 data RAM position and storing the address A n+1
The space value of the data RAM is continuously read to find the position of the data RAM with 1 to 0 or 0 to 1, and the address A is saved n+2
The PWM period is the two consecutive variations difference N read_sysclk= An+2-An.
F sysclk= Fclkin* Apll_mult// equation 3
Capturing by the CPU that the PWM period value is equal to the known PWM period value results in the following formula
(1/F sysclk) * Nread_sysclk* Tmov=1/ Fpwm// equation 4)
Substitution of equation 3 into equation 4 yields
N read_sysclk* Tmov/(Fclkin* Apll_mult)= 1/ Fpwm gives F clkin= Fpwm* Nread_sysclk* Tmov/ Apll_mult.
In one embodiment, the external input clock frequency is automatically identified by selecting CPU mode for AVP32F069, ADP32F035B finished Flash test.
F pwm simulator JTAG_TDI provides a PWM frequency of 100KHz.
And A pll_mult, obtaining a PLL frequency multiplication coefficient of 10 through an APP1 program, wherein the specification CLKINMAX < = 30MHz, and the highest dominant frequency is less than 120MHz. The APP1 program is a general algorithm for CRC32 checking on BOOTROM, which is not shown here.
F clkin, the real input frequency is 10MHz, and the frequency is identified to be 9.9-10.1 MHz by the method.
The CPU data migration program is shown in fig. 5 and the clock frequency software algorithm program is shown in fig. 6.
In this embodiment, the upper computer downloads the first program APP1 to the RAM in the MCU through the JTAG interface of the emulator, runs the program to evaluate an optimal frequency multiplication coefficient, downloads the second program APP2 to the RAM in the MCU, issues a command to enable the emulator to exit the JTAG debug mode and the TDI pin of the JTAG interface provides a known fixed PWM frequency, reads the PWM level state through the MCU-CPU and stores the PWM level state to the data RAM or enables the RAM in the MCU to capture PWM, analyzes the clock frequency through the software algorithm of the MCU, and enables the JTAG mode to read the result of the MCU-specified data RAM clock frequency.
In one embodiment, referring to FIG. 7, a system for automatically obtaining MCU clock frequency by a host computer is provided, comprising
The upper computer is used for running at the PC end, simulating debugging and sending instruction programs;
the simulator is used for realizing the USB-JTAG protocol and generating PWM frequency;
JTAG port, which is used to realize the communication protocol interface of simulation debugging;
The kernel CPU is used for realizing system control and algorithm functions;
The program RAM is used for providing a frequency multiplication coefficient evaluation program and capturing an analysis program running space;
The data RAM is used for providing IO capture level data cache space;
GPIO, which is used for realizing IO multiplexing, input and output and IO state caching functions;
CAP, which is used to realize the function of automatic capturing PWM period and pulse width by edge triggering;
And the PLL is used for realizing frequency multiplication of the input clock frequency and providing a system and peripheral clocks.
In conclusion, the invention has strong universality, no need of additional hardware support and simple realization. The Flash program burning software automatically acquires the clock frequency, and frequency setting abnormality caused by human factors is reduced. By automatically acquiring the clock, the communication waiting time of the upper computer is more accurate, and the state flag polling is reduced. System clock diagnostics may be implemented.
The foregoing embodiments are merely for illustrating the technical solution of the present invention, but not for limiting the same, and although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art that modifications may be made to the technical solution described in the foregoing embodiments or equivalents may be substituted for parts of the technical features thereof, and that such modifications or substitutions do not depart from the spirit and scope of the technical solution of the embodiments of the present invention in essence.
Claims (10)
1. The method for automatically acquiring the MCU clock frequency by using the upper computer is characterized by comprising the following steps of:
the upper computer is connected with the target chip, downloads the frequency multiplication coefficient evaluation program to the target chip, and configures the lowest frequency multiplication coefficient;
Running a frequency multiplication coefficient evaluation program and evaluating, wherein the upper computer acquires an evaluation result, judges whether the program passes or not, if so, enters the next step, and if not, adjusts the frequency multiplication coefficient;
downloading a capturing analysis program to a target chip, configuring a frequency multiplication coefficient, and simultaneously configuring an emulator JTAG_TDI pin to generate a fixed known PWM frequency;
initializing a capture analysis program, identifying a capture mode variable, configuring CAP and GPIO registers, and continuously reading the level state of a PWM pin to a data RAM;
Analyzing the clock frequency, generating a program end mark and storing the mark in a data RAM, and connecting an upper computer with a target chip to acquire and store the clock frequency.
2. The method for automatically acquiring the clock frequency of the MCU by using the upper computer according to claim 1, wherein in the method, when the upper computer is connected with a target chip, the upper computer establishes communication with the target chip through a USB connection simulator based on an MCU-JTAG simulation debugging interface and by using a synchronous protocol, so as to realize reading and writing of an MCU register and a RAM.
3. The method for automatically obtaining the clock frequency of the MCU by using the upper computer according to claim 1, wherein in the method, a frequency multiplication coefficient evaluation program is used for data migration and logic operation in a target chip and generates an operation ending zone bit, and an operation result and the ending zone bit are stored in a specified data RAM space.
4. The method for automatically obtaining the clock frequency of the MCU by using the upper computer according to claim 1, wherein in the method, after the upper computer obtains the evaluation result, if the evaluation result does not pass, the upper computer subtracts 2 from the frequency multiplication coefficient to be used as the frequency multiplication coefficient of the capturing analysis program.
5. The method for automatically obtaining the clock frequency of the MCU by the upper computer according to claim 1, wherein in the method, the lowest frequency multiplication coefficient is firstly configured for evaluation, each test is gradually increased by the frequency multiplication coefficient, when the calculation result is abnormal or the end zone bit does not generate the highest main frequency which indicates that the frequency multiplication coefficient exceeds the MCU, the upper computer reads the configuration value of the PLL frequency multiplication register.
6. The method for automatically obtaining the clock frequency of the MCU by the upper computer according to claim 1, wherein in the method, the upper computer downloads the analysis program, sets the entry address of the target chip program, issues the operation instruction, configures the JTAG port TMS and the TCK pin to be low level, and keeps the rest in a high-impedance state and an idle state.
7. The method for automatically acquiring the clock frequency of the MCU by using the upper computer according to claim 1, wherein in the method, a capturing analysis program is initialized, the upper computer commands the simulator to configure JTAG port TMS, TCK to be low level, TDI generates a fixed PWM frequency as a reference time base for calculating the clock frequency of the MCU, and the frequency relation is set by a clock frequency analysis algorithm.
8. The method for automatically obtaining the clock frequency of the MCU by the upper computer according to claim 1, wherein in the method, the upper computer reads the ending flag bit and the clock frequency value of the MCU program, if the ending flag bit is invalid, the clock frequency analysis is invalid, and if the ending flag bit is valid, the clock frequency is read and stored.
9. The method for automatically obtaining the clock frequency of the MCU by using the upper computer according to claim 1, wherein the number of the periods of the read PWM level is more than or equal to 3.
10. A system for automatically acquiring MCU clock frequency by a host computer, the system being used for realizing the method for automatically acquiring MCU clock frequency by a host computer according to any one of claims 1 to 9, comprising
The upper computer is used for running at the PC end, simulating debugging and sending instruction programs;
the simulator is used for realizing the USB-JTAG protocol and generating PWM frequency;
JTAG port, which is used to realize the communication protocol interface of simulation debugging;
The kernel CPU is used for realizing system control and algorithm functions;
The program RAM is used for providing a frequency multiplication coefficient evaluation program and capturing an analysis program running space;
The data RAM is used for providing IO capture level data cache space;
GPIO, which is used for realizing IO multiplexing, input and output and IO state caching functions;
CAP, which is used to realize the function of automatic capturing PWM period and pulse width by edge triggering;
And the PLL is used for realizing frequency multiplication of the input clock frequency and providing a system and peripheral clocks.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5905887A (en) * | 1995-03-01 | 1999-05-18 | Opti Inc. | Clock frequency detection for computer system |
| JP2008099228A (en) * | 2006-09-15 | 2008-04-24 | Ricoh Co Ltd | Serial data communication system and image forming apparatus |
| CN113301220A (en) * | 2021-04-27 | 2021-08-24 | 上海欧菲智能车联科技有限公司 | Synchronization method for vehicle-mounted camera and vehicle lamp and FPGA chip |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5905887A (en) * | 1995-03-01 | 1999-05-18 | Opti Inc. | Clock frequency detection for computer system |
| JP2008099228A (en) * | 2006-09-15 | 2008-04-24 | Ricoh Co Ltd | Serial data communication system and image forming apparatus |
| CN113301220A (en) * | 2021-04-27 | 2021-08-24 | 上海欧菲智能车联科技有限公司 | Synchronization method for vehicle-mounted camera and vehicle lamp and FPGA chip |
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