CN119110677A - Deep trench capacitor structure and manufacturing method thereof - Google Patents
Deep trench capacitor structure and manufacturing method thereof Download PDFInfo
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- CN119110677A CN119110677A CN202411098821.3A CN202411098821A CN119110677A CN 119110677 A CN119110677 A CN 119110677A CN 202411098821 A CN202411098821 A CN 202411098821A CN 119110677 A CN119110677 A CN 119110677A
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- layer
- dielectric layer
- polysilicon
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- deep trench
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- 239000003990 capacitor Substances 0.000 title claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000010410 layer Substances 0.000 claims abstract description 200
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 90
- 229920005591 polysilicon Polymers 0.000 claims abstract description 84
- 229910052751 metal Inorganic materials 0.000 claims abstract description 70
- 239000002184 metal Substances 0.000 claims abstract description 70
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 239000011229 interlayer Substances 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims description 20
- 230000004888 barrier function Effects 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 12
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 6
- 150000004767 nitrides Chemical class 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical group [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- 230000003071 parasitic effect Effects 0.000 abstract description 3
- 230000000903 blocking effect Effects 0.000 abstract 2
- 239000004065 semiconductor Substances 0.000 description 8
- 229910021332 silicide Inorganic materials 0.000 description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000000945 filler Substances 0.000 description 4
- 230000005669 field effect Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a deep trench capacitor structure, which comprises a doped region of a substrate, a polysilicon conductive layer structure, a metal electrode structure, an electrode dielectric layer, an interlayer dielectric layer, a plurality of contact windows and a doped region, wherein the doped region is provided with a two-dimensional trench array which is defined in the substrate, the two-dimensional trench array is provided with a field-shaped structure formed by a plurality of sections defined in the two-dimensional trench array, a plurality of grooves are formed in each section, the polysilicon conductive layer structure is arranged in at least one layer of the grooves, the metal electrode structure is formed on the polysilicon conductive layer structure and comprises a blocking layer and a filling metal layer formed on the blocking layer, the electrode dielectric layer is filled in the remaining grooves, an air gap is formed in the electrode dielectric layer, the interlayer dielectric layer covers the electrode dielectric layer, the polysilicon conductive layer structure and the metal electrode structure, and the contact windows are respectively connected to an exposed top surface of the polysilicon conductive layer structure and the doped region of the substrate. The invention reduces the resistivity, reduces the resistance of the metal electrode and the contact resistance of the contact window, and reduces the parasitic resistance.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and in particular, to a deep trench capacitor structure and a method for fabricating the same.
Background
In application number (CN 109427753) a publication is disclosed:
Referring to fig. 1, the trench array 808 is symmetric in the center of the letter-field shape, and four trench sections (blocks) 808s are arranged in mutually perpendicular directions, and the stresses of the adjacent trench sections are mutually offset, so that the strain is further relieved by introducing the air gap 804, and the wafer warpage is greatly reduced;
Referring to fig. 2, in the prior art, the electrodes are filled with polysilicon, which has high resistivity and severe air gap load effect.
In order to solve the above-mentioned problems, a novel deep trench capacitor structure and a method for manufacturing the same are needed.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a deep trench capacitor structure and a method for fabricating the same, which are used for solving the problem that the arrangement of a trench array and a contact window in the prior art is difficult to solve the problem of stress release.
To achieve the above and other related objects, the present invention provides a deep trench capacitor structure, comprising:
a doped region of a substrate, wherein a two-dimensional groove array is defined in the doped region, the two-dimensional groove array is provided with a field-shaped structure formed by a plurality of sections defined in the two-dimensional groove array, and a plurality of grooves are formed in each section;
The polycrystalline silicon conducting layer structure is arranged in at least one layer of the groove;
a metal electrode structure formed on the polysilicon conductive layer structure, the metal electrode structure including a barrier layer and a filler metal layer formed on the barrier layer;
filling the electrode dielectric layer of the rest grooves, wherein air gaps are formed in the electrode dielectric layer;
the interlayer dielectric layer covers the electrode dielectric layer, the polycrystalline silicon conducting layer structure and the metal electrode structure;
And a plurality of contact windows respectively connected to an exposed top surface of the polysilicon conductive layer structure, an exposed top surface of the metal electrode structure and the doped region of the substrate.
Preferably, the polysilicon conductive layer structure comprises a polysilicon layer.
Preferably, the polysilicon conductive layer structure further comprises a dielectric layer disposed between the polysilicon layer and the substrate or between the polysilicon layer and the polysilicon layer according to capacitance density.
Preferably, the dielectric layer comprises an oxide/nitride/oxide.
Preferably, edge portions of the electrode dielectric layer, the polysilicon conductive layer structure and the metal electrode structure are of a stepped structure.
Preferably, a side wall is formed on the side wall of the step-shaped structure.
Preferably, the material of the barrier layer includes titanium and titanium nitride.
Preferably, the material of the filling metal layer is tungsten.
The invention also provides a manufacturing method of the deep trench capacitor structure, which comprises the following steps:
Forming a two-dimensional groove array in a doped region of a substrate, wherein the two-dimensional groove array is provided with a field-shaped structure formed by a plurality of sections defined in the two-dimensional groove array, and a plurality of grooves are formed in each section;
step two, forming at least one layer of polycrystalline silicon conducting layer structure in the groove;
forming a metal electrode structure on the polysilicon conductive layer structure, wherein the metal electrode structure comprises a barrier layer and a filling metal layer formed on the barrier layer;
forming an electrode dielectric layer filling the rest grooves, wherein air gaps are formed in the electrode dielectric layer;
Forming an interlayer dielectric layer covering the electrode dielectric layer, the polycrystalline silicon conducting layer structure and the metal electrode structure;
And thirdly, forming a plurality of contact windows on the interlayer dielectric layer, wherein the contact windows are respectively connected to an exposed top surface of the needed polycrystalline silicon conducting layer structure, an exposed top surface of the metal electrode structure and the doped region of the substrate.
Preferably, the polysilicon conductive layer structure in the second step includes a polysilicon layer.
Preferably, the polysilicon conductive layer structure in the second step further includes a dielectric layer disposed between the polysilicon layer and the substrate or between the polysilicon layer and the polysilicon layer according to the capacitance density.
Preferably, the dielectric layer in step two comprises oxide/nitride/oxide.
Preferably, the electrode dielectric layer, the polysilicon conductive layer structure and the edge part of the metal electrode structure in the second step are in a step structure.
Preferably, a side wall is formed on the side wall of the step-shaped structure in the second step.
Preferably, the material of the barrier layer in the second step includes titanium and titanium nitride.
Preferably, the material of the filling metal layer in the second step is tungsten.
As described above, the deep trench capacitor structure and the method for manufacturing the same of the present invention have the following advantages:
Compared with the traditional polysilicon process, the invention has the advantages of reduced resistivity, reduced resistance of the metal electrode and contact resistance of the contact window, thereby reducing parasitic resistance, having no air gap load effect, omitting the step of forming metal silicide and avoiding the problem of electric leakage caused by forming metal silicide between layers of the multi-layer mechanism.
Drawings
FIG. 1 is a schematic diagram showing a layout of a trench array and a contact window and a cross-sectional structure of a device according to the prior art;
FIG. 2 is a schematic illustration of a prior art electrode filled with polysilicon;
FIG. 3 is a schematic diagram of a trench array according to the present invention;
FIG. 4 is a schematic cross-sectional view of a trench array according to the present invention;
FIG. 5 is a schematic diagram of a deep trench capacitor structure according to the present invention;
FIG. 6 shows a schematic process flow diagram of the present invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Many different implementations or examples are disclosed below to implement different features of embodiments of the present disclosure. Specific elements and arrangements thereof are described below to illustrate embodiments of the disclosure. These embodiments are, of course, merely examples and are not intended to limit the scope of the embodiments of the present disclosure. For example, reference in the specification to a first feature being formed on a second feature includes embodiments in which the first feature is in direct contact with the second feature, and also includes embodiments in which other features are additionally present between the first feature and the second feature, i.e., the first feature is not in direct contact with the second feature. Further, embodiments of the present disclosure may repeat reference numerals and/or letters in the various examples. The above repetition is for the purpose of simplicity and clarity and does not in itself limit the relationship between the various embodiments and/or configurations discussed.
Furthermore, spatially relative terms, such as "under," "below," "lower," "above," "higher," and the like, may be used herein to facilitate a description of the relationship of one element(s) or feature(s) to another element(s) or feature(s) in the drawings, including different orientations of the device in use or operation, and the orientation depicted in the drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative descriptors used herein interpreted in terms of the turned orientation.
It should also be noted that the disclosed embodiments are described in terms of trench capacitor structures that may be included in integrated circuits (e.g., micro processor controllers (fpcs)), memory devices, and/or some other integrated circuits. The integrated circuits may also include various passive and active microelectronic devices such as resistors (resistors), other types of capacitors (e.g., metal-insulator-metal capacitor (MIMCAP)), inductors (inductors), diodes, metal-oxide-semiconductor field effect transistors (MOSFETs), complementary metal-oxide-semiconductor field effect transistors (CMOS transistors), bipolar junction transistors (bipolarjunctiontransistors, BJTs), laterally diffused metal-oxide-semiconductor field effect transistors (laterly diffusedMOStransistors, LDMOS), high-power metal-oxide-semiconductor transistors (high power MOS transistors), or other types of transistors. One of ordinary skill in the art will recognize other embodiments of semiconductor devices that may benefit from aspects of the present disclosure.
Referring to fig. 5, the present invention provides a deep trench capacitor structure, comprising:
a doped region 102 of a substrate 101 having a two-dimensional trench array defined therein, the two-dimensional trench array having a field-shaped structure formed by a plurality of sections defined therein, each section having a plurality of grooves disposed therein;
The substrate 101 may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a group III-V substrate, or some other semiconductor substrate.
The number of grooves in each section can be consistent or inconsistent, and the arrangement direction in each section can be adjusted according to actual requirements. For example, referring to fig. 3, the two-dimensional groove array is formed in a windmill shape.
The cross section of the groove is shown in fig. 4, and the low-resistance doped region 102 is formed by diffusion doping;
Each section basically has the same groove cross-sectional structure, but the difference is made whether the contact hole is connected to the electrode step of each layer on the periphery.
A polysilicon conductive layer structure disposed in at least one of the grooves, and
In some embodiments, the polysilicon conductive layer structure comprises a polysilicon layer.
In some embodiments, the polysilicon conductive layer structure further includes a dielectric layer disposed between the polysilicon layer and the substrate 101 or between the polysilicon layer and the polysilicon layer according to a capacitance density. For example, referring to fig. 5, in the case that the polysilicon conductive layer structure is a first polysilicon conductive layer 103 and a second polysilicon conductive layer 104 stacked in sequence, a dielectric layer may be formed according to the requirement of capacitance density, or a dielectric layer of 2 layers may be formed.
In some embodiments, the dielectric layer comprises an oxide/nitride/oxide.
A metal electrode structure 105 formed on the polysilicon conductive layer structure, the metal electrode structure 105 including a barrier layer and a filler metal layer formed on the barrier layer;
The stress of the substrate 101 (such as a wafer) can be released through the subsequent steps, the groove is not required to be filled by a filling metal layer, then a layer of electrode dielectric layer 106 is deposited, an air gap 107 is formed at the central position, and the air gap 107 cannot exceed the height of the metal electrode structure 105 at the highest;
in some embodiments, the edge portions of the electrode dielectric layer 106, the polysilicon conductive layer structure, and the metal electrode structure 105 are stepped structures.
In some embodiments, the sidewall of the stepped structure has a sidewall 108 formed thereon.
An interlayer dielectric layer 109 covering the electrode dielectric layer 106, the polysilicon conductive layer structure, and the metal electrode structure 105;
In some embodiments, the material of the barrier layer includes titanium and titanium nitride.
In some embodiments, the material of the filler metal layer is tungsten.
A plurality of contact windows 110 are respectively connected to an exposed top surface of the desired polysilicon conductive layer structure, an exposed top surface of the metal electrode structure 105, and the doped region 102 of the substrate 101.
For example, some methods of forming trench capacitors include forming a two-dimensional array of trenches in a substrate 101 (e.g., a wafer). Stacked polysilicon conductive layer structures and metal electrode structures 105 are formed to cover the substrate 101 and completely fill the trenches of the array. In addition, the polysilicon conductive layer structure and the metal electrode structure 105 are vertically stacked and each conductive layer lines the trench. The electrodes are each successively patterned from the top of the stack of metal electrode structures 105 to the bottom of the stack of polysilicon conductive layer structures. An interlayer dielectric layer 109 (inter-LAYER DIELECTRIC LAYER) is formed to cover the substrate 101 and the electrode stack, and chemical-mechanical polishing (CMP) is performed on top of the interlayer dielectric layer. Contact 110 (contactvias) is formed through the interlayer dielectric and extends to the electrode.
The contact 110 is formed by contact hole etching and contact hole filling to connect the electrodes respectively, and the step of forming metal silicide can be omitted because the contact resistance between the contact string and the metal electrode structure 105 is low, and the subsequent process continues to form necessary metal/via/passivation layers.
In other embodiments of the present invention, the number of gate polysilicon layers is not limited to two, and the pattern arrangement of each contact 110/polysilicon layer/metal electrode structure 105 may be changed accordingly.
Referring to fig. 6, the present invention further provides a method for manufacturing the deep trench capacitor structure, which includes:
Step one, forming a two-dimensional groove array in a doped region 102 of a substrate 101, wherein the two-dimensional groove array has a field-shaped structure formed by a plurality of sections defined therein, and each section is provided with a plurality of grooves;
The substrate 101 may be a bulk silicon substrate 101, a silicon-on-insulator (SOI) substrate 101, a group III-V substrate 101, or some other semiconductor substrate 101.
The number of grooves in each section can be consistent or inconsistent, and the arrangement direction in each section can be adjusted according to actual requirements. For example, referring to fig. 3, the two-dimensional groove array is formed in a windmill shape.
The cross section of the groove is shown in fig. 4, and the low-resistance doped region 102 is formed by diffusion doping;
Each section basically has the same groove cross-sectional structure, but the difference is made whether the contact hole is connected to the electrode step of each layer on the periphery.
Step two, forming at least one layer of polycrystalline silicon conducting layer structure in the groove;
Forming a metal electrode structure 105 on the polysilicon conductive layer structure, the metal electrode structure 105 including a barrier layer and a filler metal layer formed on the barrier layer;
forming an electrode dielectric layer 106 filling the remaining grooves, wherein the electrode dielectric layer 106 can be an oxide layer, and an air gap 107 is formed in the electrode dielectric layer 106;
Forming an interlayer dielectric layer 109 covering the electrode dielectric layer 106, the polysilicon conductive layer structure and the metal electrode structure 105;
In some embodiments, the polysilicon conductive layer structure in step two comprises a polysilicon layer.
In some embodiments, the polysilicon conductive layer structure in the second step further includes a dielectric layer disposed between the polysilicon layer and the substrate 101 or between the polysilicon layer and the polysilicon layer according to the capacitance density. For example, referring to fig. 5, in the case that the polysilicon conductive layer structure is a first polysilicon conductive layer 103 and a second polysilicon conductive layer 104 stacked in sequence, a dielectric layer may be formed according to the requirement of capacitance density, or a dielectric layer of 2 layers may be formed.
In some embodiments, the dielectric layer in step two comprises an oxide/nitride/oxide.
In some embodiments, the edge portions of the electrode dielectric layer 106, the polysilicon conductive layer structure, and the metal electrode structure 105 in the second step are in a stepped structure.
In some embodiments, the sidewall 108 is formed on the sidewall of the step-like structure in the second step.
In some embodiments, the material of the barrier layer in step two comprises titanium and titanium nitride.
In some embodiments, the material of the filling metal layer in the second step is tungsten.
Step three, forming a plurality of contact windows 110 on the interlayer dielectric 109, which are respectively connected to an exposed top surface of the desired polysilicon conductive layer structure, an exposed top surface of the metal electrode structure 105, and the doped region 102 of the substrate 101.
For example, some methods of forming trench capacitors include forming a two-dimensional array of trenches in a substrate 101 (e.g., a wafer). Stacked polysilicon conductive layer structures and metal electrode structures 105 are formed to cover the substrate 101 and completely fill the trenches of the array. In addition, the polysilicon conductive layer structure and the metal electrode structure 105 are vertically stacked and each conductive layer lines the trench. The electrodes are each successively patterned from the top of the stack of metal electrode structures 105 to the bottom of the stack of polysilicon conductive layer structures. An interlayer dielectric layer 109 (inter-LAYER DIELECTRIC LAYER) is formed to cover the substrate 101 and the electrode stack, and chemical-mechanical polishing (CMP) is performed on top of the interlayer dielectric layer. Contact 110 (contactvias) is formed through the interlayer dielectric and extends to the electrode.
The contact 110 is formed by contact hole etching and contact hole filling to connect the electrodes respectively, and the step of forming metal silicide can be omitted because the contact resistance between the contact string and the metal electrode structure 105 is low, and the subsequent process continues to form necessary metal/via/passivation layers.
In other embodiments of the present invention, the number of gate polysilicon layers is not limited to two, and the pattern arrangement of each contact 110/polysilicon layer/metal electrode structure 105 may be changed accordingly.
In summary, compared with the traditional polysilicon process, the invention has the advantages of reduced resistivity, reduced resistance of the metal electrode and contact resistance of the contact window, thereby reducing parasitic resistance, no air gap load effect, omitting the step of forming metal silicide and avoiding the problem of electric leakage caused by forming metal silicide between layers. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (16)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202411098821.3A CN119110677A (en) | 2024-08-12 | 2024-08-12 | Deep trench capacitor structure and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411098821.3A CN119110677A (en) | 2024-08-12 | 2024-08-12 | Deep trench capacitor structure and manufacturing method thereof |
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| CN119110677A true CN119110677A (en) | 2024-12-10 |
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| CN202411098821.3A Pending CN119110677A (en) | 2024-08-12 | 2024-08-12 | Deep trench capacitor structure and manufacturing method thereof |
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