CN119069426A

CN119069426A - A CMOS device manufacturing process and a CMOS device manufactured based on the process

Info

Publication number: CN119069426A
Application number: CN202411171358.0A
Authority: CN
Inventors: 张运炎; 张唯桐
Original assignee: Zhejiang University ZJU
Current assignee: Zhejiang University ZJU
Priority date: 2024-08-23
Filing date: 2024-08-23
Publication date: 2024-12-03

Abstract

The invention discloses a CMOS device manufacturing process, which comprises the steps of depositing a nickel-containing metal layer and a covering layer on a substrate, performing a first-step rapid thermal annealing process to form a high-resistance nickel silicide layer, selectively etching to remove the covering layer and unreacted metal, depositing a contact etching barrier layer, and performing a second-step spike annealing process to form a low-resistance nickel silicide layer. The second annealing process step and the contact etching barrier layer deposition step are sequentially exchanged, and the contact etching barrier layer is used as a protective layer, so that the second spike annealing can be completed in the same machine platform with the first rapid thermal annealing without causing extra nickel metal pollution, new process steps and equipment are not required to be added, the production cost is reduced, meanwhile, the introduction of the spike annealing can effectively control the diffusion of nickel atoms, inhibit the generation of nickel silicide defects and obviously improve the leakage current of devices.

Description

CMOS device manufacturing process and CMOS device manufactured based on same

Technical Field

The invention relates to the technical field of semiconductors, in particular to a CMOS device manufacturing process.

Background

The salicide process plays a very important role in very large scale integrated circuits, and is one of the key manufacturing processes for high performance devices. The process reduces the series parasitic resistance of the grid electrode and the source/drain electrode, and shortens the RC delay of the device. In addition, since a self-aligned process is adopted, the technology does not need to add photoetching and etching steps, so that the process complexity is greatly reduced. The nickel silicide technology is widely applied to nodes of 65nm and below due to the advantages of small silicon consumption, low thermal budget, wireless wide effect, bridging failure and the like. A typical self-aligned nickel silicide process comprises the steps of depositing a nickel-containing metal layer and a capping layer on a substrate, performing a first step of rapid thermal annealing to form a high-resistance nickel silicide layer, selectively etching to remove the capping layer and unreacted metal, and performing a second step of rapid thermal annealing to form a low-resistance nickel silicide layer.

Nickel atoms are always main diffusion substances in the silicidation reaction process, and the diffusion speed in silicon is high (the diffusion coefficient is 10 ^-14m²/s at 500 ℃), so that the nickel atoms are extremely easy to generate uneven abnormal diffusion, and the interface of silicide/silicon is rough or corrosion defects are formed. With the continuous miniaturization of technology nodes, the size of devices is smaller and smaller, and even if nickel silicide defects are only a few nanometers, the leakage current of the devices is increased sharply, so that the static power consumption of products is increased, the yield and the reliability are reduced, and further application of the products is limited.

To suppress the abnormal diffusion of nickel atoms, many methods have been attempted. The introduction of the spike annealing process is widely adopted as a convenient and effective method. Spike annealing is extremely high in rapid thermal annealing, and is applied to the activation of doped ions and the repair of lattice damage after the source/drain electrode ion implantation of the CMOS front-end process at first, so that the spike annealing has higher temperature rise and lower heating time, and the spike annealing is applied to the second-step annealing process of nickel silicide, so that the thermal budget can be effectively reduced, and the short time scale is beneficial to controlling the diffusion of nickel atoms. The spike annealing machine is generally basically consistent with the rapid thermal annealing machine, so that the spike annealing can be realized on the rapid thermal annealing machine through simple debugging and calibration without adding new equipment, and the production cost is greatly reduced. To ensure that the thermal budget of the spike anneal is sufficient to fully convert the high resistance nickel silicide to low resistance nickel silicide, the temperature setting of the spike anneal is typically 100-200 ℃ higher than the rapid thermal anneal. Considering the rapid diffusion of nickel atoms at high temperatures, there is a potential risk of nickel metal contaminating the tool chamber, which can affect subsequent work of the tool, thereby affecting the yield of the product. To prevent nickel atoms from escaping, a protective layer may be coated on the nickel metal layer, but the additional addition of a protective layer increases the process steps, the cost and the process complexity.

Therefore, a method is desired that can suppress the occurrence of nickel silicide defects without adding new process steps and equipment to improve the yield and reliability of CMOS devices.

Disclosure of Invention

In the summary, a series of concepts in a simplified form are introduced, which will be further described in detail in the detailed description. The summary of the invention is not intended to define the key features and essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

The invention aims to provide a CMOS device manufacturing process for solving the problems of serious yield and reliability caused by nickel silicide defects in a small-sized CMOS device.

The invention adopts the following technical scheme:

the first aspect of the invention provides a CMOS device manufacturing process, comprising the steps of depositing a nickel-containing metal layer and a cover layer on a substrate, performing a first-step rapid thermal annealing process to form a high-resistance nickel silicide layer, selectively etching to remove the cover layer and unreacted metal, depositing a contact etching barrier layer, and performing a second-step spike annealing process to form a low-resistance nickel silicide layer.

According to the invention, the second annealing process step and the contact etching barrier layer deposition step are sequentially exchanged, and the contact etching barrier layer is used as a protective layer, so that the spike annealing of the second step and the rapid thermal annealing of the first step can be completed on the same machine without causing additional nickel metal pollution, no new process step and equipment are required to be added, the production cost is reduced, meanwhile, the introduction of the spike annealing can effectively control the diffusion of nickel atoms, inhibit the generation of nickel silicide erosion defects, and remarkably improve the leakage current of a device.

Optionally, the substrate is monocrystalline silicon, silicon-on-insulator, stacked silicon-on-insulator, silicon-germanium-on-insulator, stacked silicon-germanium-on-insulator, or germanium-on-insulator, etc. The substrate can be selected according to actual requirements.

Optionally, the substrate is further processed prior to depositing the nickel-containing metal layer and the capping layer on the substrate by forming gate and source/drain structures of the CMOS device on the substrate, depositing a nickel silicide barrier layer, etching the barrier layer, exposing window regions where the metal layer and capping layer are deposited.

Optionally, the nickel-containing metal layer is pure nickel or an alloy of nickel and other metals.

Optionally, the covering layer is metallic titanium or titanium nitride.

Optionally, the deposition process of the nickel-containing metal layer and the capping layer is physical vapor deposition.

Optionally, the rapid thermal annealing process in the first step adopts a rapid thermal annealing furnace, wherein the process parameters are that the annealing temperature is 200-350 ℃, the annealing time is 15-45 s, and the heating and cooling rates are less than 50 ℃ per second.

Optionally, the selective etching is wet etching, and the etchant is a mixed solution of a strong oxidant and a strong acid.

Optionally, the contact etching barrier layer is silicon nitride or silicon oxynitride.

Optionally, the deposition process of the contact etching barrier layer is plasma enhanced chemical vapor deposition, and the deposition temperature is 200-350 ℃ and is matched with the rapid thermal annealing temperature of the first step.

Optionally, the spike annealing process of the second step adopts the same rapid thermal annealing furnace as the rapid thermal annealing process of the first step, wherein the process parameters are that the annealing temperature is 500-650 ℃, the heat preservation time is not needed, and the heating and cooling rate is more than 50 ℃ per second.

A second aspect of the invention provides a CMOS device fabricated on the basis of the CMOS device fabrication process described above in relation to the first aspect of the invention.

The invention has the beneficial effects that:

The contact etching barrier layer is deposited as an inherent procedure in the manufacturing process of the CMOS device, is usually carried out after the metal silicide process is completed, is used as a barrier layer for etching to form a contact hole, prevents the gate and the source/drain from being damaged by etching, and eliminates adverse effects caused by different etching heights of the gate and the source/drain. Meanwhile, different stress can be introduced into the CMOS device according to different material selections of the contact etching barrier layer, so that the carrier mobility of the device is improved. In general, the lower the deposition temperature of the contact etch stop layer, the more relaxed the texture, the less stress is introduced and the more limited the improvement in device performance. Annealing the deposited contact etch stop layer can make it denser and the introduced stress increased. The CMOS device manufacturing process provided by the invention uses the contact etching barrier layer as a protective layer through the second annealing process and the contact etching barrier layer deposition in the nickel silicide exchange process, and under the condition of not adding new process steps and equipment, on one hand, spike annealing is completed on a rapid thermal annealing machine as the second annealing process of the nickel silicide process, so that the diffusion of nickel atoms is effectively controlled, the yield and reliability of the device are improved without causing extra nickel metal pollution, and on the other hand, the contact etching barrier layer becomes compact in the spike annealing process, can introduce larger stress, and is beneficial to improving the performance of the device.

Drawings

FIG. 1 is a typical process flow diagram;

FIG. 2 is a process flow diagram of the present invention;

Fig. 3 is a schematic cross-sectional view of a CMOS device fabrication process in an embodiment of the invention. Wherein:

FIG. 3a is a schematic diagram of a CMOS device substrate provided in an embodiment of the present invention;

FIG. 3b is a schematic illustration of depositing a nickel-containing metal layer and a capping layer on a CMOS device substrate in accordance with an embodiment of the present invention;

FIG. 3c is a schematic diagram of a first rapid thermal annealing process to form a high-resistance nickel silicide layer and selectively etching away the capping layer and unreacted metal in an embodiment of the present invention;

FIG. 3d is a schematic diagram of a second step of spike annealing process to form a low resistance nickel silicide layer after depositing a contact etch stop layer in accordance with an embodiment of the present invention.

In fig. 3, the reference numerals are as follows:

The semiconductor substrate 301, the isolation structure 302, the gate dielectric layer 303, the P-type doped gate material layer 304, the N-type doped gate material layer 305, the sidewall 306, the P-type source/drain 307, the N-type source/drain 308, the nickel silicide blocking layer 309, the nickel-containing metal layer 310, the capping layer 311, the high-resistance nickel silicide layer 312, the contact etch blocking layer 313, and the low-resistance nickel silicide layer 314.

Detailed Description

The invention will be further described with reference to the drawings and the specific examples.

The drawings are for illustrative purposes only and are not to be construed as limiting the patent, and certain components of the drawings may be omitted, enlarged or reduced in order to better illustrate the present embodiments, and not to represent the actual product size, and it will be appreciated by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted. The positional relationship depicted in the drawings is for illustrative purposes only and is not to be construed as limiting the present patent.

Fig. 1 is a flow chart of a typical CMOS device fabrication process, comprising:

Step 201, providing a patterned substrate;

Step 202, depositing a nickel-containing metal layer and a cover layer on a substrate;

Step 203, performing a first rapid thermal annealing process on the structure to form a high-resistance nickel silicide layer;

Step 204, selectively etching to remove the covering layer and unreacted metal;

step 205, performing a second rapid annealing process on the structure to form a low-resistance nickel silicide layer;

At step 206, a contact etch stop layer is deposited.

Fig. 2 is a flow chart of a CMOS device manufacturing process according to the present invention, for schematically illustrating the entire manufacturing process, including:

step 101, providing a patterned substrate;

Step 102, depositing a nickel-containing metal layer and a covering layer on a substrate;

Step 103, performing a first-step rapid thermal annealing process treatment on the structure to form a high-resistance nickel silicide layer;

Step 104, selectively etching to remove the covering layer and unreacted metal;

Step 105, exchanging the sequence of the second annealing process step and the contact etching barrier layer deposition step, depositing a contact etching barrier layer, and then performing the second spike annealing process treatment on the structure to form the low-resistance nickel silicide layer.

The greatest difference between the CMOS device manufacturing process and the conventional flow is that the sequence of the second annealing process and the contact etching barrier layer deposition in the nickel silicide process is exchanged, so that the contact etching barrier layer serves as a protective layer for preventing nickel metal from polluting a cavity in the second spike annealing process treatment, and the diffusion of nickel atoms can be effectively controlled and the generation of nickel silicide defects can be inhibited under the condition that new process steps and equipment are not added.

Fig. 3a to 3d are schematic cross-sectional views of a CMOS device fabrication process in an embodiment of the invention. The following describes in detail the steps of the CMOS device manufacturing process provided in this embodiment with reference to fig. 3.

As shown in fig. 3a, in step 101, the process of providing a patterned substrate includes:

A semiconductor substrate 301 is provided which is single crystal silicon, silicon-on-insulator, stacked silicon-on-insulator, silicon-germanium-on-insulator, stacked silicon-germanium-on-insulator, or the like. An isolation structure 302 is formed in the semiconductor substrate 301. As an example, in this embodiment, the isolation structure is shallow trench isolation, which is used to isolate the substrate between the transistors, so as to prevent current leakage and mutual interference, thereby improving the performance and reliability of the device. The semiconductor substrate 301 further has various well structures formed therein, PMOS is formed on the N-well, and NMOS is formed on the P-well, which are omitted from the drawings for simplicity. A gate structure is formed on the semiconductor substrate 301, where the gate structure includes a gate dielectric layer 303, gate material layers 304 and 305, and a sidewall 306. As an example, in this embodiment, the gate dielectric layer 303 is silicon dioxide or nitrogen doped silicon dioxide, the gate material layers 304 and 305 are P-type doped polysilicon and N-type doped polysilicon, respectively, and the sidewall 306 includes a plurality of silicon dioxide layers and/or silicon nitride layers, which are omitted in the drawings for simplicity. Source/drain electrodes 307, 308 are formed in the semiconductor substrate 301 on both sides of the gate structure. The P-type source/drain 307 in the PMOS region is doped with P-type impurities, which may be ion-implanted trivalent boron, etc., and the N-type source/drain 308 in the NMOS region is doped with N-type impurities, which may be ion-implanted pentavalent arsenic, phosphorus, etc. A nickel silicide barrier layer 309 and photoresist are deposited over the substrate structure, and the barrier layer 309 is masked, exposed, and etched to expose the window region. Preferably, the nickel silicide barrier layer 309 may be a silicon dioxide layer or a stack of silicon dioxide and silicon nitride.

As shown in fig. 3b, a nickel-containing metal layer 310 and a capping layer 311 are deposited on the patterned substrate in step 102. The capping layer 311 may prevent rapid flow of nickel atoms during annealing. The nickel-containing metal layer 310 is pure nickel or an alloy of nickel and other metals, the covering layer 311 is metallic titanium or titanium nitride, and the deposition process of the nickel-containing metal layer 310 and the covering layer 311 is physical vapor deposition. Preferably, the nickel-containing metal layer 310 may be an alloy of nickel and platinum or a stack of nickel and platinum, with a platinum content of 5% -10%.

As shown in fig. 3c, in steps 103 and 104, the structure is subjected to a first rapid thermal annealing process to form a high resistance nickel silicide layer 312, and the capping layer and unreacted metal are selectively etched away. The rapid thermal annealing process in the first step adopts a rapid thermal annealing furnace, wherein the process parameters are that the annealing temperature is 200-350 ℃, the annealing time is 15-45 s, and the heating and cooling rates are less than 50 ℃ per second. The selective etching is wet etching, and the etchant is a mixed solution of a strong oxidant and a strong acid. Preferably, the etchant may be a mixed solution of hydrogen peroxide and sulfuric acid and/or hydrochloric acid, etc.

As shown in fig. 3d, in step 105, the order of the second annealing process step and the deposition step of the contact etch stop layer 313 is exchanged, the contact etch stop layer 313 is deposited first, and then the spike annealing process treatment is performed on the above structure to form the low-resistance nickel silicide layer 314. The contact etch stop layer 313 is silicon nitride or silicon oxynitride, the deposition process is plasma enhanced chemical vapor deposition, the deposition temperature is 200 ℃ to 350 ℃, and the deposition temperature is matched with the rapid thermal annealing temperature of the first step. The peak annealing process of the second step adopts the same rapid thermal annealing furnace as the rapid thermal annealing process of the first step, and the process parameters are that the annealing temperature is 500-650 ℃, the heat preservation time is not needed, and the temperature rising and reducing rate is more than 50 ℃ per second. The shorter time scale of spike annealing can effectively control the diffusion of nickel atoms, reduce the occurrence of nickel silicide defects, and simultaneously, the contact etch barrier 313 as a protection for the tool chamber from nickel metal contamination also rearranges more tightly during the annealing process, thereby applying greater stress to the CMOS device.

After the process flow is finished, the standard CMOS process is continued, and the process of forming the contact hole, the subsequent copper metal interconnection process and the like are carried out, so that the manufacture of the complete CMOS device can be finished.

According to the embodiment of the invention, the CMOS device manufacturing process is provided, the contact etching barrier layer is used as a protective layer through the second annealing process and the contact etching barrier layer in the nickel silicide exchange process, and the spike annealing is introduced to serve as the second annealing process of the nickel silicide process under the condition that new process steps and equipment are not added, so that abnormal diffusion of nickel atoms is inhibited, the yield and reliability of the device are improved, and no extra nickel metal pollution is caused.

The present application has been illustrated by the above-described embodiments, but it should be understood that the above-described embodiments are for purposes of illustration and description only and are not intended to limit the application to the embodiments described. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.

It is to be understood that the application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims

1. A CMOS device manufacturing process, characterized by comprising:

A nickel-containing metal layer and a capping layer are deposited on the substrate, and a first step of rapid thermal annealing process is performed to form a high-resistance nickel silicide layer;

After the capping layer and unreacted metal are removed by selective etching, a contact etching barrier layer is first deposited, and then a second step of spike annealing process is performed to form a low-resistance nickel silicide layer.

2. The CMOS device manufacturing process according to claim 1, characterized in that the substrate is single crystal silicon, silicon on insulator, stacked silicon on insulator, silicon germanium on insulator, stacked germanium silicon on insulator or germanium on insulator.

3. The CMOS device manufacturing process according to claim 1 or 2, characterized in that the substrate is further treated as follows before depositing the nickel-containing metal layer and the covering layer on the substrate:

The gate and source/drain structures of the CMOS device are formed on the substrate, a nickel silicide barrier layer is deposited, and the barrier layer is etched to expose the window area of the deposited metal layer and the cover layer.

4 . The CMOS device manufacturing process according to claim 1 , wherein the nickel-containing metal layer is pure nickel or an alloy of nickel and other metals.

5 . The CMOS device manufacturing process according to claim 1 , wherein the cover layer is metal titanium or titanium nitride.

6 . The CMOS device manufacturing process according to claim 1 , 2 or 4 , characterized in that the deposition process of the nickel-containing metal layer and the covering layer is physical vapor deposition.

7. The CMOS device manufacturing process according to claim 1 is characterized in that the rapid thermal annealing process in the first step adopts a rapid thermal annealing furnace, and the process parameters are: annealing temperature is 200°C-350°C, annealing time is 15s-45s, and heating and cooling rates are less than 50°C/s.

8 . The CMOS device manufacturing process according to claim 1 , wherein the selective etching is wet etching, and the etchant is a mixed solution of a strong oxidant and a strong acid.

9 . The CMOS device manufacturing process according to claim 1 , wherein the contact etching barrier layer is silicon nitride or silicon oxynitride.

10. The CMOS device manufacturing process according to claim 1 or 7, characterized in that the deposition process of the contact etch barrier layer is plasma enhanced chemical vapor deposition, and the deposition temperature is 200°C-350°C, which matches the rapid thermal annealing temperature of the first step.

11. The CMOS device manufacturing process according to claim 1 is characterized in that the spike annealing process in the second step adopts the same rapid thermal annealing furnace as the rapid thermal annealing process in the first step, and the process parameters are: annealing temperature is 500°C-650°C, there is no holding time, and the heating and cooling rates are greater than 50°C/s.

12. A CMOS device, characterized in that the CMOS device is manufactured based on the CMOS device manufacturing process according to any one of claims 1 to 11.