CN119065901A

CN119065901A - A LPCAMM memory module testing circuit and method

Info

Publication number: CN119065901A
Application number: CN202411057623.2A
Authority: CN
Inventors: 达龙科; 梁展豪; 曹胜; 马杰伟
Original assignee: Shenzhen Yixin Information Technology Co ltd
Current assignee: Shenzhen Yixin Information Technology Co ltd
Priority date: 2024-08-02
Filing date: 2024-08-02
Publication date: 2024-12-03

Abstract

The present invention discloses a LPCAMM memory module test circuit and method, the test circuit includes: a main control module, which is used to receive instructions from a PC host computer and output different drive control signals; an interface module, which is connected to the main control module, includes a plurality of 64P channel boards, and is connected to a product to be tested through a probe EVB board to realize signal transmission and testing; a communication module, which is connected to the main control module, is used to communicate with the PC host computer, receive test instructions and send test results; a signal control module, which is connected to the main control module, is used to control the power-on and power-off operations of the product to be tested; a power supply module, which is respectively connected to the main control module and the signal control module, is used to supply power to the main control module and the product to be tested. Compared with the prior art, the present invention designs a test circuit and method for existing test equipment to test the LPCAMM memory module, the test circuit and method simultaneously support multiple performance tests and the test steps are simple, which not only reduces the test cost but also improves the test efficiency.

Description

LPCAMM memory module testing circuit and method

Technical Field

The present invention relates to the field of performance testing technologies for memory modules, and in particular, to a LPCAMM memory module testing circuit and method.

Background

With the continuous progress of technology, new memory modules such as LPCAMM are gradually becoming more and more popular. However, in the current test equipment market, market awareness and occupancy are relatively low due to their nature as emerging products, which directly results in the scarcity and high price of the associated test equipment.

At present, aiming at the problems of scarcity and high price of related test equipment, novel test equipment aiming at a memory module LPCAMM is developed in the existing market. However, it has a problem that the test function is single, the test step is complicated, and thus the test cost is increased.

Disclosure of Invention

The invention aims to provide a LPCAMM memory module testing circuit and a LPCAMM memory module testing method, and aims to solve the problems that the testing function is single, the testing steps are complicated and the testing cost is increased in the novel testing equipment of the existing memory module LPCAMM.

In order to solve the technical problems, the aim of the invention is realized by the following technical scheme:

a first aspect of an embodiment of the present application provides a LPCAMM memory module test circuit, including:

the main control module is used for receiving the instruction of the PC upper computer and outputting different driving control signals;

The interface module is connected with the main control module and comprises a plurality of 64P channel boards, and is connected with a product to be tested through the probe EVB board to realize signal transmission and test;

the communication module is connected with the main control module and is used for communicating with the PC upper computer, receiving the test instruction and sending the test result;

the signal control module is connected with the main control module and used for controlling the power-on and power-off operation of the product to be tested;

The power supply module is respectively connected with the main control module and the signal control module and is used for supplying power to the main control module and the product to be tested.

In one possible implementation manner, the power supply module comprises a first power supply module and a second power supply module, the first power supply module comprises a first switch power supply and a travel switch, a VCC port of the first switch power supply is connected with a +5v port of the main control module, a ground end of the first switch power supply is connected with a first ground port of the main control module, one end of the travel switch is connected with a ground end of the first switch power supply, and the other end of the travel switch is connected with a normally open contact port of the main control module;

The second power supply module comprises a second switching power supply, the VCC port of the second switching power supply is connected with the VCC port of the signal control module, and the grounding end of the second switching power supply is connected with the grounding port of the signal control module.

In one possible implementation manner, the signal control module is an optocoupler relay board, a ground port of the signal control module is connected with a second ground port of the main control module, a Ctrl port of the signal control module is connected with an up_ctrl port of the main control module, one end of a normally open contact interface of the signal control module is connected with an output pin, and a COM port of the signal control module is connected with a power input pin.

In one possible implementation manner, the main control module includes a plurality of input ports and a tooling indicator light interface, wherein the input ports are connected with the 64P channel plate, and the tooling indicator light interface is connected with the tooling indicator light.

A second aspect of the embodiment of the present application provides a method for testing a LPCAMM memory module, including:

the control main control module performs test operation on the LPCAMM memory module according to a preset test flow to obtain test data;

judging a test result according to the test data and displaying the test result on a PC (personal computer);

And generating a test log according to the test result and storing the test log.

In one possible implementation manner, the step of controlling the main control module to perform a test operation on the LPCAMM memory module according to a preset test flow to obtain test data includes:

Controlling the main control module to input preset current to the PIN of the LPCAMM memory module and acquiring the voltage value and/or the voltage value of the PIN of the LPCAMM memory module;

The main control module is controlled to acquire temperature data and/or temperature data output by a temperature sensor of the LPCAMM memory module;

The main control module is controlled to acquire voltage data and/or voltage data of a PMIC (permanent magnet synchronous motor) register of the LPCAMM memory module;

and controlling the main control module to write preset SN information into the SPD of the LPCAMM memory module.

In one possible implementation manner, the test operation includes an open circuit test and a short circuit test, and the step of judging a test result according to the test data and displaying the test result on the PC host computer includes:

respectively comparing the voltage value of the PIN PIN of the LPCAMM memory module with a first preset voltage threshold value and a second preset voltage threshold value;

Judging whether the voltage value of the PIN of the LPCAMM memory module is larger than a first preset voltage threshold or smaller than a second preset voltage threshold;

if the voltage value of the PIN PIN of the LPCAMM memory module is larger than a first preset voltage threshold value, judging that the open circuit test fails and displaying the open circuit test on a PC upper computer;

If the voltage value of the PIN PIN of the LPCAMM memory module is not greater than a first preset voltage threshold, judging that the open circuit test is passed and displaying the open circuit test on a PC upper computer;

If the voltage value of the PIN PIN of the LPCAMM memory module is smaller than a second preset voltage threshold, judging that the short circuit test fails and displaying the short circuit test on a PC upper computer;

if the voltage value of the PIN PIN of the LPCAMM memory module is not smaller than a second preset voltage threshold, judging that the short circuit test is passed and displaying the short circuit test on a PC upper computer.

In one possible implementation manner, the testing operation includes a temperature test, and the step of judging a test result according to the test data and displaying the test result on the PC host computer includes:

Reading the temperature data and comparing the temperature data with a preset temperature data range;

Judging whether the temperature data are in the preset temperature data range or not;

If the temperature data is in the preset temperature data range, judging that the temperature test is passed and displaying the temperature test on a PC (personal computer) upper computer;

If the temperature data is not in the preset temperature data range, judging that the temperature test is not passed and displaying the temperature test on a PC (personal computer) upper computer.

In one possible implementation manner, the test operation includes a PMIC output voltage test, and the step of judging a test result according to the test data and displaying the test result on a PC host computer includes:

comparing the voltage data with a preset voltage data threshold value;

judging whether the voltage data is equal to the preset voltage data threshold value or not;

if the voltage data is equal to the preset voltage data threshold value, judging that the PMIC test is passed and displaying the PMIC test on a PC upper computer;

if the voltage data is not equal to the preset voltage data threshold, judging that the PMIC test fails and displaying the PMIC test on a PC (personal computer).

In one possible implementation manner, the test operation includes SPD burn test, and the step of judging a test result according to the test data and displaying the test result on a PC host computer includes:

scanning bar code information of the LPCAMM memory module and extracting the bar code information;

the main control module is controlled to burn the bar code information to the SPD of the LPCAMM memory module;

reading SN information burnt into the SPD and comparing the SN information with the bar code information;

if the SN information is consistent with the bar code information, judging that the SPD burning test passes and displaying the SPD burning test on a PC upper computer;

If the SN information is inconsistent with the bar code information, judging that the SPD burning test fails and displaying the SPD burning test on a PC.

Compared with the prior art, the invention provides a LPCAMM memory module testing circuit aiming at the existing LPCAMM novel testing equipment, which consists of a main control module, an interface module, a communication module, a signal control module and a power module, realizes automatic testing, flexible expansibility, real-time communication and feedback, accurate control of power on and off and stable and reliable power supply, and also designs a LPCAMM memory module testing method based on the testing circuit, wherein the method comprises the steps of presetting a testing program in a PC upper computer and setting the testing program in a preset position, controlling the main control module to execute testing operation on the LPCAMM memory module to obtain testing data, judging a testing result according to the testing data, displaying the testing result on the PC upper computer, generating a testing log according to the testing result and storing the testing log in the preset position. Compared with the prior art, the invention designs the test circuit and the test method aiming at the existing test equipment to test the LPCAMM memory module, and the test circuit and the test method simultaneously support various performance tests, have simple test steps, reduce test cost and improve test efficiency.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic block diagram of a LPCAMM memory module test circuit according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a LPCAMM memory module test circuit according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a 64P channel board of LPCAMM memory module test circuits provided in an embodiment of the present invention;

fig. 4 is a partial packet PIN diagram of LPCAMM memory modules provided in an embodiment of the present invention;

FIG. 5 is a block diagram of another portion of a LPCAMM memory module according to one embodiment of the present invention;

FIG. 6 is a flowchart illustrating a first embodiment of a method for testing LPCAMM memory modules according to the present invention;

FIG. 7 is a second schematic sub-flowchart of a LPCAMM memory module testing method according to an embodiment of the present invention;

FIG. 8 is a third sub-flowchart of a LPCAMM memory module testing method according to an embodiment of the present invention;

FIG. 9 is a schematic diagram of a sub-flowchart of a LPCAMM memory module testing method according to an embodiment of the present invention;

FIG. 10 is a schematic diagram of a sub-flowchart of a LPCAMM memory module testing method according to an embodiment of the present invention;

FIG. 11 is a schematic diagram showing a sub-process of a LPCAMM memory module testing method according to an embodiment of the present invention.

Reference numerals:

10. The device comprises a main control module, an interface module, a communication module, a signal control module, a power module, a first power module, a second power module and a power module.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It should be understood that the terms "comprises" and "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be further understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.

Referring to fig. 1 to 11, referring specifically to fig. 1, an embodiment of the invention provides a LPCAMM memory module testing circuit, which comprises a main control module 10 for receiving an instruction of a PC host and outputting different driving control signals, an interface module 20 connected to the main control module 10 and including a plurality of 64P channel boards, a communication module 30 connected to the main control module 10 for communicating with the PC host, receiving the testing instruction and sending the testing result, a signal control module 40 connected to the main control module 10 for controlling the power-on and power-off operations of the product to be tested, and a power module 50 connected to the main control module 10 and the signal control module 40 for supplying power to the main control module 10 and the product to be tested, respectively.

Specifically, the main control module 10 is a core of the whole test circuit, is responsible for receiving instructions from the PC host computer, and outputs corresponding driving control signals according to the instructions, where the signals are used for controlling various links in the test process, such as signal transmission, powering on and off of a product to be tested, and the main control module 10 can be implemented by using a high-performance microprocessor or microcontroller, such as an ARM, a DSP, and the like, and has strong computing power and rich peripheral interfaces. The interface module 20 is connected to the main control module 10, and is used for realizing signal transmission and test between the test circuit and the product to be tested, and the module comprises a plurality of 64P (64 pin) channel boards, wherein the channel boards are connected with the product to be tested through the probe EVB board, so that the accurate transmission of signals and the reliability of test are ensured. Each 64P channel board is designed with an interface and a signal line matched with the product to be tested, and the probe EVB board is customized according to the specific layout and pin arrangement of the product to be tested so as to ensure the accuracy and flexibility of the test. The communication module 30 is connected to the main control module 10, and is responsible for communicating with the PC host computer, receiving the test command, and sending the test result. The module supports various communication protocols, such as USB, ethernet, etc., to meet the requirements of different test scenes. The signal control module 40 is connected to the main control module 10 and the second power module 502, and is used for controlling the power-on and power-off operation of the product to be tested. In the testing process, the power supply of the product to be tested is controlled according to the requirements so as to simulate different working states and detect the performance of the product. The signal control module 40 may be implemented by using a switching element such as a relay or a MOSFET, and controls the on/off of the power supply by receiving a control signal from the main control module 10. The power module 50 includes a main power supply and a second power supply, wherein the main power supply supplies power to the main control module 10 and other auxiliary circuits, and the second power supply supplies power to the product to be tested through the signal control module 40.

As shown in fig. 1-2, the power module 50 includes a first power module 501 and a second power module 502, the first power module 501 includes a first switching power supply and a travel switch, a VCC port of the first switching power supply is connected to a +5v port of the main control module 10, a ground terminal of the first switching power supply is connected to a first ground port of the main control module 10, one end of the travel switch is connected to a ground terminal of the first switching power supply, and the other end is connected to a normally open contact port of the main control module 10, the second power module 502 includes a second switching power supply, a VCC port of the second switching power supply is connected to a VCC port of the signal control module 40, and a ground terminal of the second switching power supply is connected to a ground port of the signal control module 40.

As shown in fig. 2, the communication module 30 is a FT232 serial port board, the FT232 serial port board communicates with the PC host computer, the VCC end on the FT232 serial port board is not powered on, the TX end of the FT232 serial port board is connected with the RXD port of the main control module 10, the RX end of the FT232 serial port board is connected with the TXD port of the main control module 10, and the GND end of the FT232 serial port board is connected with the SET port of the main control module 10. The communication module 30 is responsible for communication between the main control module 10 and the PC upper computer, receives a test instruction from the PC upper computer, and sends a test result or state information in a test process back to the PC upper computer, so that a tester can monitor the test progress and result on the PC upper computer in real time, and control and adjust the test process.

As shown in fig. 1, the signal control module 40 is an optocoupler relay board, the ground port of the signal control module 40 is connected with the second ground port of the main control module 10, the Ctrl port of the signal control module 40 is connected with the up_ctrl port of the main control module 10, one end of the normally open contact interface of the signal control module 40 is connected with an output pin, and the COM port of the signal control module 40 is connected with a power input pin.

Specifically, the working principle of the optocoupler relay is based on the photoelectric effect, and the optocoupler relay converts an electric signal into an optical signal and then converts the optical signal back into an electric signal, so that the electric isolation of the circuit is realized. In the optocoupler relay board, when the Ctrl pin receives a control signal (e.g., high or low), the internal optocoupler is activated or deactivated, thereby changing the state of the NO (normally open) pin (from open to closed or from closed to open, depending on the circuit design). And the NO pin is connected with the OUTPUT pin, and the OUTPUT pin is connected to the circuit of the product to be tested, and when the state of the NO pin is changed, the on-off of the circuit of the product to be tested is controlled.

In this embodiment, when the main control module 10 completes the open-short circuit test, the up_ctrl port of the main control module 10 sends out a control signal, the Ctrl pin receives the control signal to close the NO pin, the second power module 50250 is connected to the optocoupler relay, and the product to be tested is powered on at this time, so as to perform other tests, such as a PMIC test, a TS test, and the like.

As shown in fig. 2-3, the main control module 10 includes a plurality of input ports and a tooling indicator light interface, the input ports are connected with the 64P channel board, and the tooling indicator light interface is connected with the tooling indicator light.

Specifically, because there is the difference in the PIN resistances of LPCAMM memory modules, the embodiment adopts a grouping test mode, classifies PINs with close resistances into one group, and totally divides into six groups to perform open-short circuit test, meanwhile, the number of 64P channel boards is also taken to be six, and the six 64P channel boards are connected with a product to be tested through a probe EVB board, so that each group of PINs on the product to be tested corresponds to each 64P channel board one by one, the master control module 10 is convenient for performing the open-short circuit test on each group of PINs, and the tooling indicator lamp comprises OK and NG, when the tooling indicator lamp OK is on, the test result at the moment is indicated to be passed, and when the tooling indicator lamp NG is on, the test result at the moment is indicated to be failed.

The working principle of the test circuit provided by the embodiment is that the test device is electrified, a product to be tested is placed into the test device, a quick clamp on the test device is pressed down, a travel switch K1 is conducted, an NO port on the main control module 10 is pulled down to enter the test, the main control module 10 is communicated with a PC upper computer to send and receive instructions, a U2 control board starts to work to perform open-short circuit test, the test is completed, an UP_CTRL port output signal U3 on the main control module 10 is conducted, the product to be tested is electrified to perform other tests, the test is completed, a test result is output, a PC upper computer displays the result, and a tool indicator lamp OK or NG is lightened at the moment.

Referring to fig. 6 to 11, and specifically referring to fig. 6, an embodiment of the present invention further provides a LPCAMM memory module testing method, including:

s110, controlling the main control module 10 to execute test operation on the LPCAMM memory module according to a preset test flow to obtain test data;

S120, judging a test result according to the test data and displaying the test result on the PC;

s130, generating a test log according to the test result and storing the test log.

Specifically, the compiled Test program is compiled and packaged into an executable file, and then the executable file is placed in a preset folder of the PC upper computer through a file manager or a command line tool, for example, "C: \ LPCAMM _test\". This step ensures that the test program can be easily found and executed by the system or test script in subsequent operations. The LPCAMM memory module is connected to the main control module 10 by using a 64P channel board, a test instruction is sent to the main control module 10 by a test program on a PC upper computer, and after the main control module 10 receives the instruction, a series of tests, such as an electrical performance test, SPD burning and the like, are performed on the LPCAMM memory module according to a preset test flow so as to acquire detailed test data. The main control module 10 transmits all key data generated in the testing process back to the PC upper computer in real time, and stores the key data in a designated memory area or file for subsequent analysis. After the test program receives the test data, the data is processed and analyzed according to a preset algorithm or logic to evaluate whether the performance of the LPCAMM memory module meets the expected standard. The analysis results (including whether the test passes, specific performance indexes, error details and the like) are displayed to the user on a display screen of the PC upper computer in the form of a graphical interface or a text report. After the test program completes all the test tasks, a detailed test log is automatically generated according to the test results. And storing the generated Test log in a preset position of a PC upper computer in the form of a text file, an Excel table or a database record and the like, for example, a' C: \ LPCAMM _test\ Logs \folder, and ensuring that the log file name has a time stamp or a unique identifier so as to facilitate subsequent searching and management.

As shown in fig. 7, in a more specific embodiment, performing step S110 further specifically includes performing step S111:

s111, the control main control module 10 inputs preset current to the PIN of the LPCAMM memory module and obtains the voltage value of the PIN of the LPCAMM memory module and/or the temperature data output by the temperature sensor of the LPCAMM memory module, the control main control module 10 obtains the voltage data of the PMIC register of the LPCAMM memory module and/or the preset SN information written into the SPD of the LPCAMM memory module by the control main control module 10.

Specifically, in order to detect whether each group of PIN in the LPCAMM memory module has an open circuit or a short circuit fault, the PC upper computer controls the main control module 10 to drive the corresponding current output circuit to input a preset current to each group of PIN of the 64P channel board through the issued test instruction and obtain the voltage value of each group of PIN. The preset current is used for enabling the PIN of the 64P channel plate to generate voltage, and the PC upper computer can set the preset current according to the test requirement. The main control module 10 inputs preset current to each group of PIN PINs of the 64P channel board according to the test instruction issued by the upper computer, each group of PIN PINs of the 64P channel board can generate corresponding voltage, and the main control module 10 detects the voltage value of each group of PIN PINs of the 64P channel board through the voltage detection circuit and sends the voltage value to the upper computer. After the upper computer obtains the voltage value of the PIN PINs of the 64P channel plate, the voltage value can be analyzed and processed, the open-short circuit state of each group of PIN PINs of the LPCAMM memory module is obtained, and whether the electrical connection of each group of PIN PINs of the LPCAMM memory module is normal or not is judged.

Specifically, the acquiring LPCAMM temperature data output by the temperature sensor of the memory module mainly includes sending an appropriate command to the LPCAMM memory module through the main control module 10 or accessing a specific register to identify and locate the temperature sensor inside the memory module, checking the response of the memory module to the command, ensuring that the temperature sensor is correctly identified and ready to send temperature data, sending a read request to the register of the temperature sensor through the main control module 10 to acquire the current temperature data, receiving the data returned from the temperature sensor, analyzing the data into a readable temperature value by using an appropriate algorithm or software tool, recording the read temperature data in a test report, and displaying the read temperature data on an interface of the test system in real time.

Specifically, the PMIC connectivity test is to read a voltage value in a PMIC register to determine whether the PMIC connectivity is good, and the steps thereof are mainly divided into reading the PMIC register, waiting for a PMIC response and returning the data to the data main control module 10 of the register to receive response data from the PMIC, analyzing the data to obtain a voltage value, generally converting the received original data into a voltage unit (such as volts), displaying the voltage data on a user interface of test software, analyzing the obtained voltage data, and determining whether the connectivity of the PMIC is good. Optionally, the data is recorded into a log file or database for subsequent analysis.

Specifically, the SPD is an EEPROM chip above LPCAMM, and is used for storing related information of the LPCAMM memory, where the SPD memory mainly includes related information (timing, specification, capacity, voltage, etc.) of the LPCAMM memory. In order to achieve the consistency of the SN information in the SPD and the bar code, the device scans the two-dimensional code on the LPCAMM module through the bar scanning gun, extracts the related SN information to be written in through the two-dimensional code, and then burns the related SN information into the SPD of the LPCAMM module.

As shown in fig. 8, the test operation includes an open circuit test and a short circuit test, and step S120 of judging a test result according to the test data and displaying it on the PC host computer includes steps S1201 to S1206.

S1201, respectively comparing the voltage value of the PIN PIN of the LPCAMM memory module with a first preset voltage threshold value and a second preset voltage threshold value;

S1202, judging whether the voltage value of a PIN PIN of the LPCAMM memory module is larger than a first preset voltage threshold or smaller than a second preset voltage threshold;

s1203, if the voltage value of the PIN PIN of the LPCAMM memory module is larger than a first preset voltage threshold value, judging that the open circuit test fails and displaying the open circuit test on the PC upper computer;

s1204, if the voltage value of the PIN PIN of the LPCAMM memory module is not greater than a first preset voltage threshold value, judging that the open circuit test is passed and displaying the open circuit test on a PC upper computer;

s1205, if the voltage value of the PIN PIN of the LPCAMM memory module is smaller than a second preset voltage threshold, judging that the short circuit test fails and displaying the short circuit test on the PC upper computer;

s1206, if the voltage value of the PIN of the LPCAMM memory module is not less than the second preset voltage threshold, judging that the short circuit test is passed and displaying the short circuit test on the PC upper computer.

Specifically, the upper computer compares the obtained voltage values of each group of PIN of the LPCAMM memory module with a first preset voltage threshold to determine whether open circuit faults exist in each group of PIN of the LPCAMM memory module, and compares the obtained voltage values with a second preset voltage threshold to determine whether short circuit faults exist in each group of PIN of the LPCAMM memory module. During testing, the LPCAMM memory module is required to be ensured to be installed correctly and connected to a testing system, the testing system comprises voltage measuring equipment and a PC upper computer, testing software is installed and configured on the PC upper computer, the software has the functions of reading voltage values, logic judgment, result display and the like, and a first preset voltage threshold value (for open circuit testing) and a second preset voltage threshold value (for short circuit testing) are set in the testing software according to the technical specification and testing requirements of the LPCAMM memory module. The test system obtains the voltage value of each group of PIN PINs of the LPCAMM memory module through the voltage measurement equipment, compares the voltage value of each group of PIN PINs with a first preset voltage threshold value and a second preset voltage threshold value respectively, judges whether the voltage value of each group of PIN PINs is larger than the first preset voltage threshold value or smaller than the second preset voltage threshold value, if the voltage value is larger than the first preset voltage threshold value, the test software judges that the open test of the PIN PINs fails, generates a corresponding test result, displays the information that the open test fails on the PC upper computer, including the number of the PIN PINs, the voltage value, the test result and the like, and if the voltage value is not larger than the first preset voltage threshold value, the test software judges that the open test of the PIN PINs passes, generates a corresponding test result and displays the information that the open test passes on the PC upper computer. If the voltage value is not less than the second preset voltage threshold, the test software judges that the PIN PIN short circuit test is passed, generates a corresponding test result, displays the information that the short circuit test is not passed on the PC upper computer, and also comprises the PIN PIN number, the voltage value and the test result.

As shown in fig. 9, the test operation includes a temperature test, and step S120 of judging a test result according to the test data and displaying it on the PC host computer includes steps S1207 to S12010.

S1207, reading temperature data and comparing the temperature data with a preset temperature data range;

s1208, judging whether the temperature data is in a preset temperature data range;

S1209, if the temperature data is within the preset temperature data range, judging that the temperature test is passed and displaying the temperature test on the PC upper computer;

S12010, if the temperature data is not in the preset temperature data range, judging that the temperature test is not passed and displaying the temperature test on the PC.

Specifically, temperature data of tested equipment are collected in real time through a temperature test system by using a temperature sensor, the collected temperature data are compared with a preset temperature data range, the preset temperature data range comprises the lowest acceptable temperature and the highest acceptable temperature, whether the current temperature data are located in the preset temperature data range is judged according to a comparison result, if the temperature data are located between the lowest acceptable temperature and the highest acceptable temperature, the temperature data are considered to be normal, if the temperature data are located in the preset temperature data range, test software judges that the temperature test is passed, prompt information of PASS is displayed on a PC upper computer, if the temperature data are not located in the preset temperature data range, test software judges that the temperature test is not passed, prompt information of FAIL is displayed on the PC upper computer, and specific conditions that the current temperature value exceeds the preset range, such as 'temperature is too high' or 'temperature too low', are clearly indicated.

As shown in fig. 10, the test operation includes a PMIC output voltage test, and step S120 of determining a test result according to the test data and displaying the test result on the PC host computer includes steps S12011 to S12014.

S12011, comparing the voltage data with a preset voltage data threshold value;

s12012, judging whether the voltage data is equal to a preset voltage data threshold value;

S12013, if the voltage data is equal to the preset voltage data threshold, judging that the PMIC test is passed and displaying the PMIC test on the PC upper computer;

S12014, if the voltage data is not equal to the preset voltage data threshold, judging that the PMIC test is not passed and displaying the PMIC test on the PC.

Specifically, the output voltage of the PMIC is measured in real time by using a voltage measurement device, and the measurement result is transmitted to a data acquisition module, and the data acquisition module compares the acquired voltage data with a voltage data threshold preset in software, wherein the preset voltage data threshold generally comprises one or more specific voltage values or voltage ranges, and depends on specifications and requirements of the PMIC. Judging whether the acquired voltage data is equal to a preset voltage data threshold value or not according to a comparison result, if the voltage data is equal to the preset voltage data threshold value, judging that the PMIC output voltage test passes by test software, displaying a prompt message of PASS on a PC upper computer and comprising the current voltage value, the preset voltage data threshold value, test time and other detailed information, and if the voltage data is not equal to the preset voltage data threshold value, judging that the PMIC output voltage test FAILs by test software, displaying a prompt message of FAIL on the PC upper computer, and clearly indicating the difference between the current voltage value and the preset voltage data threshold value and the current voltage value and the preset voltage data threshold value.

As shown in fig. 11, the test operation includes SPD burn test, and step S1230 of determining a test result according to the test data and displaying the test result on the PC host computer includes steps S12015-S12019.

S12015, scanning LPCAMM bar code information of the memory module and extracting the bar code information;

s12016, controlling the main control module 10 to burn bar code information to the SPD of the LPCAMM memory module;

S12017, reading SN information burnt into the SPD and comparing the SN information with bar code information;

s12018, if the SN information is consistent with the bar code information, judging that the SPD burning test passes and displaying the SPD burning test on a PC upper computer;

s12019, if the SN information is inconsistent with the bar code information, judging that the SPD burning test is not passed and displaying the SPD burning test on the PC.

Specifically, in this embodiment, a barcode scanner is used to scan the barcode of the LPCAMM memory module, test software receives and extracts barcode information, and typically includes key information such as a product Serial Number (SN), the test software sends a burning instruction to the SPD of the LPCAMM memory module through the main control module 10, the main control module 10 burns the extracted barcode information to a specified position of the SPD, waits for the completion of burning, confirms no error prompt, uses an SPD reading device to read the burnt SN information from the SPD of the LPCAMM memory module, the test software compares the read SN information with the barcode information extracted in step S13015, if the read SN information is completely consistent with the barcode information, the test software determines that the SPD burning test passes, displays a prompting message of "PASS" on the PC host computer, if the read SN information is inconsistent with the barcode information, the test software determines that the SPD burning test FAILs, displays a prompting message of "FAIL" on the PC host computer, and prompts a specific error cause, such as "SN information mismatch".

While the application has been described with reference to certain preferred embodiments, it will be understood by those skilled in the art that various changes and substitutions of equivalents may be made and equivalents will be apparent to those skilled in the art without departing from the scope of the application. Therefore, the protection scope of the application is subject to the protection scope of the claims.

Claims

1. A LPCAMM memory module test circuit, comprising:

2. The LPCAMM memory module test circuit of claim 1, wherein the power supply module includes a first power supply module and a second power supply module, the first power supply module includes a first switching power supply and a travel switch, a VCC port of the first switching power supply is connected to a +5v port of the main control module, a ground terminal of the first switching power supply is connected to a first ground port of the main control module, one end of the travel switch is connected to a ground terminal of the first switching power supply, and the other end is connected to a normally open contact port of the main control module;

3. The LPCAMM memory module testing circuit of claim 1, wherein said signal control module is an optocoupler relay board, a ground port of said signal control module is connected to said second ground port of said master control module, a Ctrl port of said signal control module is connected to an up_ctrl port of said master control module, an output pin is connected to one end of a normally open contact interface of said signal control module, and a COM port of said signal control module is connected to a power input pin.

4. The LPCAMM memory module test circuit of claim 1, wherein the main control module includes a plurality of input ports and a tooling indicator light interface, the input ports are connected with the 64P channel board, and the tooling indicator light interface is connected with the tooling indicator light.

5. A LPCAMM memory module test method, comprising:

6. The method for testing a LPCAMM memory module according to claim 5, wherein the step of controlling the main control module to perform a test operation on the LPCAMM memory module according to a preset test flow to obtain test data includes:

7. The LPCAMM memory module testing method of claim 6, wherein said testing includes open circuit testing and short circuit testing, said determining a test result based on said test data and displaying the test result on a PC host, comprising:

8. The LPCAMM memory module testing method of claim 6, wherein said testing includes temperature testing, said determining a test result based on said test data and displaying said test result on a PC host, comprising:

9. The LPCAMM memory module testing method of claim 6, wherein said testing includes PMIC output voltage testing, said determining a test result based on said test data and displaying said test result on a PC host, comprising:

comparing the voltage data with a preset voltage data threshold value;

10. The LPCAMM memory module testing method of claim 6, wherein said testing includes SPD burn-in testing, said determining test results based on said test data and displaying said test results on a PC host, comprising: