CN119054089A - System and method for a wavelength infrared (MWIR) photodetector in hybrid PIN PbSe - Google Patents

Abstract

Methods and systems for photodetectors employing hybrid PIN or PN lead selenide (PbSe) junctions are provided. In some examples, the PbSe junction can include one or more semiconductor layers, including an n-type layer, an n+ type layer, a p(i) type layer, and/or a p+ type layer, as a non-limiting list of examples. Photodetectors employing PbSe PIN or PN junctions are produced. Methods for preparing photosensitive PbSe semiconductor layers for detecting electromagnetic energy (e.g., mid-wavelength infrared (MWIR)) are also disclosed.

Description

System and method for a wavelength infrared (MWIR) photodetector in hybrid PIN PbSe

Cross Reference to Related Applications

The present application hereby claims the priority and benefit of U.S. provisional application serial No. 63/333,616 entitled "SYSTEMS AND METHODS FOR HYBRID PIN PbSe MID-WAVELENGTH INFRARED (MWIR) PHOTODETECTORS [ systems and methods for Mixing Wavelength Infrared (MWIR) photodetectors in PIN PbSe ]" filed on month 22 of 2023. U.S. provisional application Ser. No. 63/333,616 is incorporated herein by reference in its entirety for all purposes.

Background

Photosensitive materials are used as detectors in many applications. However, conventional techniques may be expensive and complex to produce and may have a narrow absorption range. It is therefore desirable to produce photosensitive materials with improved sensitivity by a cheaper and less complex process.

Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present disclosure as set forth in the remainder of the present application with reference to the drawings.

Disclosure of Invention

Systems and/or methods for photodetectors employing hybrid PIN or PN PbSe junctions are provided. In some examples, the junction may include one or more PbSe semiconductor layers including an n-type layer, an n+ -type layer, a p (i) -type layer, and/or a p+ -type layer, as a non-limiting example list.

These and various other advantages, aspects and novel features of the present disclosure, as well as details of illustrated embodiments of the present disclosure, will be more fully understood from the following description and drawings.

Drawings

Fig. 1A illustrates a partial top view of a photodiode according to an example embodiment of the present disclosure.

Fig. 1B illustrates a cross-sectional view of an example lead selenide (PbSe) photodetector, according to an example embodiment of the disclosure.

Fig. 2 illustrates an example method for forming a lead selenide (PbSe) photodetector in accordance with aspects of the disclosure.

Fig. 3A and 3B illustrate example PbSe PIN junctions in accordance with aspects of the present disclosure.

Fig. 3C illustrates an example PbSe PN junction in accordance with aspects of the present disclosure.

Fig. 4 is a graph providing light transmission depths of various materials in accordance with aspects of the present disclosure.

The figures are not necessarily drawn to scale. Wherever appropriate, like or identical reference numerals have been used to designate like or identical elements.

Detailed Description

Examples of systems and methods for photodetectors employing hybrid PIN or PN lead selenide (PbSe) structures are disclosed. In some examples, the PbSe junction may include one or more semiconductor layers, including, as a non-limiting example list, an n-type layer, an n+ -type layer, a p (i) -type layer, and/or a p+ -type layer.

In the present disclosure, a photodetector is formed that employs a PbSe PIN or PN junction. Methods for preparing a photosensitive PbSe semiconductor layer for detecting electromagnetic energy (e.g., mid-wavelength infrared (MWIR), etc.) are also disclosed.

In forming the example PbSe junction, the first PbSe n+ -type layer may be fabricated on the substrate by various physical and chemical deposition techniques including Pulsed Laser Deposition (PLD), molecular Beam Epitaxy (MBE), magnetron sputtering, electron beam/thermal evaporation, or Metal Organic Chemical Vapor Deposition (MOCVD) techniques. The second p (i) -type layer may be formed on the surface of the first layer via chemical deposition (e.g., chemical Bath Deposition (CBD) and other techniques mentioned previously). A third p+ -type layer may be formed on the surface of the second layer opposite the first layer via chemical deposition (e.g., CBD and other techniques mentioned previously).

The PbSe junction may be formed on a substrate (e.g., a silicon wafer) that may include an ion implanted layer (e.g., a doped semiconductor layer). The PbSe junction may be packaged as a photodetector to accommodate and/or be tuned to respond to the wavelength range of the incident light. In some examples, the wavelength range may include the Infrared (IR) band, particularly the mid-wavelength infrared (MWIR) (e.g., 3 μm to 5 μm) band.

As provided herein, the junctions at the interfaces between the semiconductor layers are prepared at different doping levels and dopant types. Such junctions are common in a wide variety of electronic devices. For example, a PIN junction is a specific type of semiconductor junction that employs three layers (each layer having a different doping amount).

The PIN junction typically includes an intrinsic (or undoped) semiconductor layer (e.g., a p (i) -type layer) disposed between two other semiconductor layers. Typically, the other two semiconductor layers include a doped p-type layer and a doped n-type layer. The p-type layer and the n-type layer may have similar doping levels or have different doping levels depending on the particular application or desired result. The doping level of one or both of the p-type layer and the n-type layer may be relatively high (as compared to the intrinsic semiconductor layer) because these layers operate as ohmic contacts within the device (e.g., photodetector).

Techniques for forming or depositing each layer, the type of material used to prepare one or more layers, and the dopant may determine the operational characteristics of the junction, such as the band gap energy between the p-type layer and the n-type layer. In the disclosed example, employing a PIN junction in a PbSe photodetector with a relatively wide intrinsic layer (e.g., p (i) layer) provides advantageous performance characteristics for photodetectors (e.g., in the MWIR range).

By using a PIN PbSe photodetector and its morphology/structural engineering, many advantages are provided, such as tunable band gap, relatively high response speed, low noise in operation, relatively high sensitivity to light, relatively low sensitivity to temperature, and can be manufactured in small packages at low cost, and provide adequate performance results over long-term use. Advantageously, the disclosed PbSe photodetector has a higher sensitivity and thus a greater detection capability, a wider temperature operating window, and is more cost-effective.

In the disclosed examples, the PbSe semiconductor layers produced by the disclosed methods can be used in photodetectors, providing low cost, small package detectors for a wide variety of applications, particularly in mid-wave IR applications where no cooling component is required. For example, the disclosed PbSe photodetectors, when coupled with other materials, may be used in other applications, products, and/or use cases (e.g., in addition to detection), including for solar cells, light emitting diodes, and/or lasers, as a non-limiting example list.

As used herein, "and/or" means any one or more of the plurality of items in the list connected by "and/or". For example, "x and/or y" means any element in the three-element set { (x), (y), (x, y) }. Similarly, "x, y, and/or z" means any element in the seven-element set { (x), (y), (z), (x, y), (x, z), (y, z), (x, y, z) }. As used herein, the term "module" refers to a function that may be implemented in hardware, software, firmware, or any combination of one or more thereof. As used herein, the term "example" or "exemplary" is meant to be used as a non-limiting example, instance, or illustration.

In the example of a single junction device, photons with incident energy greater than the bandgap of the affected material are absorbed. However, the excess energy of photons is lost in the form of heat via thermal relaxation. To reduce energy loss due to thermal relaxation and thereby improve conversion efficiency, multi-junction structures may be integrated by employing different semiconductor materials of different bandgap energies. By adding an additional multi-junction layer with other compound elements, the light absorption efficiency can be improved, thereby improving the spectral response. Thus, high energy photons can be absorbed with higher efficiency in such multi-junction structures.

However, the composition and fabrication of multi-junction semiconductors can increase the overall cost of the device due to increased material usage and production complexity. On the other hand, pbSe has a narrow bandgap, which allows light absorption in a larger range of the electromagnetic spectrum, most notably in the low and mid-infrared regions, where some semiconductor photovoltaic cells (e.g., silicon) cannot absorb light. Furthermore, the production of the disclosed PbSe junctions and corresponding thin films is much cheaper than conventional semiconductor materials used in photovoltaic mode operation.

In some disclosed examples, pbSe is used to form one or more semiconductor layers of a junction in a photodetector. PbSe is a polar semiconductor, exhibiting both ionic and covalent chemical bonds, where the nuclei forming these bonds share electrons unevenly. However, covalent bonds predominate in the resulting PbSe crystals. The crystalline PbSe film has a face-centered cubic lattice structure, which can have aboutBut may be smaller or larger depending on the desired characteristics). In some examples, for bulk materials, the lattice structure may have a direct bandgap of about 0.27eV at room temperature, and may have an intrinsic carrier density of 3 x 10 ¹⁶cm^-3 (although smaller or larger bandgaps and/or carrier densities may be present depending on the desired characteristics). Because of this narrow band gap, the structure is sensitive to radiation in the Infrared (IR) spectrum. For this reason, at least in part, some lead chalcogenides have been used in a wide variety of applications, including IR sensors, photoresistors, photodiodes, IR lasers, and/or thermoelectric generators. For example, pbSe provides detection at longer wavelengths (ranging from about 3 μm to about 5 μm) in the IR spectrum.

In addition, pbSe is a direct bandgap semiconductor capable of absorbing electromagnetic radiation in materials or layers as low as tens of nanometers in thickness, which is much thinner than conventional photosensitive materials, even thinner than materials with narrower light absorption ranges. In addition and advantageously, the disclosed PbSe junctions are relatively simple to fabricate in large areas (e.g., as compared to conventional semiconductor materials) at lower temperatures by low cost fabrication techniques such as liquid phase or thermal deposition, chemical Bath Deposition (CBD), and the like.

Fig. 1B illustrates a cross-sectional view of an example photodetector 100. In the example of fig. 1B, the photodetector 100 is a PbSe photodetector employing a PIN junction 102. The PIN junction 102 includes a first layer 108 (e.g., an n+ -type layer), a second layer 106 (e.g., a p (i) -type layer), and a third layer 104 (e.g., a p+ -type layer). Thus, the third layer 104 is configured to receive photons as windows and the absorbed photons generate electron-hole pairs in the layer 106, with the second layer 106 acting as an intrinsic layer. The PIN junction stack may be inverted and light may be absorbed via the top or bottom layers (e.g., via the first layer 108 or the third layer 104, as a thinned Si substrate).

The photodetector 100 employs a substrate 114 on which the junction 102 is formed. In some examples, the expensive quartz substrate may be replaced with cheaper materials (such as silicon and/or glass). For example, the substrate 114 may be a doped n-type Si wafer. In some examples, substrate 114 is Si with ion implantation, si with SiO ₂, and/or glass (such as indium tin oxide—ito or other transparent conductive oxide on glass).

Layer 116 may be bonded or otherwise formed on substrate 114, which may be fully or partially exposed on a surface of the substrate. Additionally or alternatively, layer 116 may be doped. For example, layer 116 may be an ion implanted layer (e.g., a doped n+ layer with phosphorus). In some examples, layer 116 is defined by a doping level and/or carrier concentration that is different from (e.g., greater than) substrate 114. The junction 102 is disposed on the layer 116 such that the layer forms a conductive path between the junction and a conductor (e.g., electrode portion 110D).

The junction 102 is partially enclosed within one or more sidewalls 112 to ensure charge isolation between the junction and external components. The sidewalls 112 may be any number of suitable materials for isolating and/or passivating the junction sidewalls, such as dielectric materials (including, but not limited to, oxides, carbides, nitrides, fluorides, sulfides, and/or composites thereof) and/or polymeric materials.

First or underlayer 108 (formed directly on substrate 114 and/or ion implantation layer 116) includes an n-type PbSe layer deposited via PLD (or other suitable deposition technique as described above). The first layer 108 is doped to have a relatively high carrier concentration of about 10 ¹⁸ to 10 ²⁰ carriers per cm ³ (as compared to the second layer 106). The resulting layer has a relatively high carrier concentration.

The second or intermediate layer 106 comprises a p-type PbSe layer and may be formed via chemical deposition (e.g., CBD) or other suitable technique as previously mentioned. The second layer 106 may be lightly doped and serve as an intrinsic region between the p-doped layer 104 and the n-doped layer 108, respectively. The carrier concentration of the second layer 106 is much lower than the first layer 108 or the third layer 104, respectively, wherein the carrier concentration is about 10 ¹⁶ carriers per cm ³. The second layer 106 acts as a wide depletion layer between the other layers due to the relatively small amount of mobile carriers with external dopants. In some examples, an oxide layer may be applied on the surface of the second layer 106.

The third layer 104 includes a p+ -type PbSe layer. The third layer 104 may be formed via chemical deposition (e.g., CBD) or other suitable technique. The third layer 104 is doped to have a relatively high carrier concentration of about 10 ¹⁷ to 10 ¹⁸ carriers per cm ³ (as compared to the second layer 106). In some examples, a thin film oxide layer may be applied to the third layer 104.

Sidewalls 112 are formed over portions of junction 102, substrate 114, and/or layer 116. The sidewalls 112 provide passivation and isolation layers between the junction 102 and other components and may include one or more oxides, such as silicon dioxide (SiO ₂), aluminum oxide (Al ₂O₃), and/or another suitable material (e.g., oxide, carbide, nitride, fluoride, sulfide, and/or composites thereof) and/or a polymeric material. Electrode portions 110A to 110D are formed on photodiode 100 to provide a conductive path between electrode portions 110C and 110D through junction 102. The electrode portions 110A-110D are formed of a conductive material (e.g., metal, including gold) and are formed by one or more deposition techniques.

Fig. 1A shows a partial top view of photodiode 100. The electrode portion 110B is connected to the electrode portion 110A, which provides a conductive path to the third layer 104.

In some disclosed examples, as illustrated in fig. 2, a method 200 for processing a PbSe photodetector (e.g., employing a PIN junction, a PN junction, etc.), such as PbSe photodetector 100, is provided. The method 200 includes one or more of substrate preparation in block 202, formation of an ion implanted layer in block 204, deposition of a first layer in block 206, deposition of a second layer in block 208, deposition of a third layer in block 210, passivation and isolation of sidewalls in block 212, and metallization and encapsulation in block 214.

In some examples, in block 202, the substrate may be prepared from a material selected from one of several suitable candidates, including sapphire, quartz, fused silica, silicon oxide, silicon (Si), and the like. In some examples, the substrate is subjected to pre-cleaning (which may include additional or alternative plasma cleaning) and/or surface treatment in the substrate preparation step to roughen one or more surfaces of the substrate.

The substrate may include portions or layers that couple the junction with the conductor, such as ion implantation layer 116, which is deposited, formed, and/or otherwise introduced into the substrate in block 204.

In block 206, the first layer may be an n-type PbSe semiconductor layer and may be deposited by chemical and physical deposition techniques (e.g., PLD, MOCVD, or MBE). In block 208, the second layer may be a p-type PbSe semiconductor layer produced by chemical deposition (e.g., CBD) of lightly doped PbSe. In block 209, the carrier concentration of the second layer may be controlled via oxygen and/or iodine sensitization, and/or by additional material processing and/or treatment.

In block 210, the third layer may be a p+ -type heavily doped PbSe semiconductor layer deposited by chemical deposition (e.g., CBD). In some examples, thin film oxidation (e.g., oxygen sensitization, thin coatings, or thin layers) may be applied to one or more of the layers, such as the second layer and the third layer. Other deposition techniques may be applied to form the second or third layer.

In block 212, sidewalls are formed to passivate and/or isolate the structure. In some examples, the sidewall(s) are formed from SiO ₂ or Al ₂O₃ material (e.g., dielectric material (such as oxide, carbide, nitride, fluoride, sulfide, and/or composites thereof) and/or polymeric material). In block 214, metallization and packaging processes are performed to provide conductive contacts, resulting in a semiconductor PbSe photodetector.

In some additional or alternative examples, one or more layers are subjected to one or more of heat treatment (e.g., vacuum bake and/or post bake), oxygen sensitization, film iodination (e.g., iodine sensitization), and/or chemical etching at ambient conditions to remove oxide (e.g., after formation of sidewalls). As provided herein, the method may be performed as listed, may be performed as one or more of the listed acts that are optional and/or differently arranged.

Fig. 3A-3C provide example PbSe junctions employed in the photodetector 100, as disclosed herein. Fig. 3A shows the example junction 102 as a PIN junction having a first n+ -type layer 108, a second p (i) -type layer 106, and a third p+ -type layer 104, wherein the first layer 108 is formed on a substrate 114 (as shown in fig. 1B). However, the example junction 102A shown in fig. 3B suggests that the first layer 108 and the third layer 104 (e.g., n+ type layer and p+ type layer, respectively) are interchanged, thereby resulting in a junction having similar capabilities as in fig. 3A.

In operation, a PIN photodiode employing junction 102 or 102A operates under reverse bias. Reverse biasing of the PIN photodiode can introduce noise currents, which reduce the signal-to-noise ratio in operation. Further, reverse biasing provides better performance for high dynamic range applications (relative to PN photodiodes).

The intrinsic layer also increases the width of the depletion region. Carriers are generated in the intrinsic region because this layer is much thicker than the depletion region of the PN structure (which lacks the intrinsic layer). Another effect of the thick intrinsic region may be to reduce capacitance, which allows for an increase in detection bandwidth. The wide depletion layer provided by the intrinsic layer further ensures that the PIN diode has high reverse breakdown characteristics. Since the capacitance decreases with increasing spacing, the depletion region will be wider than a comparable diode employing a PN junction (as shown in fig. 3C). This may be pn+ or n+p in the stack.

The PN junction 102B for the PN photodiode is shown in FIG. 2C. The PN junction 102B provides a first n-type layer 108 and a second p-type layer 104, wherein the first layer 108 is formed on a substrate. In some examples, the order of the layers may be reversed with respect to the substrate. Some example PN photodiodes provide different capabilities than PIN photodiodes. For example, PN photodiodes do not need to be reverse biased, and thus may exhibit sensitivity to low light applications.

Fig. 4 illustrates an example annotation graph of light transmission depth. The figure is an example submitted to the Journal of application physics (Journal of APPLIED PHYSICS) (see, e.g., journal of APPLIED PHYSICS) 93,4355 (2003); https:// doi. Org/10.1063/1.1558224). The absorbance and depth of light transmission are shown for various photodetector materials, with a spectral range of 1 μm to 14 μm. As shown, pbSe exhibits a sharp turn at about 4 μm, corresponding to an absorbance of approximately 10 ⁴/cm, and a light transmission depth of approximately 1/α (μm) (depth of approximately 1.7 μm).

Although several examples and/or embodiments are described with respect to a PbSe layer, the principles and/or advantages disclosed herein may employ techniques that are not limited to a particular type of material and/or application.

While the disclosure has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the disclosure. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the disclosure without departing from the scope thereof. Therefore, it is intended that the disclosure not be limited to the particular embodiments disclosed, but that the disclosure will include all embodiments falling within the scope of the appended claims.

Claims (9)

1. A method of forming a photodetector having a lead selenide (PbSe) junction, the method comprising:

Preparing a substrate;

forming an ion implantation layer;

Depositing a first heavily doped lead selenide (PbSe) layer over the substrate and the ion implantation layer via various deposition techniques, such as Pulsed Laser Deposition (PLD), molecular Beam Epitaxy (MBE), or Metal Organic Chemical Vapor Deposition (MOCVD);

Depositing a second lightly doped or undoped PbSe layer over the first layer via a Chemical Bath Deposition (CBD) process or other deposition technique;

depositing a third heavily doped PbSe layer on a second layer opposite the first layer via a CBD process or other deposition technique;

Forming a sidewall around one or more of the substrate, the ion implantation layer, the first layer, the second layer, or the third layer, and

One or more conductors are formed on one or more of the first layer, the second layer, or the third layer.

2. The method of claim 1, further comprising applying an oxide layer on one or more of the second layer or the third layer.

3. The method of claim 1, wherein a doping level of the first layer is substantially similar to a doping level of the third layer.

4. The method of claim 1, wherein a doping level of the first layer is greater than a doping level of the third layer.

5. The method of claim 1, wherein the doping level of the second layer is substantially shallower.

6. A method of forming a photodetector having a lead selenide (PbSe) junction, the method comprising:

Preparing a substrate;

forming an ion implantation layer;

Depositing a first doped lead selenide (PbSe) layer on the substrate and the ion implantation layer via various deposition techniques, such as Pulsed Laser Deposition (PLD), molecular Beam Epitaxy (MBE), or Metal Organic Chemical Vapor Deposition (MOCVD);

Depositing a second layer of doped PbSe layer on the first layer via a Chemical Bath Deposition (CBD) process or other deposition technique;

controlling the carrier concentration of the second layer via oxygen or iodine sensitization or additive material processing or treatment;

forming a sidewall around one or more of the substrate, the ion implantation layer, the first layer, or the second layer, and

One or more conductors are formed on one or more of the first layer or the second layer.

7. The method of claim 6, further comprising applying an oxide layer on one or more of the first layer or the second layer.

8. The method of claim 6, wherein a doping level of the first layer is substantially similar to a doping level of the third layer.

9. The method of claim 6, wherein a doping level of the first layer is greater than a doping level of the second layer.