CN119052481A - Pixel sampling device, method and image compression system - Google Patents
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Abstract
本申请涉及图像处理技术领域，公开了一种像素采样装置、方法及图像压缩系统。该装置包括：第一地址发生器，预测调整单元、私有缓存单元及下采样单元；所述第一地址发生器，用于根据预先设置的初始地址及终止地址，向外部存储器中的目标图像发起读请求；所述读请求，用于读取目标图像的所有目标数据块；所述私有缓存单元，用于缓存历史图像中的高频数据块和对应的像素频率信息，以及预测期值；所述预测调整单元，用于根据当前的预测期值，预测当前的目标数据块是否与所述私有缓存单元中的高频数据块相同；根据预测结果，将所述目标数据块或所述高频数据块确定为待转换数据块；所述预测期值，是基于对上一个目标数据块进行预测的预测结果确定的；所述下采样单元，用于对所述待转换数据块进行色彩空间转换，以及色度信息下采样，得到结果数据块。基于本装置能够实现图像压缩的硬件采样过程，减少对系统资源的占用，并且能够提高图像压缩效率。
The present application relates to the field of image processing technology, and discloses a pixel sampling device, method and image compression system. The device includes: a first address generator, a prediction adjustment unit, a private cache unit and a downsampling unit; the first address generator is used to initiate a read request to the target image in the external memory according to the preset initial address and end address; the read request is used to read all target data blocks of the target image; the private cache unit is used to cache the high-frequency data blocks and corresponding pixel frequency information in the historical image, as well as the prediction period value; the prediction adjustment unit is used to predict whether the current target data block is the same as the high-frequency data block in the private cache unit according to the current prediction period value; according to the prediction result, the target data block or the high-frequency data block is determined as the data block to be converted; the prediction period value is determined based on the prediction result of the previous target data block; the downsampling unit is used to perform color space conversion on the data block to be converted, and downsample the chromaticity information to obtain the result data block. Based on the present device, the hardware sampling process of image compression can be realized, the occupation of system resources can be reduced, and the image compression efficiency can be improved.
Description
Technical Field
The present application relates to the field of image processing technologies, and in particular, to a pixel sampling device, a pixel sampling method, and an image compression system.
Background
The human eyes are sensitive to the brightness information and the chrominance information, and sensitive to the low-frequency information and the high-frequency information, and the image compression is to cut or remove the data insensitive to the human eyes according to the visual characteristics of the human eyes. JPEG (Joint Photographic Experts Group) is a widely used image file format, compression of JPEG is based on lossy compression, which is a process that first converts RGB chrominance information into YCbCr color space. YCbCr is a derivative of the YUV color space in which Y is the luminance component, cb is the blue chrominance component, and Cr is the red chrominance component. To reduce the amount of redundant information contained in the chrominance channels, the chrominance information of the image data is also downsampled, typically from the original YUV4:4:4 format to the 4:2:2 or 4:2:0 format. Then, the luminance and chrominance information in the image space domain is transformed into the frequency domain through DCT, the luminance information is finely quantized, the color information is coarsely quantized, the low-frequency information is finely quantized, and the high-frequency information is coarsely quantized. Finally, the quantized result is subjected to variable length coding, so that the purpose of compressing pictures is achieved, and the quality of the pictures seen subjectively by human eyes is ensured not to be greatly reduced.
The current implementation manner of JPEG is mostly a software implementation manner, and color space conversion sampling and DCT (Discrete Cosine Transform ) processing are implemented based on an operating system, so that the problem at present is that the execution of JPEG image compression by software occupies a large amount of computing resources of a CPU (Central Processing Unit ), and occupies more software threads, so that the computing resources are tensed, the computing efficiency is reduced, and particularly in the fields with stronger timeliness, such as AI computing, server group computing, super computing and the like, the computing resources are greatly consumed, and the efficiency of image compression processing is seriously reduced. In addition, the optimization of the image frequency domain in the JPEG compression process is in the DCT stage after sampling, but a large amount of high-frequency data can still be reserved in the sampling stage, the high-frequency data is frequently accessed in the sampling process to cause great access pressure on a bus, excessive bus resources are occupied, delay is increased, and the image compression efficiency is low.
Disclosure of Invention
In view of the foregoing, the present application is directed to a pixel sampling apparatus, a pixel sampling method, and an image compression system, so as to reduce system resource occupation and improve image compression processing efficiency.
In order to achieve the above purpose, the technical scheme of the application is as follows:
A first aspect of an embodiment of the present application provides a pixel sampling apparatus connected to an external memory through a system bus, including:
The device comprises a first address generator, a prediction adjusting unit, a private cache unit and a downsampling unit;
the first address generator is used for initiating a read request to a target image in the external memory according to a preset initial address and a preset termination address, wherein the read request is used for reading all target data blocks of the target image;
The private caching unit is used for caching the high-frequency data blocks and the corresponding pixel frequency information in the historical images and the prediction period value;
the prediction adjusting unit is used for predicting whether the current target data block is identical to the high-frequency data block in the private cache unit according to the current prediction period value, and determining the target data block or the high-frequency data block as a data block to be converted according to a prediction result;
and the downsampling unit is used for performing color space conversion on the data block to be converted and downsampling the chromaticity information to obtain a result data block.
Optionally, the pixel sampling device further includes at least one bus read interface, a bus arbiter, and a first buffer module;
The first address generator is further configured to sequentially access each bus read interface, and initiate a corresponding read request to the external memory;
the bus arbiter is used for adjusting the writing sequence of the target data blocks returned by each bus reading interface according to the protocol handshake signals returned by each bus reading interface;
The first buffer module is used for buffering all target data blocks in the target image.
Optionally, the pixel sampling device further includes a second buffer module, configured to buffer a data block to be converted;
Before predicting the pixel frequency information of the target data block according to the prediction period value, the prediction adjustment unit is further used for determining that the historical image is a high-frequency data block according to the DCT feedback result of the previous historical image, wherein the ratio of the maximum value of the pixel frequency to the minimum value of the pixel frequency in the high-frequency data block is greater than or equal to a first threshold value;
Predicting the pixel frequency information of the target data block according to the prediction period value, specifically including:
Based on the high-frequency tag number, acquiring a corresponding historical data block from the private cache unit;
Reading a prediction period value from the private cache unit, and judging whether the current prediction period value is larger than or equal to a second threshold value;
predicting that the pixel frequency information of the target data block is consistent with the pixel frequency information of the historical data block under the condition that the prediction period value is greater than or equal to a second threshold value;
and writing the historical data block serving as a prediction result into the second cache module.
Optionally, the prediction adjustment unit is configured to determine a data block to be converted, and specifically includes:
comparing the target data block with the historical data block, and judging whether the pixel frequency information is consistent;
Under the condition that the pixel frequency information is consistent in comparison, taking the predicted data block stored in the second buffer module as a data block to be converted;
and under the condition that the pixel frequency information contrast is inconsistent, writing the target data block serving as the data block to be converted into the second buffer memory module, and covering the predicted data block.
Optionally, the prediction adjustment unit is further configured to perform the following steps:
adding a high-frequency tag number which is the same as the predicted data block to the target data block;
in the case of inconsistent pixel frequency information contrast, the current prediction period value is reduced by 1.
Optionally, the prediction adjustment unit is further configured to perform the following steps:
predicting that pixel frequency information of the target data block and the historical data block is inconsistent under the condition that the prediction period value is smaller than the second threshold value;
And directly writing the target data block into the second cache module.
Optionally, the prediction adjustment unit is further configured to adjust an access sequence of all the data blocks to be converted in the second buffer module, so that the data blocks to be converted without the high-frequency tag number are preferentially accessed.
Optionally, the downsampling unit includes:
The computing module is used for carrying out color space conversion on the data block to be converted by adopting a binary algorithm to obtain data to be sampled, and comprises a shift register, an 8-bit multiplier, an 8-bit complement adder-subtractor and a register;
the sampling memory is used for buffering data to be sampled, wherein every two data to be sampled are stored in a combined mode;
The sampling module comprises a reading operation module and a second address generator, wherein the second address generator is used for generating a plurality of head addresses based on a second size, and the reading operation module is used for downsampling chromaticity information of a data block to be sampled in the sampling memory according to each head address to obtain a result data block.
According to a second aspect of the embodiment of the present application, there is provided a pixel sampling method, and the pixel sampling apparatus provided according to the first aspect of the embodiment of the present application includes:
Initiating a read request to a target image in an external memory according to a preset initial address and a preset termination address by a first address generator, and reading all target data blocks of the target image;
predicting whether a current target data block is the same as a high-frequency data block in a private cache unit according to a current prediction period value, and determining the target data block or the high-frequency data block as a data block to be converted according to a prediction result;
and performing color space conversion and chroma information downsampling on the data block to be converted to obtain a result data block.
According to a third aspect of an embodiment of the present application, there is provided an image compression system including:
The pixel sampling apparatus provided in the first aspect of the embodiment of the present application, wherein the downsampling unit further includes a third buffer module, configured to store the result data block;
The compression unit is used for obtaining a result data block from the third buffer module, and performing DCT transformation, quantization and coding compression to obtain a compressed data block;
and transmitting DCT feedback results of all target data blocks of the target image obtained by DCT conversion to a prediction adjustment module in the pixel sampling device.
According to a fourth aspect of embodiments of the present application, there is provided a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the pixel sampling method according to the second aspect of embodiments of the present application.
According to a fifth aspect of an embodiment of the present application, there is provided an electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the steps in the pixel sampling method according to the second aspect of the embodiment of the present application are implemented when the processor executes the computer program.
The pixel sampling device provided by the application is connected with an external memory through a system bus, and initiates a read request to the external memory through a first address generator according to the storage address of a target image in the external memory, and reads the data of the target image in the form of a target data block. The prediction adjusting unit obtains the target data block, predicts the target data block based on the current prediction period value, and predicts whether the current target data block is identical with the high-frequency data block in the last historical image cached in the private caching unit. And if the current target data block is the same as the high-frequency data block in the previous historical image, outputting the historical image data block in the private cache to the downsampled data block for processing instead of the target data block. Since the pixels in the image are continuous, the probability that the next target data block is identical to the high-frequency data block stored in the private buffer memory is higher in the case of multiple prediction hits (i.e., high prediction period values), the data block is read from the private buffer memory and input to the downsampling unit, and the timeliness of compressed image processing can be improved.
The application adopts a hardware mode to realize the color space conversion and downsampling of the image, thereby reducing the frequency of CPU accessing the bus and reducing the occupation of system resources. By predicting the next target data block to be processed in advance, the downsampling unit can directly process the high-frequency data block in the private cache under the condition that the prediction hits the high-frequency data, so that the time delay caused by frequent access to the external memory through the system bus is reduced, the image sampling efficiency is improved, and the overall compression efficiency of the image is further improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments of the present application will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a pixel sampling apparatus according to an embodiment of the present application;
FIG. 2 is a state jump diagram of a state machine controller according to an embodiment of the present application;
FIG. 3 is a flowchart illustrating operation of the predictive adaptation unit in accordance with one embodiment of the application;
FIG. 4 is a schematic diagram of a downsampling unit according to an embodiment of the application;
FIG. 5 is a flowchart of a pixel sampling method according to an embodiment of the present application;
Fig. 6 is a schematic diagram of an image compression system according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
In various embodiments of the present application, it should be understood that the sequence numbers of the following processes do not mean the order of execution, and the order of execution of the processes should be determined by the functions and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods that are consistent with some aspects as detailed in the application.
It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other.
According to the application, hardware modeling is performed through Verilog, so that an efficient JPEG pixel sampling scheme is realized. The present embodiment describes the implementation of the RGB image compression JPEG scheme based on an FPGA (Field-Programmable GATE ARRAY ). The application will be described in detail below with reference to the drawings in connection with embodiments.
Fig. 1 is a schematic diagram of a pixel sampling apparatus according to an embodiment of the application. The device is connected with an external memory through a system bus and comprises a first address generator 101, a prediction adjusting unit 102, a private buffer unit 103 and a downsampling unit 104;
The first address generator 101 is configured to initiate a read request to a target image in an external memory according to a preset initial address and a preset termination address, where the read request is used to read all target data blocks of the target image;
the private caching unit 103 is configured to cache the high-frequency data block and the corresponding pixel frequency information in the history image, and a prediction period value;
The prediction adjustment unit 102 is configured to predict whether a current target data block is the same as a high-frequency data block in the private cache unit according to a current prediction period value, and determine the target data block or the high-frequency data block as a data block to be converted according to a prediction result;
the downsampling unit 104 is configured to perform color space conversion on the data block to be converted, and downsample chroma information to obtain a result data block.
In this embodiment, the pixel sampling device models based on verilog. The 32bit RGB image data is stored in the external memory in advance, the pixel sampling device generates a read request through the first address generator, accesses the external memory through the system bus, and requests to read target image data in the external memory. In this embodiment, the target image data is RGB image data. The target image data is read in the form of 8x 8-sized data blocks (i.e., target data blocks), which are predicted by the prediction adjustment unit. The private buffer unit stores the feedback result of the DCT stage of the previous image (history image), and the prediction adjustment unit predicts the target data block according to the information of the high-frequency data block in the previous image and the current prediction period value, and predicts whether the current target data block is the same as the high-frequency data block in the previous history image buffered in the private buffer unit. And if the current target data block is the same as the high-frequency data block in the previous historical image, outputting the historical image data block in the private cache to the downsampled data block for processing instead of the target data block. The prediction period value is changed according to the prediction result of predicting different data blocks each time, and since pixels in the image are continuous, the prediction result of the previous data block will affect the prediction period value, and further affect the current data block prediction result.
The high-frequency data block appearing in the target image is predicted through the prediction adjusting unit, and under the condition that the prediction of the target data block hits (namely, the prediction is correct), the downsampling unit can directly process the corresponding high-frequency data block in the history image stored in the private caching unit without reading the target data block from an external memory every time, so that the bus read-write frequency of accessing the high-frequency data is reduced, the sampling efficiency of the target image is improved, and the timeliness of compression JPRG is improved.
As an embodiment of the present application, the pixel sampling device further includes at least one bus read interface, a bus arbiter, and a first buffer module;
The first address generator is further configured to sequentially access each bus read interface, and initiate a corresponding read request to the external memory;
the bus arbiter is used for adjusting the writing sequence of the target data blocks returned by each bus reading interface according to the protocol handshake signals returned by each bus reading interface;
The first buffer module is used for buffering all target data blocks in the target image.
In this embodiment, the operation states of the modules in the pixel sampling device are controlled by the state machine controller. FIG. 2 is a state jump diagram of a state machine controller according to an embodiment of the present application. As shown in fig. 2, the state machine has 8 states, specifically:
(1) In the initialization address stage, the state machine controller controls the first address generator to internally configure an initial address and a termination address of the image storage position. After the configuration is completed, enabling the work and jumping to the next state;
(2) In the pixel data reading stage, a read address and a read request are generated by a first read address generator, and read data (RGB image data) is obtained by a bus. In this embodiment, the system bus is based on AMBA bus protocol, and the interface uses an AHB bus interface protocol part in AMBA protocol to ensure communication compatibility of modeling. After a read request is sent out, jumping to the next state;
(3) The RGB image data is written into a first buffer memory module (FIFO-0) in the form of block (data block) to wait for reading, and after the target data block is buffered, the next state is skipped;
(4) In the high-frequency prediction stage, the prediction adjustment unit predicts the target data block at high frequency, marks the target data block if the target data block is predicted to be the same as the high-frequency data block in the private cache unit, and writes the cached high-frequency data block into the second cache module (FIFO-1) instead of the target data block as a data block to be converted for subsequent processing. The prediction adjusting unit also adjusts the sequence of the data blocks processed by the downsampling unit, preferentially processes the data blocks with balanced pixel frequency, and discharges the high-frequency data blocks later. After the adjustment is completed, jumping to the next state;
(5) The second buffer module stores all data blocks to be converted which need to be subjected to color space conversion and downsampling, the data blocks are sequentially transmitted to the downsampling module according to the buffer queue sequence, and after all data blocks are transmitted, the next state is skipped;
(6) The downsampling module performs color space conversion on the data block to be converted to obtain YCbCr data. After the color space conversion is completed, jumping to the next state;
(7) And the downsampling module performs chroma information downsampling operation on the YCbCr data, removes part of chroma information, and reduces the storage space occupied by the image data. After the downsampling is completed, jumping to the next state;
(8) After the downsampling is completed, the image data of YCbCr is output.
In the present embodiment, the number of bus read interfaces for accessing the external memory may be set according to actual situations, and in the present embodiment, 4 bus read interfaces (interface 0, interface 1, interface 2, interface 3) are illustrated as an example. The first address generator sequentially accesses the system bus read interface based on the initial address accumulation mode, sends a read request to the external memory, and returns response data (namely, target images). In one embodiment, when multiple read requests or read data occur simultaneously, the order of execution is arbitrated by the bus arbitration module.
In this embodiment, the bus arbiter arbitrates the order of writing the target data blocks into the first buffer module (FIFO-0) according to the protocol handshaking signals fed back by each bus read interface. Specifically, a polling arbitration mode is adopted, the returned IDs in the data responded by the external memory are read, and the target data blocks are sequentially written into the first cache module according to the sequence of sending the read requests. In the embodiment, the first buffer module is built based on a BLOCK RAM device of an FPGA, and internally comprises a write data control module, a read data control module, a Gray code conversion module, a Gray code synchronization module, an empty-full signal generation module and a data storage module (dual-port RAM). The parameter characteristics of the first buffer module are that the bit width is 32 bits, the depth is 4096,1 read interfaces and 1 write interfaces.
Under the condition that a plurality of bus read interfaces simultaneously have response data, the write-in sequence of each response data is arbitrated through a bus arbiter, so that target data blocks are sequentially written into a first buffer unit according to the request sequence, the processing sequence of the target data blocks is ensured to be correct, and errors of the data in the subsequent processing process are avoided.
As one embodiment of the present application, the pixel sampling apparatus further includes a second buffer module, configured to buffer a data block to be converted;
Before predicting the pixel frequency information of the target data block according to the prediction period value, the prediction adjustment unit is further used for determining that the historical image is a high-frequency data block according to the DCT feedback result of the previous historical image, wherein the ratio of the maximum value of the pixel frequency to the minimum value of the pixel frequency in the high-frequency data block is greater than or equal to a first threshold value;
Predicting the pixel frequency information of the target data block according to the prediction period value, specifically including:
Based on the high-frequency tag number, acquiring a corresponding historical data block from the private cache unit;
Reading a prediction period value from the private cache unit, and judging whether the current prediction period value is larger than or equal to a second threshold value;
predicting that the pixel frequency information of the target data block is consistent with the pixel frequency information of the historical data block under the condition that the prediction period value is greater than or equal to a second threshold value;
and writing the historical data block serving as a prediction result into the second cache module.
FIG. 3 is a flowchart illustrating the operation of the predictive adaptation unit in accordance with an embodiment of the application. As shown in fig. 3, in this embodiment, before predicting the current target data block, the prediction adjustment unit obtains the feedback result of the previous historical image in the DCT phase, and adjusts the processing mode of the data block according to the frequency domain feedback result of the DCT phase of JPEG. The private cache unit is responsible for recording the pixel frequency evaluation condition of each data block in the picture and marking the corresponding position and address of the picture. Specifically, the high-frequency data block is screened from the historical pictures, and the steepness degree of the data block is judged according to the occurrence frequency of the pixel with the highest occurrence frequency and the occurrence frequency of the pixel with the lowest occurrence frequency in the data block, namely whether the data block is the high-frequency data block or not is judged. In this embodiment, whether the data block is a high frequency data block is determined by the first threshold value, and if the ratio of the pixel frequency with the highest frequency to the pixel frequency with the lowest frequency in the data block is greater than or equal to the first threshold value, the data block is determined to be the high frequency data block. In practical applications, the first threshold of the prediction period value may be set according to requirements, for example, set to 3.
The high frequency data block is stored in the private cache space and marked, and the marking content and the data structure are shown in the following table 1, and the marking content and the data structure comprise the frame position of the data block in the image, the storage space address of the data block and the corresponding high frequency marking number.
TABLE 1
| Frame position | Memory space address | High frequency tag number |
The high-frequency tag number occupies 0-7bit, the storage space address occupies 8-39bit, and the frame position occupies 40-55bit.
When a target data block is predicted, the prediction period value is read, if the prediction period value is larger than or equal to a second threshold value, the current target data block is consistent with the pixel frequency information of the corresponding high-frequency data block stored in the private cache unit, on the basis, the corresponding historical data block is read from the private cache unit according to the high-frequency tag number as a prediction result, and the cached data block is used for replacing the target data block to be written into a second cache module, so that the sampling efficiency of an image is improved, and the delay caused by frequently accessing a bus to acquire the target data block is reduced. For example, when the previous target data block hits the history data block of the high frequency tag number 2 and the prediction period value is higher than the second threshold value, the current target data block is likely to hit the history data block of the high frequency tag number 3, so the current prediction searches for the corresponding history data block based on the high frequency tag number 3 and is used as the prediction result of the current target data block.
As an embodiment of the present application, the prediction adjustment unit is configured to determine a data block to be converted, and specifically includes:
comparing the target data block with the historical data block, and judging whether the pixel frequency information is consistent;
Under the condition that the pixel frequency information is consistent in comparison, taking the predicted data block stored in the second buffer module as a data block to be converted;
and under the condition that the pixel frequency information contrast is inconsistent, writing the target data block serving as the data block to be converted into the second buffer memory module, and covering the predicted data block.
In this embodiment, after the target data block predicts and hits the high frequency data block and outputs the prediction result, in order to ensure the correctness of the processing of the target image by the downsampling module, the data block of the prediction result is further compared with the real target data block, so as to verify whether the prediction result is correct.
In this embodiment, after the prediction result is written into the second buffer module, the target data block is compared with the prediction result (the history data block), so as to verify whether the prediction result of the target data block is correct. And under the condition that the pixel frequency information comparison of the two is consistent, determining that the prediction result is correct, namely, writing the prediction result (the prediction data block) of the second buffer module into the second buffer module for processing by the downsampling module. And according to the high-frequency tag number of the predicted data block, the target data block is marked in the same way, combined with the target data block and written into a private cache unit.
If the pixel frequency information contrast of the two is inconsistent, a prediction error is indicated, and in this case, the target data block is written into the second buffer memory module to be refreshed, and the prediction result (predicted data block) in the second buffer memory module is covered, so that the correctness of the image data processed by the subsequent downsampling module is ensured. In this embodiment, the target data block is predicted in advance, so that the efficiency of downsampling is improved, and the prediction result is verified after the prediction result is written into the second buffer module, so as to ensure the correctness of the sampled image data.
As an embodiment of the present application, the prediction adjustment unit is further configured to perform the following steps:
adding a high-frequency tag number which is the same as the predicted data block to the target data block;
in the case of inconsistent pixel frequency information contrast, the current prediction period value is reduced by 1.
In this embodiment, the prediction period value is adjusted based on the comparison result of each prediction result and the real data block, so that the accuracy of the prediction result when the next data block is predicted is improved, the number of repeated brushing and covering of the second buffer unit is reduced, and the image sampling efficiency is further improved.
Specifically, in the case that the pixel frequency information is consistent in comparison, that is, the prediction result of the current target data block is correct, the current prediction period value is increased by 1, so that the hit probability in predicting the next target data block is increased. That is, the probability of the next data block prediction hit is increased, indicating that the next data block is more likely to be high frequency data in the case of hit of high frequency data in a continuous plurality of predictions.
Correspondingly, under the condition that the pixel frequency information is inconsistent in comparison, namely the current prediction result of the target data block is incorrect, the current prediction period value is reduced by 1, so that the hit probability when the next target data block is predicted is reduced. That is, the probability of the next data block prediction hit is reduced, indicating that after the present prediction is wrong, the next target data block has a certain probability of not being high frequency data.
As an embodiment of the present application, the prediction adjustment unit is further configured to perform the following steps:
predicting that pixel frequency information of the target data block and the historical data block is inconsistent under the condition that the prediction period value is smaller than the second threshold value;
And directly writing the target data block into the second cache module.
In this embodiment, when the prediction period value does not reach the second threshold value, it is indicated that the prediction of the data block preceding the current target data block does not hit, and the probability that the current target data block hits the high-frequency data is small due to the continuity of the pixels in the image. In this case, the pixel frequency information of the target data block and the history data block is predicted to be inconsistent, that is, the current target data block is not high frequency data, and therefore, the target data block is normally written into the second buffer module to wait for the processing of the downsampling module.
As an implementation manner of the present application, the prediction adjustment unit is further configured to adjust an access sequence of all the data blocks to be converted in the second buffer module, so that the data blocks to be converted without the high-frequency tag number are preferentially accessed.
In this embodiment, the prediction adjustment unit further adjusts the reading sequence of each data block according to whether the target data block in the second buffer module has the high-frequency tag number. Specifically, the data blocks to be converted (high frequency data) with the high frequency tag numbers are arranged later, so that the data blocks without the high frequency tag numbers are preferentially processed. Because the high-frequency data needs to be removed in the subsequent DCT conversion stage in the JPRG image compression process, the subsequent centralized processing of the high-frequency data can be facilitated by adjusting the processing sequence, and the processing efficiency is further improved.
As an embodiment of the present application, the downsampling unit includes:
The computing module is used for carrying out color space conversion on the data block to be converted by adopting a binary algorithm to obtain data to be sampled, and comprises a shift register, an 8-bit multiplier, an 8-bit complement adder-subtractor and a register;
the sampling memory is used for buffering data to be sampled, wherein every two data to be sampled are stored in a combined mode;
The sampling module comprises a reading operation module and a second address generator, wherein the second address generator is used for generating a plurality of head addresses based on a second size, and the reading operation module is used for downsampling chromaticity information of a data block to be sampled in the sampling memory according to each head address to obtain a result data block.
In the JPEG compression process, conversion from the RGB color space to the YCbCr color space requires the use of the following conversion formula:
Y=0.299000R+0.587000G+0.114000B
Cb=-0.168736R-0.331264G+0.500002B
Cr=0.500000R-0.418688G-0.081312B
Where Y is the luminance component, cb is the blue chrominance component, cr is the red chrominance component, R is the red component in the RGB image, G is the green component in the RGB image, and B is the blue component in the RGB image. In the current software compression scheme, floating point calculation and subtraction calculation are involved, and because floating point numbers are represented by 32 bits, a large number of floating point number calculation can cause excessive system power consumption, greatly occupy calculation resources and have low image compression efficiency. In this embodiment, in order to further reduce the occupation of computing resources and improve the sampling efficiency, the downsampling unit implements color space conversion and downsampling based on a binary hardware manner.
Fig. 4 is a schematic diagram of a downsampling unit according to an embodiment of the application. As shown in fig. 4, the downsampling unit includes:
a shift register including calculation parameters for inputting calculation Y component, cb component and Cr component (such as coefficient "0.299000" in the above conversion formula);
3 groups of calculation modules, each group of calculation modules comprises 3 8-bit binary multipliers (the input of which is an array of R, G, B components of a data block respectively), 3 8-bit complement adders and subtractors and 3 registers, and is used for realizing YCbCr color space conversion;
a sample memory (RAM) for storing the converted YCbCr data;
And the second address generator generates a head address of the left upper corner of each block according to the size of 2x2 blocks according to the converted YCbCr data, and the read operation module reads the YCbCr data from the RAM for downsampling according to the data block address generated by the second address generator. In this embodiment, the downsampling is performed in a 4:2:0 mode, so as to reduce the storage space occupied by the image as much as possible.
The downsampling unit further comprises an output buffer module, and a FIFO buffer is adopted for buffering the downsampled image data.
In this embodiment, the downsampling unit performs the operations of color space conversion and chroma information downsampling based on an 8-bit binary computing manner, and compared with a scheme of performing picture compression by using software to perform 32-bit floating point number computation, the scheme greatly reduces the occupation of computing resources, reduces the computing power consumption, and improves the image compression efficiency.
In one embodiment, the second address generator may generate corresponding first address data according to different data block sizes. It is noted that the size of the data block needs to be able to divide the size of 2x 2. For example, the second address generator may be configured to generate a first address based on a data block size of 4×4, and the read operation module may read YCbCr data of a corresponding size from the RAM based on the size. Taking the size of 2x2 and the size of 4x4 as examples, the data block size according to which the first address is generated by the second address generator is properly enlarged, so that the frequency of accessing the RAM by the read operation module is reduced, the occupation of system resources is further reduced, and the image sampling efficiency is improved.
Based on the same inventive concept, an embodiment of the present application provides a pixel sampling method. Referring to fig. 5, fig. 5 is a flowchart of a pixel sampling method according to an embodiment of the application. As shown in fig. 5, the method includes:
S1, initiating a read request to a target image in an external memory through a first address generator according to a preset initial address and a preset termination address, and reading all target data blocks of the target image;
S2, predicting whether a current target data block is identical to a high-frequency data block in a private cache unit according to a current prediction period value, and determining the target data block or the high-frequency data block as a data block to be converted according to a prediction result;
And S3, performing color space conversion and chroma information downsampling on the data block to be converted to obtain a result data block.
As one embodiment of the present application, reading all target data blocks of a target image includes:
sequentially accessing each bus read interface through the first address generator, and initiating a corresponding read request to an external memory;
According to the protocol handshaking signals returned by each bus reading interface, the writing sequence of the target data blocks returned by each bus reading interface is adjusted, and each target data block is sequentially written into the first buffer module according to the adjusted writing sequence.
As an embodiment of the present application, before predicting whether the current target data block is identical to the high frequency data block in the private cache unit, further includes:
determining that the historical image is a high-frequency data block according to the DCT feedback result of the previous historical image, wherein the ratio of the maximum value of pixel frequency to the minimum value of pixel frequency in the high-frequency data block is greater than or equal to a first threshold value;
And adding marks for all the high-frequency data blocks and storing the marks in the private cache unit, wherein the marks comprise frame positions, storage addresses and high-frequency tag numbers.
As one embodiment of the present application, predicting whether a current target data block is identical to a high frequency data block in a private cache unit includes:
Based on the high-frequency tag number, acquiring a corresponding historical data block from the private cache unit;
Reading a prediction period value from the private cache unit, and judging whether the current prediction period value is larger than or equal to a second threshold value;
predicting that the pixel frequency information of the target data block is consistent with the pixel frequency information of the historical data block under the condition that the prediction period value is greater than or equal to a second threshold value;
And writing the historical data block serving as a prediction result into a second cache module.
As one embodiment of the present application, determining the target data block or the high frequency data block as a data block to be converted according to a prediction result includes:
comparing the target data block with the historical data block, and judging whether the pixel frequency information is consistent;
Under the condition that the pixel frequency information is consistent in comparison, taking the predicted data block stored in the second buffer module as a data block to be converted;
and under the condition that the pixel frequency information contrast is inconsistent, writing the target data block serving as the data block to be converted into the second buffer memory module, and covering the predicted data block.
As an embodiment of the present application, the method further comprises:
adding a high-frequency tag number which is the same as the predicted data block to the target data block;
in the case of inconsistent pixel frequency information contrast, the current prediction period value is reduced by 1.
As an embodiment of the present application, the method further comprises:
predicting that pixel frequency information of the target data block and the historical data block is inconsistent under the condition that the prediction period value is smaller than the second threshold value;
And directly writing the target data block into the second cache module.
As an embodiment of the present application, the method further comprises:
and adjusting the access sequence of all the data blocks to be converted in the second buffer module, so that the data blocks to be converted without the high-frequency tag number are preferentially accessed.
As an embodiment of the present application, performing color space conversion on the data block to be converted and downsampling chroma information to obtain a resulting data block, including:
Performing color space conversion on the data block to be converted by adopting a binary algorithm through a calculation module to obtain data to be sampled, and writing the data into a sampling memory;
generating, by a second address generator, a plurality of head addresses based on the second size;
and carrying out chroma information downsampling on the data block to be sampled in the sampling memory according to each head address through a sampling module to obtain a result data block.
Based on the same inventive concept, an embodiment of the present application provides an image compression system. Referring to fig. 6, fig. 6 is a schematic diagram of an image compression system according to an embodiment of the present application. As shown in fig. 6, the system includes:
The pixel sampling apparatus provided in the above embodiment, wherein the downsampling unit further includes a third buffer module, configured to store the result data block;
The compression unit is used for obtaining a result data block from the third buffer module, and performing DCT transformation, quantization and coding compression to obtain a compressed data block;
and transmitting DCT feedback results of all target data blocks of the target image obtained by DCT conversion to a prediction adjustment module in the pixel sampling device.
In this embodiment, the first buffer module (FIFO-0 in FIG. 6), the second buffer module (FIFO-1 in FIG. 6) and the third buffer module (FIFO-2 in FIG. 6) of the pixel sampling device all adopt FIFO structures.
Based on the same inventive concept, an embodiment of the present application provides a readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the pixel sampling method according to any of the above embodiments of the present application.
Based on the same inventive concept, an embodiment of the present application provides an electronic device, including a memory, a processor, and a computer program stored on the memory and capable of running on the processor, wherein the steps in the pixel sampling method according to any one of the above embodiments of the present application are implemented when the processor executes the computer program.
The specific manner in which the various modules perform the operations in relation to the methods of the embodiments described above have been described in detail in relation to the embodiments of the apparatus and will not be described in detail herein.
The foregoing description of the preferred embodiments of the application is not intended to be limiting, but rather is intended to cover all modifications, equivalents, alternatives, and improvements that fall within the spirit and scope of the application.
For the purposes of simplicity of explanation, the methodologies are shown as a series of acts, but one of ordinary skill in the art will recognize that the present application is not limited by the order of acts described, as some acts may, in accordance with the present application, occur in other orders and concurrently. Further, those skilled in the art will recognize that the embodiments described in the specification are all of the preferred embodiments, and that the acts and components referred to are not necessarily required by the present application.
It will be apparent to those skilled in the art that embodiments of the present application may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the application may take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
Embodiments of the present application are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, this application is to be construed as including the preferred embodiments and all such variations and modifications as fall within the scope of the embodiments of the application.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article or terminal device comprising the element.
The pixel sampling apparatus, method and image compression system provided by the present application have been described in detail, and specific examples are provided herein to illustrate the principles and embodiments of the present application, and the above examples are provided to assist in understanding the method and core ideas of the present application, and meanwhile, the present application should not be construed as being limited to the embodiments and application scope of the present application, since modifications will be apparent to those skilled in the art based on the concepts of the present application.
Claims (12)
1. The pixel sampling device is characterized by being connected with an external memory through a system bus and comprising a first address generator, a prediction adjusting unit, a private buffer unit and a downsampling unit;
the first address generator is used for initiating a read request to a target image in the external memory according to a preset initial address and a preset termination address, wherein the read request is used for reading all target data blocks of the target image;
The private caching unit is used for caching the high-frequency data blocks and the corresponding pixel frequency information in the historical images and the prediction period value;
the prediction adjusting unit is used for predicting whether the current target data block is identical to the high-frequency data block in the private cache unit according to the current prediction period value, and determining the target data block or the high-frequency data block as a data block to be converted according to a prediction result;
and the downsampling unit is used for performing color space conversion on the data block to be converted and downsampling the chromaticity information to obtain a result data block.
2. The pixel sampling apparatus according to claim 1, further comprising at least one bus read interface, a bus arbiter, and a first buffer module;
The first address generator is further configured to sequentially access each bus read interface, and initiate a corresponding read request to the external memory;
the bus arbiter is used for adjusting the writing sequence of the target data blocks returned by each bus reading interface according to the protocol handshake signals returned by each bus reading interface;
The first buffer module is used for buffering all target data blocks in the target image.
3. The pixel sampling apparatus according to claim 1, further comprising a second buffer module for buffering the data block to be converted;
Before predicting the pixel frequency information of the target data block according to the prediction period value, the prediction adjustment unit is further used for determining that the historical image is a high-frequency data block according to the DCT feedback result of the previous historical image, wherein the ratio of the maximum value of the pixel frequency to the minimum value of the pixel frequency in the high-frequency data block is greater than or equal to a first threshold value;
Predicting the pixel frequency information of the target data block according to the prediction period value, specifically including:
Based on the high-frequency tag number, acquiring a corresponding historical data block from the private cache unit;
Reading a prediction period value from the private cache unit, and judging whether the current prediction period value is larger than or equal to a second threshold value;
predicting that the pixel frequency information of the target data block is consistent with the pixel frequency information of the historical data block under the condition that the prediction period value is greater than or equal to a second threshold value;
and writing the historical data block serving as a prediction result into the second cache module.
4. A pixel sampling apparatus according to claim 3, wherein the prediction adjustment unit is configured to determine the data block to be converted, and specifically comprises:
comparing the target data block with the historical data block, and judging whether the pixel frequency information is consistent;
Under the condition that the pixel frequency information is consistent in comparison, taking the predicted data block stored in the second buffer module as a data block to be converted;
and under the condition that the pixel frequency information contrast is inconsistent, writing the target data block serving as the data block to be converted into the second buffer memory module, and covering the predicted data block.
5. The pixel sampling apparatus according to claim 4, wherein the prediction adjustment unit is further configured to perform the steps of:
adding a high-frequency tag number which is the same as the predicted data block to the target data block;
in the case of inconsistent pixel frequency information contrast, the current prediction period value is reduced by 1.
6. A pixel sampling apparatus according to claim 3, wherein the prediction adjustment unit is further configured to perform the steps of:
predicting that pixel frequency information of the target data block and the historical data block is inconsistent under the condition that the prediction period value is smaller than the second threshold value;
And directly writing the target data block into the second cache module.
7. The pixel sampling apparatus according to claim 3, wherein the prediction adjustment unit is further configured to adjust an access sequence of all the data blocks to be converted in the second buffer module, so that the data blocks to be converted without the high-frequency tag number are preferentially accessed.
8. The pixel sampling apparatus according to claim 1, wherein the downsampling unit comprises:
The computing module is used for carrying out color space conversion on the data block to be converted by adopting a binary algorithm to obtain data to be sampled, and comprises a shift register, an 8-bit multiplier, an 8-bit complement adder-subtractor and a register;
the sampling memory is used for buffering data to be sampled, wherein every two data to be sampled are stored in a combined mode;
The sampling module comprises a reading operation module and a second address generator, wherein the second address generator is used for generating a plurality of head addresses based on a second size, and the reading operation module is used for downsampling chromaticity information of a data block to be sampled in the sampling memory according to each head address to obtain a result data block.
9. A pixel sampling method, characterized in that it is based on a pixel sampling apparatus according to any one of claims 1-7, comprising:
Initiating a read request to a target image in an external memory according to a preset initial address and a preset termination address by a first address generator, and reading all target data blocks of the target image;
predicting whether a current target data block is the same as a high-frequency data block in a private cache unit according to a current prediction period value, and determining the target data block or the high-frequency data block as a data block to be converted according to a prediction result;
and performing color space conversion and chroma information downsampling on the data block to be converted to obtain a result data block.
10. An image compression system, comprising:
The pixel sampling apparatus according to any one of claims 1-8, wherein the downsampling unit further comprises a third buffer module for storing the resulting data block;
The compression unit is used for obtaining a result data block from the third buffer module, and performing DCT transformation, quantization and coding compression to obtain a compressed data block;
and transmitting DCT feedback results of all target data blocks of the target image obtained by DCT conversion to a prediction adjustment module in the pixel sampling device.
11. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method of claim 9.
12. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor performs the steps in the method as claimed in claim 9 when the computer program is executed.
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