CN119051826A

CN119051826A - 10GBase-T physical layer synchronization and equalization method and device

Info

Publication number: CN119051826A
Application number: CN202410401750.3A
Authority: CN
Inventors: 李浩洋; 朱俊; 管旭东; 何大治; 徐胤; 管云峰
Original assignee: Shanghai Jiao Tong University
Current assignee: Shanghai Jiao Tong University
Priority date: 2024-04-03
Filing date: 2024-04-03
Publication date: 2024-11-29

Abstract

The present invention provides a 10GBase-T physical layer synchronization and equalization method and device, which utilizes the iterative interaction between a multi-state equalizer and a PN synchronization algorithm to realize the rapid capture of a PN training sequence in PN synchronization; at the same time, the multi-state equalization method in the equalizer has a high degree of multiplexing and inheritance characteristics of equalization training results in hardware, which can greatly reduce the hardware overhead of synchronization and equalization modules in 10GBase-T and significantly improve the convergence speed of equalization training; further, as the training of the filter coefficients in the equalizer converges, the quality of the equalization output signal continues to improve, and the equalization output result continues to be used as the input of the PN synchronization module, which will further improve the stability of PN synchronization tracking and reduce the probability of out-of-step.

Description

10GBase-T physical layer synchronization and equalization method and device

Technical Field

The invention relates to the technical field of physical layer algorithm development of 10GBase-T IP chips, in particular to a 10GBase-T physical layer synchronization and equalization method and device.

Background

The technology of the wireless communication network is rapidly developed, and a series of new technologies, new standards, new protocols and new devices are developed and upgraded, so that the wireless network rate is gradually surpassed the gigabit rate Ethernet network which is currently mainstream. Accordingly, upgrades to the wired network rates are urgent, and tera ethernet technology has evolved in the above background. The megaethernet (10 GBase-T for short) is a high-speed ethernet technology for transmitting data with a rate of 10Gbps (Gigabit per second), where "—t" represents that the transmission medium is twisted pair, and is one of the most common standards in the 10Gbps rate ethernet technology. In a high rate system of 10GBase-T, accurate signaling is an important performance indicator.

Equalization techniques are techniques for inserting tunable filters into a communication system to correct and compensate for transmission characteristics of the system and to reduce the effects of intersymbol interference. In a 10GBase-T system, the equalizer is required to compensate for the channel transmission impact of the system. To ensure the accuracy of the receiver demodulation signal, the performance requirements of the equalizer design in a 10GBase-T system are very high. The equalizer is divided into a training phase and a data equalization phase. In the training stage, the equalizer mainly uses the local reference sequence generated by the receiver to compare with the transmitter transmission sequence which is received by the equalizer and is affected by the channel transmission, and uses the comparison result to train the filter coefficient required by the filter in the equalizer. And in the data equalization stage, the trained filter coefficients are utilized to equalize the transmission data. Based on this, the acquisition of the local reference sequence by the receiver becomes a necessary condition for the equalization process. The pseudo-random (PN) sequence synchronization technology for realizing the condition plays a vital role in a 10GBase-T communication system.

And in the physical layer training stage of the 10GBase-T system, PN sequences are used as training sequences. The receiver needs to use the PN synchronization technology to achieve the acquisition and signal alignment of PN training sequences to obtain the local reference sequences for training and convergence of the equalizer filter coefficients.

In the IEEE 802.3 standard, the generation of PN sequences in a 10GBase-T system is realized by adopting a 33-bit shift register, the initial value of the register is often a random value, and in the generation of PN sequences, the periodic reset of the register value is not usually carried out. This feature makes it impossible for the receiver to predict in advance the initial time and the 33-bit register values in the transmitter PN sequence generator at the current time, and thus to obtain the local reference sequence directly.

For this purpose, the receiver first needs to achieve data acquisition in the PN generation register, i.e. acquisition of the PN training sequence, without any a priori information when performing the PN synchronization. In order to achieve this acquisition, it is necessary to ensure that the input data of the PN synchronization algorithm has phase information substantially identical to the transmitted training sequence, i.e. no excessive phase errors. However, the high-speed baud rate makes the 10GBase-T system extremely sensitive to the influence of the twisted pair transmission characteristics, and brings a large amount of phase errors to the received data of the receiver, so that the system cannot be directly applied to the register data capture of the PN sequence. In order to improve the input data quality of the PN synchronization algorithm and reduce the phase error, one possible method is to add a pre-equalization operation before PN synchronization, but at the same time, the conventional equalization process requires a local reference sequence provided by the PN synchronization algorithm after the correct synchronization is achieved. Therefore, in order to realize the correct receiving of the physical layer of the 10GBase-T system, PN synchronization and equalization processing of the system need to be combined. However, the IEEE 802.3 standard does not explicitly propose a specific solution. Therefore, it is urgent to develop a set of algorithm and device for combining PN synchronization and equalization of 10GBase-T system.

Patent document CN114826843a discloses a blind equalization method, device and blind equalizer for high-order quadrature amplitude modulation signals, which obtains prior probabilities based on a plurality of constant modulus values of the high-order quadrature amplitude modulation signals, selects sample sets of different modulus values according to error sequencing of observation signals and constant modulus value signals, combines the prior probabilities, aggregates the plurality of sample sets of different modulus values into a final sample, constructs a cost function under a high-order quadrature amplitude modulation channel according to a classical constant modulus algorithm and the selected sample sets, constructs an iterative formula of the high-order quadrature amplitude modulation channel method according to a newton method, and optimizes the channel blind equalizer.

In conventional approaches, separate designs are typically used to separate PN synchronization from equalization. PN synchronization in order to achieve the capture of register values, a separate preprocessing module needs to be provided. After the PN synchronization is successful, the equalizer designed independently starts to train the equalizing coefficient. Compared with the combined algorithm proposal provided by the invention, the traditional method has obvious disadvantages in equalizer convergence speed and hardware logic overhead. Meanwhile, as the channel transmission compensation capability of the PN synchronization preprocessing module is far inferior to that of an equalizer, the quality of an input signal of PN synchronization cannot be further improved after the first register value acquisition is successfully realized, and compared with the joint processing method provided by the invention, the PN synchronization preprocessing module has higher step-out probability in the follow-up PN synchronization tracking.

Disclosure of Invention

Aiming at the defects in the prior art, the invention aims to provide a 10GBase-T physical layer synchronization and equalization method and device.

The 10GBase-T physical layer synchronization and equalization method provided by the invention comprises the following steps:

Step 1, a multi-state Equalizer performs a first equalization state operation on a baseband received signal subjected to first preprocessing, wherein the first equalization state operation adopts a Linear Equalizer (LE) based on a constant modulus blind equalization (CMA: constant Modulus Algorithm) algorithm to perform equalization;

And 2, enabling the multi-state equalizer to enter a second equalization state, adopting a decision feedback equalization (DFE: decision Feedback Equalizer) state based on a blind equalization algorithm CMA, and continuing training convergence based on the first state equalizer coefficient. Wherein, the second equilibrium state is not an essential step of the invention, the multi-state equalizer can skip the step 2 and directly carry out the step 3;

And 3, along with the continuous improvement of the quality of the output signal of the multi-state equalizer, the phase error is continuously reduced, and the PN synchronization module finally realizes the successful capture of the generation register and the successful generation of the local reference signal. At this time, the PN synchronization module outputs a local reference sequence to the multi-state equalizer, and notifies the multi-state equalizer to enter a third equalization state, namely, the DFE state is equalized by adopting a decision feedback of a least mean square algorithm (LMS: LEAST MEAN square), the multi-state equalizer is based on the second state equalizer coefficient, and the equalization coefficient training based on the LMS algorithm is performed by utilizing the local reference sequence;

And 4, when the output signal quality of the multi-state equalizer reaches a preset threshold, the far-end transmitter starts THP (Tomlinson-HARASHIMA PRECODING) precoding, and the multi-state equalizer enters a fourth equalization state, namely LE linear equalization processing and THP decoding based on an LMS algorithm. The function of the THP precoding of the far-end transmitter is to pre-set the processing of the feedback filter in the decision feedback equalizer of the receiver to the far-end transmitter, and when the THP precoding is started, the multi-state equalizer of the receiver is backed off from the DFE equalizing structure to the LE equalizing structure. When the quality of the equalization result meets the decoding requirement of an 802.3 physical coding sublayer (PCS: physical Coding Sublayer), the system transits to a data transmission stage, and a receiver realizes correct decoding of the PCS.

Preferably, the first preprocessing includes near-end crosstalk cancellation, far-end crosstalk cancellation, echo interference cancellation, and the like, and the cancellation process uses a baseband signal generated by the own transmitter as a reference.

Preferably, in the transmitter, the generation of a training sequence and the generation of a data signal are included, wherein the former generates a PAM2 modulation signal and the latter generates a PAM16 modulation signal after PCS coding according to the 802.3 standard. The modulated signal is processed by the THP encoder, transmitted as a transmitter baseband signal to the radio frequency front end, and transmitted over a transmission medium.

Preferably, in the receiver, the radio frequency front end obtains a receiving signal on a transmission medium, the receiving signal is subjected to analog-to-digital conversion operation to obtain a baseband signal of the receiver, the baseband signal is subjected to interference elimination operation, the signal after interference elimination enters a multi-state equalizer, multi-state equalization processing is performed, an output result is used as an input of a PN synchronization module, the PN synchronization module captures a PN generation register value by using the result of the multi-state equalizer, a local reference sequence is obtained, the local reference sequence is fed back to the multi-state equalizer, a signaling part in a training sequence is simultaneously extracted, an output result of the multi-state equalizer is simultaneously used as an input of a PCS decoder and a sampling deviation SFO (Sampling clock Frequency Offset) estimator of the receiver, and the PCS decoding result is a data bit stream and is transmitted to an XGMII interface.

Preferably, the CMA equalization algorithm is implemented as shown in equation (1) Cheng Ru, where e (n) is an error signal, z (n) is an equalizer output signal, R is an autocorrelation matrix, s (n) is an independently distributed transmit signal, y (n) is a receiver receive signal, J is a cost function, W (n) is an equalizer weight vector, and μ is a step size;

preferably, the LMS equalization algorithm uses the error between the local reference sequence and the received sequence to achieve convergence of the equalizer filter coefficient by using a minimum mean square error criterion, and the implementation process is shown in formula (2), where X (n) is an input vector and d (n) is a local reference signal;

preferably, the linear equalizer LE filters the received signal through an adaptive linear filter to implement equalization processing, wherein coefficient training and convergence of the adaptive linear filter are performed based on the blind equalization algorithm CMA or LMS equalization algorithm;

Preferably, the decision feedback equalizer DFE is divided into an adaptive feedforward filter and an adaptive feedback filter, the coefficient convergence of which is based on the blind equalization algorithm CMA or LMS equalization algorithm described above.

The 10GBase-T physical layer synchronization and equalization device provided by the invention comprises the following components:

the module M1 is used for realizing multi-state equalization processing based on a CMA equalization algorithm, an LMS equalization algorithm, an LE equalization structure and a DFE equalization structure and THP decoding processing;

the module M2 is a PN synchronizer, which utilizes the output result of the multi-state equalizer to capture PN training sequences and generate local reference sequences for training and processing the multi-state equalizer;

interaction and iteration exist between the module M1 and the module M2, and the module M1 realizes switching of various equilibrium states according to the processing state of the module M2.

Compared with the prior art, the invention has the following beneficial effects:

The invention provides a PN synchronization and equalization combined algorithm scheme, which utilizes iterative interaction of a multi-state equalizer and a PN synchronization algorithm to realize rapid capture of register data in PN synchronization, meanwhile, the multi-state equalization method in the equalizer has higher multiplexing degree and inheritance characteristics of equalization training results on hardware, can greatly reduce hardware expenditure of synchronization and equalization modules in 10GBase-T, obviously improves convergence rate of equalization training, and further, continuously improves quality of equalization output signals along with training convergence of filter coefficients in the equalizer, takes the equalization output results as input of the PN synchronization module, and can further improve stability of the PN synchronization module and reduce out-of-step probability.

Drawings

Other features, objects and advantages of the present invention will become more apparent upon reading of the detailed description of non-limiting embodiments, given with reference to the accompanying drawings in which:

FIG. 1 is a schematic diagram of a 10GBase-T overall algorithm design incorporating the apparatus and process of the present invention;

FIG. 2 is a multi-state equalizer state transition example 1;

FIG. 3 is a multi-state equalizer state transition example 2;

FIG. 4 is a block diagram of a linear equalizer LE;

fig. 5 is a block diagram of a DFE of the decision feedback equalizer.

Detailed Description

The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the present invention, but are not intended to limit the invention in any way. It should be noted that variations and modifications could be made by those skilled in the art without departing from the inventive concept. These are all within the scope of the present invention.

Fig. 1 is a schematic diagram of a10 GBase-T overall algorithm architecture incorporating the apparatus and process of the present invention, wherein the 10GBase-T physical layer process is a full duplex process, i.e., includes a transmitter process and a receiver process.

The transmitter processing includes training sequence generation and data signal generation. Wherein, according to the 802.3 standard, the former generates a PAM2 modulation signal, and the latter generates a PAM16 modulation signal after PCS coding. The modulated signal is processed by the THP encoder and then transmitted as a transmitter baseband signal to the radio frequency front end for transmission over a transmission medium.

In the receiver processing, the radio frequency front end obtains a receiving signal on a transmission medium, and the receiving signal is subjected to analog-to-digital conversion and other operations to obtain a baseband signal of the receiver. The baseband signal first needs to undergo interference cancellation operations, including near-end crosstalk cancellation, far-end crosstalk cancellation, echo interference cancellation, and the like, and the cancellation process needs to use the baseband signal generated by the own transmitter as a reference. The signal after interference elimination enters a multi-state equalizer to perform multi-state equalization processing, and the output result is used as the input of the PN synchronization module. The PN synchronization module captures the PN generation register value by utilizing the result of the multi-state equalizer, obtains a local reference sequence, feeds back to the multi-state equalizer, and simultaneously extracts a signaling part in the training sequence. The output of the multi-state equalizer is used as input to both the receiver PCS decoder and the sampling offset SFO estimator. The PCS decoding result is the data bit stream and is transmitted to the XGMII interface.

The core invention of the invention is the joint design of the multi-state equalizer and the PN synchronization module. The steps of the specific embodiment are as follows:

example 1:

Step 1, a multi-state equalizer performs a first-state equalization operation on a baseband received signal subjected to a first preprocessing (including interference cancellation and the like). The first equalization state is equalized by using a linear equalizer LE based on a constant modulus blind equalization CMA algorithm. The blind equalization CMA algorithm uses the high order statistics of the signal to train the initial filter coefficients without the need for assistance from a local reference sequence. The PN synchronization module captures PN generation registers and generates local reference signals by utilizing the output result of the multi-state equalizer.

And 2, along with the training convergence of the equalization filter coefficient in the CMA-LE, the quality of the CMA-LE output result is continuously improved, and the constellation diagram can be basically distinguished. At this time, the multi-state equalizer is switched to a second equalization state, namely, the decision feedback equalization DFE state based on the blind equalization CMA algorithm is adopted, and training and convergence are continued based on the first state equalizer coefficient, so that the quality of the equalizer output signal is further improved.

And 3, along with the continuous improvement of the quality of the output signal of the multi-state equalizer, the phase error is continuously reduced, and the PN synchronization module finally realizes the successful capture of the generation register and the successful generation of the local reference signal. At this time, the PN synchronization module outputs a local reference sequence to the multi-state equalizer and informs the multi-state equalizer to enter a third equalization state, namely, a DFE equalization state adopting a least mean square LMS algorithm. At this time, the multi-state equalizer uses the local reference sequence to perform the equalization coefficient training based on the LMS algorithm based on the second state equalizer coefficient, so as to further improve the quality of the equalizer output signal.

And 4, when the quality of the output signal of the multi-state equalizer reaches a preset threshold, the remote transmitter starts THP precoding. At this time, the multi-state equalizer performs fourth equalization state, that is, LE linear equalization processing and THP decoding based on the LMS algorithm. The function of the THP precoding of the far-end transmitter is to pre-set the processing of the feedback filter in the decision feedback equalizer of the receiver to the far-end transmitter, so that after the THP precoding is started, the multi-state equalizer of the receiver needs to fall back from the DFE equalizing structure to the LE equalizing structure.

Finally, when the quality of the equalization result meets the PCS decoding requirement, the system transits to a data transmission stage, and the receiver can realize correct decoding of the PCS.

In the implementation steps, the state switching process of the multi-state equalizer is shown in fig. 2.

Another preferred embodiment of the present invention is realized by deleting the second state equalization based on the above embodiment, as follows:

Example 2:

step 1, a multi-state equalizer performs a first-state equalization operation on a baseband received signal subjected to a first preprocessing (including interference cancellation and the like). The first equalization state is equalized by an LE equalizer based on a CMA algorithm. The CMA algorithm uses the higher order statistics of the signal to train the initial filter coefficients without the need for assistance from a local reference sequence. The PN synchronization module captures PN generation registers and generates local reference signals by utilizing the output result of the multi-state equalizer.

And 2, along with the training convergence of the equalization filter coefficient in the CMA-LE, the quality of the CMA-LE output result is continuously improved, the phase error is continuously reduced, and the PN synchronization module can finally realize the successful capture of the generation register and the successful generation of the local reference signal. At this time, the PN synchronization module outputs a local reference sequence to the multi-state equalizer and informs the multi-state equalizer to enter a second equalization state, i.e., a DFE equalization state using an LMS algorithm. At this time, the multi-state equalizer uses the local reference sequence to perform equalization coefficient training based on the LMS criterion based on the first state equalizer coefficient, so as to further improve the equalizer output signal quality.

And 3, when the quality of the output signal of the multi-state equalizer reaches a preset threshold, the remote transmitter starts THP precoding. At this time, the multi-state equalizer performs a third equalization state, i.e., LE linear equalization processing and THP decoding based on the LMS criterion.

In the implementation steps, the state switching process of the multi-state equalizer is shown in fig. 3.

In the above process, the principle of CMA equalization is as follows:

CMA blind equalization is an algorithm that can implement the equalization process using only the received signal and its higher order statistical properties without the need for a local reference sequence.

The implementation process of the CMA algorithm is shown in a formula (1);

Where e (n) is the error signal, z (n) is the equalizer output signal, R is the autocorrelation matrix, s (n) is the independently distributed transmit signal, y (n) is the receiver receive signal, J is the cost function, W (n) is the equalizer weight vector, and μ is the step size. The implementation process of the LMS equalization is shown in a formula (2);

wherein X (n) is an input vector and d (n) is a local reference signal.

The LE linear equalizer is structured as shown in fig. 4, and filters the received signal by an adaptive filter to implement equalization processing. The coefficient training and convergence of the adaptive filter may be based on the CMA blind equalization algorithm or the LMS equalization algorithm.

The DFE decision feedback equalizer is divided into an adaptive feedforward filter and an adaptive feedback filter as shown in fig. 5, and the coefficient convergence can be performed based on the CMA blind equalization algorithm or the LMS equalization algorithm.

The processing principles and processes of THP encoding and decoding are as described in standard 802.3 an.

Example 3:

The invention also provides a 10GBase-T physical layer synchronization and equalization device, which can be realized by executing the flow steps of the 10GBase-T physical layer synchronization and equalization method, namely, a person skilled in the art can understand the 10GBase-T physical layer synchronization and equalization method as a preferred implementation mode of the 10GBase-T physical layer synchronization and equalization device.

interaction and iteration exist between the module M1 and the module M2, and the module M1 realizes switching of various equilibrium states according to the processing state of the module M2;

The specific processing and state switching procedures of the modules M1 and M2 can be realized by the above-described embodiments 1 and 2.

Those skilled in the art will appreciate that the systems, apparatus, and their respective modules provided herein may be implemented entirely by logic programming of method steps such that the systems, apparatus, and their respective modules are implemented as logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers, etc., in addition to the systems, apparatus, and their respective modules being implemented as pure computer readable program code. Therefore, the system, the device and the respective modules thereof provided by the invention can be regarded as a hardware component, and the modules for realizing various programs included therein can be regarded as a structure in the hardware component, and the modules for realizing various functions can be regarded as a structure in the hardware component as well as a software program for realizing the method.

The foregoing describes specific embodiments of the present application. It is to be understood that the application is not limited to the particular embodiments described above, and that various changes or modifications may be made by those skilled in the art within the scope of the appended claims without affecting the spirit of the application. The embodiments of the application and the features of the embodiments may be combined with each other arbitrarily without conflict.

Claims

1. A 10GBase-T physical layer synchronization and equalization method, characterized by comprising:

Step 1: The multi-state equalizer uses a first equalization state to perform equalization processing on the baseband received data that has undergone the first preprocessing, and the equalization result is used for PN synchronization processing;

Step 2: PN synchronization processing uses the output result of the multi-state equalizer to capture the PN training sequence. After successfully capturing the PN training sequence, the generated local PN reference sequence is fed back to the multi-state equalizer;

Step 3: After receiving feedback of the local PN reference sequence, the multi-state equalizer switches to the second equalization state and uses the local PN reference sequence to assist the equalizer in further training and processing.

2. The 10GBase-T physical layer synchronization and equalization method according to claim 1, wherein the first equalization state uses a constant modulus blind equalization CMA algorithm to train and process the equalizer;

The first equalization state includes one sub-state: a linear equalization processing state using a CMA algorithm;

Or, the first equalization state includes two sub-states: the first sub-state is: a linear equalization processing state using a CMA algorithm; the second sub-state is: a decision feedback equalization processing state using a CMA algorithm.

3. The 10GBase-T physical layer synchronization and equalization method according to claim 1, characterized in that the second equalization state uses a local PN reference sequence-assisted least mean square LMS algorithm to train and process the equalizer;

The second equalization state includes two sub-states: the first sub-state is a decision feedback equalization processing state using the LMS algorithm; the second sub-state is a linear equalization processing and THP decoding processing state using the LMS algorithm.

4. The 10GBase-T physical layer synchronization and balancing method according to claim 1 is characterized in that the multi-state equalizer may inherit the balancing coefficient obtained in the previous state or may not inherit the balancing coefficient obtained in the previous state when the state is switched.

5. The 10GBase-T physical layer synchronization and equalization method according to claim 1 is characterized in that the first preprocessing includes: echo interference elimination, and/or near-end interference elimination, and/or far-end interference elimination processing.

6. A 10GBase-T physical layer synchronization and equalization device, characterized in that it comprises: a multi-state equalizer and a PN synchronizer;

The multi-state equalizer performs equalization processing on the baseband received data after the first preprocessing, and outputs the first state equalization result to the PN synchronizer for capturing the PN training sequence;

After successfully capturing the PN training sequence, the PN synchronizer feeds back the generated local PN reference sequence to the multi-state equalizer for equalization training and processing of the second state of the multi-state equalizer.

7. The 10GBase-T physical layer synchronization and equalization device according to claim 6, characterized in that the first equalization state uses a constant modulus blind equalization CMA algorithm to train and process the equalizer;

8. The 10GBase-T physical layer synchronization and equalization device according to claim 6, characterized in that the second equalization state uses a local PN reference sequence assisted least mean square (LMS) algorithm to train and process the equalizer;

9. The 10GBase-T physical layer synchronization and balancing device according to claim 6 is characterized in that the multi-state equalizer may inherit the balancing coefficient obtained in the previous state or may not inherit the balancing coefficient obtained in the previous state when the state is switched.

10. The 10GBase-T physical layer synchronization and equalization device according to claim 1, characterized in that the first preprocessor comprises: an echo interference canceller, and/or a near-end interference canceller, and/or a far-end interference canceller.