CN119051675B - Transmitter driving circuit - Google Patents
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- CN119051675B CN119051675B CN202410116365.4A CN202410116365A CN119051675B CN 119051675 B CN119051675 B CN 119051675B CN 202410116365 A CN202410116365 A CN 202410116365A CN 119051675 B CN119051675 B CN 119051675B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/02—Transmitters
- H04B1/04—Circuits
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- H—ELECTRICITY
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Abstract
本申请涉及电子电路技术领域，公开了一种发射机驱动电路，包括：主驱动阵列电路，包括：第一前抽头驱动单元电路组，第一主抽头驱动单元电路组，第一后抽头驱动单元电路组；输出阻抗校准阵列电路，包括：与第一前抽头、主抽头和后抽头驱动单元电路组分别连接的第二前抽头、第二主抽头和第二后抽头驱动单元电路组；输出阻抗校准控制电路，用于向第二前抽头、第二主抽头和第二后抽头驱动单元电路组分别发送数字控制信号；第一和第二前抽头、主抽头、后抽头驱动单元电路组分别包含多个驱动单元电路，并且，第一和第二前抽头、主抽头、后抽头驱动单元电路组所包含的驱动单元电路的数量比例关系均为k。本申请能够有效提高信号的线性度和信噪比。
The present application relates to the technical field of electronic circuits, and discloses a transmitter driving circuit, including: a main driving array circuit, including: a first front tap driving unit circuit group, a first main tap driving unit circuit group, and a first rear tap driving unit circuit group; an output impedance calibration array circuit, including: a second front tap, a second main tap, and a second rear tap driving unit circuit group respectively connected to the first front tap, the main tap, and the rear tap driving unit circuit group; an output impedance calibration control circuit, for sending digital control signals to the second front tap, the second main tap, and the second rear tap driving unit circuit group respectively; the first and second front tap, main tap, and rear tap driving unit circuit groups respectively include a plurality of driving unit circuits, and the number ratio of the driving unit circuits included in the first and second front tap, main tap, and rear tap driving unit circuit groups is k. The present application can effectively improve the linearity and signal-to-noise ratio of the signal.
Description
Technical Field
The application relates to the technical field of electronic circuits, in particular to a transmitter driving circuit design.
Background
Due to the low-pass filtering characteristics of the transmission line, different frequency components may suffer from different levels of attenuation during high-speed data signal transmission. This attenuation occurs during the transmission from the serial Transmitter (TX) to the Receiver (RX), resulting in severe Inter-symbol interference (Inter-Symbol Interference, ISI) of the signal received by the receiver, which directly affects the decision capability of the receiver for the current bit data. To reduce the impact of such low-pass transmission characteristics, receivers typically employ a variety of equalization methods, including continuous-time linear equalization (CTLE), decision Feedback Equalization (DFE), digital Signal Processing (DSP), and the like. Meanwhile, in order to reduce the pressure of the receiver equalization process, the serial transmitter typically performs a feed-forward equalization process (FFE) on the transmission signal, as shown in fig. 1.
However, while the above measures can mitigate inter-symbol interference and transmission loss to some extent, these solutions still face the problem of insufficient signal linearity and signal-to-noise ratio (SNDR) in high-speed data transmission. The lack of linearity can lead to distortion of signal waveform, increase error rate, and low signal-to-noise ratio can reduce the ability of the receiver to detect signals, further affecting accuracy and reliability of data transmission. Therefore, although various measures are taken in the prior art to improve the signal transmission quality, in high-speed serial communication, improving the linearity and the signal-to-noise ratio of the signal is still a technical problem to be solved.
Disclosure of Invention
The present application is directed to a transmitter driving circuit, which solves the above-mentioned problems.
The application discloses a transmitter driving circuit, comprising:
a main drive array circuit including a first front tap drive unit circuit group, a first main tap drive unit circuit group, and a first rear tap drive unit circuit group, wherein each group includes a plurality of drive unit circuits;
The output impedance calibration array circuit comprises a second front tap drive unit circuit group, a second main tap drive unit circuit group and a second rear tap drive unit circuit group, wherein each group is connected with a corresponding group in the main drive array circuit;
an output impedance calibration control circuit for transmitting digital control signals to the second front tap, the second main tap, and the second rear tap drive unit circuit group, respectively;
The number of the driving unit circuits included in the second front tap, the second main tap and the second rear tap driving unit circuit group is k times of the number of the driving unit circuits corresponding to the first front tap, the first main tap and the first rear tap driving unit circuit group respectively, k is a constant smaller than 1, and the digital control signal is used for adjusting the value of k so as to accurately adjust the output impedance of the transmitter.
In a preferred embodiment, the output impedance calibration control circuit includes:
A voltage detection unit for detecting a voltage in a series or parallel circuit formed by the main drive array circuit and the reference resistor, the unit capturing a voltage value from the divided voltage of the main drive array and the reference resistor;
the voltage comparison unit is used for comparing the output voltage Vout detected by the voltage detection unit with the reference voltage Vref and generating a comparison result;
And the control signal generating unit is used for generating a digital control signal according to the comparison result of the voltage comparison unit, so that the output characteristic of the circuit is adjusted according to the comparison condition of the output voltage Vout and the reference voltage Vref, and the expected output impedance calibration is realized.
In a preferred embodiment, each drive unit circuit of the first front tap drive unit circuit group in the main drive array circuit is connected in one-to-one correspondence with a corresponding second front tap drive unit circuit in the output impedance calibration array circuit;
Each driving unit circuit of a first main tap driving unit circuit group in the main driving array circuit is connected with a corresponding second main tap driving unit circuit in the output impedance calibration array circuit in a one-to-one correspondence manner;
Each drive unit circuit of the first back tap drive unit circuit group in the main drive array circuit is connected with a corresponding second back tap drive unit circuit in the output impedance calibration array circuit in a one-to-one correspondence.
In a preferred embodiment, the first front tap, the main tap and the rear tap driving unit circuit group in the main driving array circuit are correspondingly connected in parallel with the second front tap, the main tap and the rear tap driving unit circuit group in the output impedance calibration array circuit respectively;
the first front tap driving unit circuit group is connected with the corresponding second front tap driving unit circuit group in parallel to drive the front tap data signals;
The first main tap driving unit circuit group is connected with the corresponding second main tap driving unit circuit group in parallel to drive the main tap data signals;
The first set of rear tap drive unit circuits is connected in parallel with a corresponding second set of rear tap drive unit circuits to drive the rear tap data signals.
In a preferred embodiment, the digital control signal is in the form of a multi-bit binary code, and the high-low level combination of each binary bit represents different control states for controlling the conduction conditions of the second front tap, the second main tap and the second rear tap driving unit circuit group in the output impedance calibration array circuit.
In a preferred embodiment, the main driving array circuit and the output impedance calibration array circuit are connected in parallel, the output impedance calibration array circuit is used for calibrating the output impedance of the transmitter, and the main driving array circuit and the output impedance calibration array circuit are used for driving the output signal of the transmitter together.
In a preferred embodiment, the digital control signal output by the output impedance calibration control circuit includes a multi-bit binary code, and the bit number of the binary code is the same as the number of the driving unit circuits in the output impedance calibration array circuit, so as to perform independent switch control on each driving unit circuit.
In a preferred embodiment, the output impedance calibration control circuit is connected to the output impedance calibration array circuit through a digital interface, and the digital interface is used for transmitting digital control signals.
Compared with the prior art, the embodiment of the application has the following technical differences:
Firstly, an independent output impedance calibration array is adopted, and compared with the traditional scheme, the output impedance calibration array circuit is separated from a main driving array circuit, so that the working state of the driving unit circuit is not influenced by the calibration circuit.
Further, a main drive array circuit is employed that includes multiple front taps, main taps, and back tap drive cell circuits. These circuits are configured in parallel, which can provide flexible equalization processing.
Furthermore, the innovative design of the output impedance calibration control circuit is adopted, and the circuit generates a digital control signal according to a specific voltage detection result and is used for controlling the output impedance calibration array circuit so as to realize accurate impedance calibration.
The transmitter driving circuit according to the present application has the following technical effects:
Firstly, the linearity of signal transmission is improved, namely, the output linearity of a transmitter is maintained through independent impedance calibration, and the problem of linearity caused by the change of the resistance ratio of an MOS tube and a poly resistor in the traditional method is solved.
Furthermore, the signal-to-noise ratio (SNDR) and the spurious-free dynamic range (SFDR) of the signals are improved, the simulation result shows that the signal-to-noise ratio of the output signals is improved from 31.99dB to 34.76dB, the improvement is 2.7d, the spurious-free dynamic range of the output signals is improved from 31.74dB to 41.53dB, the improvement is 6.79dB, and the performance is better than that of the traditional method.
Further, the interference of the analog control signal is prevented, namely, the switch of the output impedance calibration array is controlled by the digital control word, so that the interference possibly caused by the analog control signal is avoided.
The application realizes output impedance calibration and ensures the linearity of the transmitter through the accurate control of the digital control signal, and has obvious technical advantages and effects.
The numerous technical features described in the description of the present application are distributed among the various technical solutions, which can make the description too lengthy if all possible combinations of technical features of the present application (i.e., technical solutions) are to be listed. In order to avoid this problem, the technical features disclosed in the above summary of the application, the technical features disclosed in the following embodiments and examples, and the technical features disclosed in the drawings may be freely combined with each other to constitute various new technical solutions (these technical solutions are regarded as already described in the present specification) unless such a combination of technical features is technically impossible. For example, in one example, feature a+b+c is disclosed, in another example, feature a+b+d+e is disclosed, and features C and D are equivalent technical means that perform the same function, technically only by alternative use, and may not be adopted simultaneously, feature E may be technically combined with feature C, and then the solution of a+b+c+d should not be considered as already described because of technical impossibility, and the solution of a+b+c+e should be considered as already described.
Drawings
FIG. 1 is a schematic diagram of a prior art transmitter driving circuit;
Fig. 2 is a schematic diagram of a structure of a transmitter driving circuit according to a first embodiment of the present application;
fig. 3 to 5 are schematic diagrams of a transmitter driving unit circuit of a transmitter driving circuit according to a first embodiment of the present application;
fig. 6 is a diagram of transmitter output resistance calibration of a transmitter driving circuit according to a first embodiment of the application;
FIG. 7 is a schematic diagram of the output signal DFT of a conventional calibration method;
Fig. 8 is a schematic diagram of the output signal DFT of the transmitter driving circuit according to the first embodiment of the application.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. It will be understood by those skilled in the art that the claimed application may be practiced without these specific details and with various changes and modifications from the embodiments that follow.
Description of the partial concepts:
Front tap data (pre data) refers to the original serial data signal that has not passed through the delay cell.
Main tap data (main data) refers to a serial data signal passing through a one-stage delay unit.
Post data refers to a serial data signal that passes through the two-stage delay unit.
Feed Forward Equalization (FFE) compensates the signal by introducing different degrees of advance to the signal to improve the integrity of the signal during transmission.
Output impedance is the equivalent impedance of the transmitter to the output. Matching the impedance of the transmitter and the transmission line can maximize signal transmission efficiency.
Inter-symbol interference (ISI), interference between adjacent symbols due to transmission. The high frequency signal is severely attenuated, and the transmission quality is degraded.
Signal-to-noise ratio (SNR), which is the ratio of signal power to noise power, represents an indicator of whether the signal quality is good or bad. The larger the value, the better the signal quality.
Spurious Free Dynamic Range (SFDR), the dynamic range between maximum signal and maximum spurious. Indicating the linearity and purity of the signal.
The following outline of some of the innovative features of the present application:
After long-term research and analysis, the inventor of the application finds that the traditional output impedance calibration can change the proportion relation between the on-resistance and the calibration resistance of the MOS tube, thereby causing the linearity of the transmitter to be poor. Specifically, the objective of conventional output impedance calibration is to control the sum of the on-resistance (ron_ mosp/ron_ mosn) of the MOS transistor and the resistance of the polysilicon resistor (r_poly) to be constant, so as to meet the requirement of the output impedance of the transmitter. However, after such calibration, the ratio of the on-resistance of the MOS transistor to the resistance of the polysilicon (Ron_ mosp/R_poly) or (Ron_ mosn/R_poly) will change. Such variations in the ratio can lead to poor linearity of the transmitter due to process variations in the CMOS chip, adversely affecting signal quality. The technical scheme of the application aims to solve the technical problem of poor linearity of the transmitter caused by the traditional output impedance calibration mode, and ensures that the linearity of the transmitter is unchanged or improved while realizing the output impedance calibration through a novel circuit structure and a control mode. The application adopts an independent output impedance calibration array, which is characterized in that the output impedance calibration array is separated from the main driving array, thus ensuring that the normal operation of the main driving circuit is not interfered in the calibration process. Furthermore, the application optimizes the main drive array circuit, which comprises a plurality of drive units of front tap, main tap and rear tap, and the units work in parallel, thus providing flexible equalization processing capability for the transmission process. Furthermore, the application provides an output impedance calibration control circuit, which adjusts an output impedance calibration array based on a voltage detection result by using a digital control signal to realize accurate control.
The application solves the technical problems that firstly, the linearity of signal transmission is improved, and the linearity of a traditional serial transmitter driving circuit is reduced due to the change of the resistance ratio of an MOS tube and a poly resistor. The independent output impedance calibration of the present application effectively solves this problem, preserving the linearity of the output signal. Furthermore, the signal-to-noise ratio (SNDR) and the spurious-free dynamic range (SFDR) of the signal are improved, and the signal-to-noise ratio and the spurious-free dynamic range of the output signal are obviously improved through optimized equalization processing and accurate impedance calibration, so that the transmission quality is improved. Furthermore, the interference of the analog control signal is reduced, namely, the output impedance calibration is controlled by adopting a digital control method, so that the interference problem possibly caused by the analog control signal is reduced. While the output impedance calibration is completed, as the taps of the first and second driving units maintain the same proportional relationship, each step size of the FFE remains unchanged, and the minimum equalization step size required by the protocol can still be satisfied. In general, the present application provides an optimized serial transmitter driver circuit design that significantly improves the performance of high-speed data transmission, particularly in terms of linearity and signal-to-noise ratio, through innovative impedance calibration and equalization processing techniques.
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
A first embodiment of the present application relates to a transmitter driving circuit having a structure as shown in fig. 2 to 6, and the transmitter driving circuit of the present embodiment includes a main driving array circuit, an output impedance calibration array circuit, and an output impedance calibration control circuit. In the scheme, the output impedance calibration array is separated from the main drive array circuit, and the working state of the drive unit circuit is not influenced by the calibration circuit.
In general, the main drive array circuit includes a first front tap drive unit circuit group, a first main tap drive unit circuit group, and a first rear tap drive unit circuit group, each of which includes a plurality of drive unit circuits.
Further, the output impedance calibration array circuit includes a second front tap drive cell circuit group, a second main tap drive cell circuit group, and a second rear tap drive cell circuit group, each of which is connected to a corresponding group in the main drive array circuit.
Further, the output impedance calibration control circuit is used for respectively sending digital control signals to the second front tap, the second main tap and the second rear tap driving unit circuit group, and comprises a voltage detection unit, a voltage comparison unit and a control signal generation unit, wherein the voltage detection unit is used for detecting voltages in a series or parallel circuit formed by the main driving array circuit and the reference resistor, the voltage detection unit is used for capturing voltage values of partial voltages of the main driving array and the reference resistor, the voltage comparison unit is used for comparing the output voltage Vout detected by the voltage detection unit with the reference voltage Vref and generating comparison results, and the control signal generation unit is used for generating digital control signals according to the comparison results of the voltage comparison unit, so that the output characteristics of the circuit are adjusted according to the comparison condition of the output voltage Vout and the reference voltage Vref, and expected output impedance calibration is achieved.
Further, the number proportion relation of the driving unit circuits included in the first front tap, the second front tap, the main tap and the rear tap driving unit circuit group is k, k is a constant smaller than 1, and the digital control signal is used for adjusting the value of k so as to adjust the output impedance of the transmitter. In other words, the number of driving unit circuits included in the second front tap, the second main tap, and the second rear tap driving unit circuit group is k times the number of corresponding driving unit circuits in the first front tap, the first main tap, and the first rear tap driving unit circuit group, respectively.
More specifically, in the transmitter driving circuit of the present application, there are two key sets of circuit components, a first set and a second set. The two groups respectively comprise a front tap, a main tap and a rear tap driving unit circuit group. Each group contains a plurality of drive unit circuits, but the number of drive unit circuits in the two groups is different. "k" is a constant used to describe the quantitative ratio between the two groups. Specifically, "k" is a value smaller than 1, representing the ratio of the number of drive unit circuits in the second group (second front tap, second main tap, second rear tap drive unit circuit group) to the number in the first group (first front tap, first main tap, first rear tap drive unit circuit group). For example, if k is 0.5, this means that the number of circuits of each driving unit circuit group in the second group is half of that of the corresponding circuit group of the first group. The function of the digital control signal is to adjust the value of this ratio k. By varying the value of k, the output impedance of the transmitter can be adjusted. k defines the proportional relationship of the number of circuits in the first and second sets of drive unit circuits. By adjusting the value of k, the output impedance of the transmitter can be finely controlled to optimize its performance.
Optionally, each driving unit circuit of the first front tap driving unit circuit group in the main driving array circuit is connected with a corresponding second front tap driving unit circuit in the output impedance calibration array circuit in a one-to-one correspondence manner, each driving unit circuit of the first main tap driving unit circuit group in the main driving array circuit is connected with a corresponding second main tap driving unit circuit in the output impedance calibration array circuit in a one-to-one correspondence manner, and each driving unit circuit of the first rear tap driving unit circuit group in the main driving array circuit is connected with a corresponding second rear tap driving unit circuit in the output impedance calibration array circuit in a one-to-one correspondence manner.
Optionally, a first front tap, a main tap and a rear tap driving unit circuit group in the main driving array circuit are correspondingly connected in parallel with a second front tap, a main tap and a rear tap driving unit circuit group in the output impedance calibration array circuit respectively, the first front tap driving unit circuit group is connected in parallel with the corresponding second front tap driving unit circuit group to drive front tap data signals, the first main tap driving unit circuit group is connected in parallel with the corresponding second main tap driving unit circuit group to drive main tap data signals, and the first rear tap driving unit circuit group is connected in parallel with the corresponding second rear tap driving unit circuit group to drive rear tap data signals.
Optionally, the digital control signal is in the form of multi-bit binary code, and the high-low level combination of each binary bit represents different control states and is used for controlling the conduction condition of the second front tap, the second main tap and the second rear tap driving unit circuit group in the output impedance calibration array circuit.
Optionally, the digital control signal output by the output impedance calibration control circuit includes a multi-bit binary code, where the number of bits of the binary code is the same as the number of driving unit circuits in the output impedance calibration array circuit, and the digital control signal is used to perform independent switch control on each driving unit circuit.
Optionally, the output impedance calibration control circuit is connected with the output impedance calibration array circuit through a digital interface, and the digital interface is used for transmitting a digital control signal.
The configuration of the transmitter driving circuit of the present embodiment will be described in more detail.
Main drive array circuit
The main drive array circuit includes m parts of pre data, n parts of main data and p parts of post data drive unit circuits.
Wherein, pre data refers to front tap data and refers to serial data signals which do not pass through a delay unit. main data refers to main tap data, and refers to serial data signals passing through a primary delay unit. post data refers to post tap data, and refers to a serial data signal passing through two stages of delay units.
The Pre/main/post data driving circuit forms a feedforward equalization processing (FFE) circuit, and the purpose of signal equalization is achieved through the processing of attenuating low-frequency signals and increasing high-frequency signals.
Specifically, the main drive array circuit includes m parallel front tap drive cell circuits (pre data), n parallel main tap drive cell circuits (main data) and p parallel rear tap drive cell circuits (post data).
The m parallel front tap driving unit circuits, the n parallel main tap driving unit circuits and the p parallel rear tap driving unit circuits respectively form a first front tap driving unit circuit group, a first main tap driving unit circuit group and a first rear tap driving unit circuit group.
Output impedance calibration array circuit
The output impedance calibration array circuit is created in this embodiment, specifically, the output impedance calibration array circuit includes m×k parts pre data, n×k parts main data and p×k parts post data driving unit circuits.
In other words, the output impedance calibration array circuit includes m×k parts of the parallel front tap drive unit circuit (pre data), n×k parts of the parallel main tap drive unit circuit (main data), and p×k parts of the parallel rear tap drive unit circuit (post data).
The m x k parts of parallel front tap driving unit circuits, n x k parts of parallel main tap driving unit circuits and p x k parts of parallel rear balance driving unit circuits respectively form a second front tap driving unit circuit group, a second main tap driving unit circuit group and a second rear tap driving unit circuit group.
And the first front tap driving unit circuit group is connected with the second front tap driving unit circuit group in parallel, the first main tap driving unit circuit group is connected with the second main tap driving unit circuit group in parallel, and the first rear tap driving unit circuit group is connected with the second rear tap driving unit circuit group in parallel.
Wherein the output impedance calibration parameter k is a constant less than 1. Assuming that after output impedance calibration, the output impedance calibration array circuit is turned on m×r parts of pre data, n×r parts of main data and p×r parts of post data unit circuits (r < =k), respectively, and when equalization processing is implemented, the numbers of pre data, main data and post data driving units are m× 1+r, n× 1+r and p× 1+r, respectively, and the mutual ratio is still m: n: p. In this way, after impedance calibration, the amplitude of the output signal can be kept constant, and meanwhile, each TAP (post/main/pre) of the FFE is simultaneously introduced with a resistor calibration unit array, so that each step length of the FFE is kept unchanged, thereby meeting the minimum equalization step length required by a protocol.
That is, k is used to adjust the number of turns on of the driving unit circuits in the output impedance calibration array circuit. Specifically:
Impedance calibration when the output impedance calibration array circuit performs impedance calibration, it selectively turns on a specific number of drive unit circuits based on a scale factor r (r is less than or equal to k). Here, "m×r portion pre data", "n×r portion main data" and "p×r portion post data" unit circuits refer to the number of additional driving units that are turned on according to the impedance calibration requirement.
Equalization processing, namely, when equalization processing is realized, the number of pre data, main data and post data driving units is increased to m (1+r), n (1+r) and p (1+r) respectively, so that the original m: n: p ratio is kept unchanged.
Stabilization of the output signal and equalization step sizes by this method, the output signal amplitude can be kept constant while the impedance calibration is accomplished, and it is ensured that each TAP (post/main/pre) of the Feed Forward Equalization (FFE) incorporates an array of resistive calibration cells, so that each step size of the FFE remains unchanged. This is important because it meets the protocol's requirements for a minimum equalization step size.
In general, this design allows the proportion and efficiency of the equalization process to be maintained by adjusting the number of cells in the impedance calibration circuit while ensuring stability of the output signal and compliance with protocol requirements.
Output impedance calibration control circuit
The present embodiment innovatively adds an output impedance calibration control circuit for detecting the divided voltage signal Vout after the transmitter driving unit and the off-chip reference resistor are connected in series and comparing it with the reference voltage Vref to generate a digital control signal. The digital control signals are respectively sent into a second front tap, a main tap and a rear tap driving unit group in the output impedance calibration array circuit, and the switches of the driving units in the groups are controlled to realize accurate output impedance adjustment.
Alternatively, the output impedance calibration control circuit may employ a circuit configuration as shown in FIG. 6, which includes a voltage detection circuit and a voltage comparison circuit. The voltage detection circuit obtains a voltage detection value Vout by connecting the transmitter driving unit and an off-chip reference resistor in series. The voltage comparing circuit compares Vout with a reference voltage Vref, outputs a high level control signal if Vout is higher than Vref, and outputs a low level control signal if Vout is lower than Vref. The high-low level control signals in the digital form enter the front tap, the main tap and the rear tap driving unit groups corresponding to the output impedance calibration array circuit, and the transistor switches in the driving unit groups are controlled to be conducted or not so as to adjust the number of the driving units, thereby realizing accurate output impedance calibration. In summary, the circuit dynamically adjusts the number of the on-states of the driving units in the output impedance calibration array circuit in a voltage detection and digital control mode, so as to achieve the purpose of output impedance calibration, and enable the transmitter to work in an optimal state. The design ensures that the detection, comparison, control and other modules are cooperatively matched, so that the output impedance can be accurately regulated, and the operation of a transmitter driving circuit is efficient and stable.
Transmitter unit driving circuit
Transmitter unit drive circuitry is a critical component designed to process and condition serial data signals for efficient transmission. It generally includes a plurality of tap drive units, such as front tap, main tap and rear tap drive units, which may be in a parallel or series configuration. The driving units work cooperatively to improve the transmission efficiency and quality of the signals and reduce the attenuation and distortion of the signals in the transmission process.
Alternatively, the transmitter unit driving circuit may be implemented in fig. 3, fig. 4, fig. 5, or other manners, and it should be noted that Rswp in fig. 3 and fig. 4 represents a PMOS switch resistor, ronp represents a PMOS on-resistance, rmosp represents a PMOS tube resistor, ronn represents an NMOS on-resistance, rswn represents an NMOS switch resistor, rmosn represents an NMOS tube resistor, rpoly represents a polysilicon calibration resistor, enb_drv represents a driving unit enable signal, and en_drv represents a driving unit on-control signal. Vb_ swp in fig. 5 represents a PMOS bias voltage, and vb_ swn represents an NMOS bias voltage.
Off-chip reference resistor
The off-chip reference resistor is an independent component externally connected with the transmitter driving circuit and is used for providing an accurate resistance reference value for the circuit.
Specifically, it is connected to the outside of the transmitter driving circuit, and is connected to the output impedance calibration control circuit to supply the detection voltage to the voltage detection circuit of the latter.
In voltage detection, one end of the reference resistor is grounded, and the other end of the reference resistor outputs a stable detection voltage signal Vout to the voltage detection circuit.
The voltage detection circuit is used for connecting the transmitter driving unit and the reference resistor in series and feeding the detected serial voltage division voltage value Vout value into the voltage comparison circuit. The voltage comparison circuit compares and decides Vout and reference voltage Vref to generate digital control signals. The digital control signal is then fed into an output impedance calibration array circuit to adjust the output impedance of the transmitter.
In summary, the off-chip reference resistor provides a precise reference resistor for the transmitter driving circuit, and the reference function is to ensure the accuracy and stability of the output impedance calibration. It is a key component to achieve accurate output impedance calibration.
Working principle:
The transmitter driving circuit of the above embodiment performs signal conditioning and equalization processing by a series of driving unit circuits to accommodate the requirement of high-speed data transmission. The front tap, main tap and rear tap drive units cooperate through a parallel arrangement to compensate for losses and distortion of the signal during transmission. The output impedance calibration array circuit dynamically adjusts the working state of each driving unit according to the real-time performance of the circuit and an external reference standard by utilizing a digital control signal so as to accurately match the impedance of a transmission line. The adjustment ensures the integrity and stability of the signal in the transmission process, reduces inter-code crosstalk and improves the accuracy and reliability of data transmission. In addition, the off-chip reference resistor provides a stable reference point for the system, is used for calibrating the internal resistance value, and ensures the consistency of circuit output. The design of the whole circuit optimizes the linearity and the signal-to-noise ratio of signals and ensures the stable performance under different working conditions and loads.
The specific working procedure of the transmitter driving circuit of the above embodiment is as follows:
The pre-driving circuit carries out different delay processing on the input data signals to obtain front tap, main tap and rear tap data, and feedforward equalization of the signals is realized.
The driving units in the output impedance calibration array circuit correspond to the driving units of the main driving array circuit according to a certain proportion relation. Wherein the switch of the driving unit is controlled by an output impedance calibration control circuit.
The output impedance calibration control circuit compares the detection result Vout with the reference voltage Vref by detecting the voltage of the series division of the main drive circuit and the reference resistance voltage to obtain a switching control signal of the drive unit.
The control signal turns on or off the corresponding drive unit switch to adjust the quantity proportion of the drive units in the main drive array circuit and the output impedance calibration array circuit, so that the calibration of the output impedance is realized.
After calibration, the stability of the amplitude and the equalization step length of the output signal and the constancy of the proportional relation of the resistance values between the MOS resistor and the poly resistor can be ensured, thereby achieving the purpose of improving the linearity of the transmitter.
The technical effects are as follows:
The goal of conventional output impedance calibration circuits is to control the sum of Rmosp +rpoly and Rmosn +rpoly resistances to remain constant to meet the transmitter output impedance index requirements. However, after calibration, the ratio of on-resistance to poly-resistance (Rmosp/Rpoly or Rmosn/Rpoly) of the MOS transistor may change, which may result in poor linearity of the transmitter at some process angles.
The transmitter driving circuit of the above embodiment of the present application obtains a digital control word through the calibration circuit to control whether the switch of the additional output impedance calibration array circuit is turned on. Therefore, the interference possibly caused by the analog control signal can be avoided, and meanwhile, the resistance ratio of the on-resistance of the MOS tube to the poly-resistance is kept constant, so that the output of the transmitter is kept constant in linearity.
More specifically, the output impedance calibration control circuit precisely controls the switching of the driving unit in the output impedance calibration array circuit according to the voltage detection result. So that the number proportional relationship of the driving units in the main driving array circuit and the output impedance calibration array circuit is kept constant. Therefore, the proportional relation among all links of feedforward equalization can be ensured to be unchanged, and the final output signal amplitude can be stabilized by increasing a driving unit provided by a calibration array circuit. The linearity of the transmitter is improved while the output impedance calibration is satisfied.
Compared with the traditional analog control mode, the method and the device realize output impedance calibration and ensure the linearity of the transmitter through accurate control of the digital control signals, and have obvious technical advantages and effects.
Simulation results:
In order to verify the performance of the circuit, a simulation comparison experiment is performed. Fig. 7 is a spectrum of a transmitter output signal when using a conventional calibration method. Fig. 8 is a spectrum of the transmitter output signal when the novel method of the present application is used. As is apparent from fig. 7 and 8, under the same test conditions:
The signal-to-noise ratio (SNDR) of the output signal of the present application is 34.76dB, whereas the conventional method is 31.99dB. This shows that the new approach achieves a significant improvement in signal-to-noise ratio of 2.77 dB.
The Spurious Free Dynamic Range (SFDR) of the output signal of the present application is 41.53dB, whereas the conventional method is 34.74dB. This shows that the new approach achieves a significant improvement in spurious free dynamic range of 6.79 dB.
The relative amplitude of each subharmonic of the output signal relative to the fundamental wave is obviously lower, and the schematic linearity is improved.
In summary, the simulation results prove that compared with the conventional technology, the transmitter driving circuit provided by the application has significantly improved linearity and signal-to-noise ratio. This further demonstrates the effectiveness of the circuit architecture and control strategy of the present application.
In general, embodiments of the present application have the following technical improvements:
Firstly, an independent output impedance calibration array is adopted, and compared with the traditional scheme, the output impedance calibration array circuit is separated from a main driving array circuit, so that the working state of the driving unit circuit is not influenced by the calibration circuit.
Further, a main drive array circuit is employed that includes multiple front taps, main taps, and back tap drive cell circuits. These circuits are configured in parallel, which can provide flexible equalization processing.
Furthermore, the innovative design of the output impedance calibration control circuit is adopted, and the circuit generates a digital control signal according to a specific voltage detection result and is used for controlling the output impedance calibration array circuit so as to realize accurate impedance calibration.
The transmitter driving circuit according to the present application has the following technical effects:
Firstly, the linearity of signal transmission is improved, namely, the output linearity of a transmitter is maintained through independent impedance calibration, and the problem of linearity caused by the change of the resistance ratio of an MOS tube and a poly resistor in the traditional method is solved.
Furthermore, the signal-to-noise ratio (SNDR) and the spurious-free dynamic range (SFDR) of the signals are improved, the simulation result shows that the signal-to-noise ratio of the output signals is improved from 31.99dB to 34.76dB, the improvement is 2.7d, the spurious-free dynamic range of the output signals is improved from 31.74dB to 41.53dB, the improvement is 6.79dB, and the performance is better than that of the traditional method.
Further, the interference of the analog control signal is prevented, namely, the switch of the output impedance calibration array is controlled by the digital control word, so that the interference possibly caused by the analog control signal is avoided.
While the impedance calibration is completed, as the taps of the first and second driving units maintain the same proportional relationship, each step size of the FFE remains unchanged, and the minimum equalization step size required by the protocol can still be satisfied.
It should be noted that in the present patent application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. In the present patent application, if it is mentioned that an action is performed according to an element, it means that the action is performed according to at least the element, and includes both cases that the action is performed according to only the element and that the action is performed according to the element and other elements. Multiple, etc. expressions include 2, 2 times, 2, and 2 or more, 2 or more times, 2 or more.
All references mentioned in this disclosure are to be considered as being included in the disclosure of the application in its entirety so that modifications may be made as necessary. Further, it is understood that various changes or modifications of the present application may be made by those skilled in the art after reading the above disclosure, and such equivalents are intended to fall within the scope of the application as claimed.
Claims (6)
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| CN109729295A (en) * | 2018-12-19 | 2019-05-07 | 芯原微电子(上海)有限公司 | Transmitter drive circuit and method |
| CN111525966A (en) * | 2020-05-07 | 2020-08-11 | 江苏集萃智能集成电路设计技术研究所有限公司 | Impedance calibration circuit applied to transmitter |
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| CN109729295A (en) * | 2018-12-19 | 2019-05-07 | 芯原微电子(上海)有限公司 | Transmitter drive circuit and method |
| CN111525966A (en) * | 2020-05-07 | 2020-08-11 | 江苏集萃智能集成电路设计技术研究所有限公司 | Impedance calibration circuit applied to transmitter |
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