CN119047384A - Compiling method and device for chip verification and computing equipment - Google Patents
Compiling method and device for chip verification and computing equipment Download PDFInfo
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Abstract
The invention belongs to the technical field of chip verification, and provides a compiling method, a compiling device and computing equipment for chip verification, wherein the method comprises the steps of generating a corresponding compiling source file based on a verification environment according to a configuration instruction from a user; the method comprises the steps of adopting a corresponding script according to the identification result of a compiling source file, rendering the compiling source file into a compiling base file, reading the compiling base file to generate a compiling sequence, wherein the compiling sequence comprises target addressing and target content, mapping all the compiling sequences to target parts corresponding to the target addressing in a verification environment respectively, and endowing the target content to the target parts. The scheme supports the designer to write the compiling source file, takes the compiling sequence as a unit after identification and rendering, adopts a mapping method to modify the value of the target piece nested in the verification environment, omits the time of the whole compiling verification environment, and accelerates the chip verification efficiency.
Description
Technical Field
The invention belongs to the technical field of chip verification, and particularly relates to a compiling method, a compiling device and computing equipment for chip verification.
Background
In recent years, as the chip scale is enlarged, the chip design is also more and more complex, and in order to support diversified functions, the chip is often required to be configured with more and more registers. The conventional chip verification process is usually to write an integral verification code, compile the integral experience verification code, and assign the compiled files to registers in a verification environment in sequence for simulation execution.
With the increase of the number of registers in the chip, the frequency of modifying the register value required for verifying the chip increases, and compiling and assigning of the verification environment are required to be performed again for each modifying of the register value, so that the verification efficiency is low. Moreover, since the register configuration code is often nested in the verification environment (test sequence), it is difficult for a technician who is not familiar with the verification platform to find the original configuration value corresponding to the target register from the verification environment and replace the original configuration value with the configuration value when modifying the register value.
Accordingly, there is a need to provide a compiling method and a computing device for chip verification to solve the above-mentioned problems existing in the prior art.
Disclosure of Invention
In order to solve the problems of poor accuracy of change and low adaptation efficiency in the prior art, when technicians adjust the value of a target register, compiling and assigning of a verification environment are required to be carried out again, the application provides a compiling method, a compiling device and a computing device for chip verification.
The compiling method, the compiling device and the calculating equipment for chip verification provided by the application adopt the following technical scheme:
A compilation method for chip verification, the method comprising:
based on the verification environment, generating a corresponding compiled source file according to a configuration instruction from a user;
Rendering the compiled source file into a compiled base file by adopting a corresponding script according to the identification result of the compiled source file;
reading the compiling base file to generate a compiling sequence, wherein the compiling sequence comprises target addressing and target content;
And mapping all compiling sequences to target pieces corresponding to the target addresses in the verification environment respectively, and endowing the target contents to the target pieces.
By adopting the technical scheme, under the verification environment, the compiling source file is generated according to the configuration instruction of the user, and the compiling source file supports multiplexing (such as macro code groups or built-in functions and the like) under the verification environment, so that the editing threshold is reduced. And then, running the compiled source file by adopting a script corresponding to the compiled source file to obtain a compiled base file, so as to realize the rendering of the compiled source file. And then the compiling sequence in the compiling foundation file which is rendered and compiled is mapped into the verification environment according to the sequence, so that the verification environment can perform simulation execution conveniently. And after the compiling source file is compiled by a support designer, the compiling sequence is taken as a unit, and a mapping method is adopted to modify the value of a target piece nested in the verification environment, so that the time of the integral compiling verification environment is omitted, and the chip verification efficiency is accelerated.
Optionally, before generating the corresponding compiled source file according to the configuration instruction from the user based on the verification environment, the method further includes:
Importing an SV general file library in a verification environment, so that the compiled source file generated in the verification environment can call built-in functions in the SV general file library.
By adopting the technical scheme, the SV general file library is imported in the verification environment, so that when a user generates a compiled source file in the verification environment, the built-in function in the SV general file library is directly called, the compiled source file is ensured to support multiplexing of codes and functions in various forms, and the difficulty of compiling the source file in the verification environment by the user through configuration instructions is greatly reduced.
Optionally, the generating the corresponding compiled source file according to the configuration instruction from the user includes:
And selecting a corresponding engine template according to the configuration instruction, and generating a compiled source file according to a code instruction and a calling instruction in the configuration instruction, wherein the calling instruction is used for calling a macro code group in the engine template and a built-in function of the verification environment.
By adopting the technical scheme, after the user selects the engine template through the configuration instruction, the native code corresponding to the code instruction in the configuration instruction is filled into the engine template, and the macro code set and the built-in function called by the calling instruction are also filled into the engine template. The scheme supports the compiling of the source file reference macro code set and the built-in function, reduces the writing amount of the compiling source file dom, and increases the reusability of codes.
Optionally, when the engine template is a Python engine template, the compiled source file is generated according to jinjia language.
By adopting the technical scheme, the jinjia language is a special engine in the Python engine template, when the compiled source file is generated, the characteristics of the jinja language can be utilized to write the configuration of the register into the compiled source file according to a three-segment (for example, register level-register name-register value) method so as to facilitate the subsequent assignment of target content to corresponding target pieces according to target addressing.
Optionally, rendering the compiled source file into a compiled base file by adopting a corresponding script according to the identification result of the compiled source file, including:
And identifying an engine template of the compiled source file, and rendering the compiled source file by using a script corresponding to the engine template to obtain a compiled base file composed of basic elements.
By adopting the technical scheme, the script corresponding to the engine template is used for running the compiling source file to obtain the compiling base file. And running the macro code set and the built-in function in the compiled source file by adopting a script, and taking the running result as a part of the compiled base file.
Optionally, reading the compiling base file to generate a compiling sequence includes:
and reading the compiling base file row by row to generate a compiling sequence corresponding to each row, wherein the compiling sequence comprises a register level, a register name and a register value which are mutually related, or an identifier address, an identifier name and an identifier value which are mutually related.
By adopting the technical scheme, each line of codes for reading the compiling base file is taken as a compiling sequence. The compiled sequence of register levels, register names, and register values indicates that a mapping assignment update is to be performed to registers in the verification environment. A compiled sequence of identifier addresses, identifier names, identifier values indicates that mapping assignment updates are made to identifiers in the verification environment.
Optionally, mapping all compiled sequences to a target piece corresponding to the target address in the verification environment, and assigning the target content to the target piece, including:
Where the compilation sequence includes a register hierarchy, a register name and a register value,
And matching corresponding target registers in a character string pool in the verification environment according to the register level and the register name, discarding the read compiling sequence when the target registers do not exist, reading the next compiling sequence, and giving the register value to the target registers when the target registers exist.
By adopting the technical scheme, when mapping assignment is carried out on the register level, the register name and the register value which are mutually related in the compiling sequence, if a target register in the verification environment can be locked according to the register level and the register name, the register value is directly mapped into the target register to be used as a value, and if the target register in the verification environment cannot be locked according to the register level and the register name, the compiling sequence is directly discarded, and the compiling sequence of the next row in the compiling base file is read.
Optionally, after mapping all compiled sequences to the target parts corresponding to the target addresses in the verification environment, the method further includes:
And screening the registers which are not assigned in the character string pool as pending registers, and sequentially assigning unique random values to the pending registers.
By adopting the technical scheme, after all compiling sequences are mapped to the verification environment, checking whether the character string pool has unassigned registers or not, taking the unassigned registers as pending registers, generating random numbers, and assigning the random numbers to the pending registers. And each register is ensured to be endowed with a new value, so that the registers in the character string pool are prevented from using a default value for a long time, and interference faults occur in the verification environment when simulation operation is performed.
Optionally, mapping all compiled sequences to a target piece corresponding to the target address in the verification environment, and assigning the target content to the target piece, including:
where the compiled sequence includes an identifier address, an identifier name and an identifier value,
And according to the identifier address and the identifier name, matching a target identifier in the verification environment, and endowing the identifier value to the target identifier.
By adopting the technical scheme, the compiling sequence can also carry out assignment mapping on the identifiers in the verification environment, so that the application range is improved.
The invention also provides a compiling device for chip verification, which comprises an instruction acquisition unit, a writing unit, an identification unit, a rendering unit, a reading unit and a mapping matching unit;
The instruction acquisition unit is used for acquiring a configuration instruction from a user;
the compiling unit is used for generating a corresponding compiling source file under the verification environment according to the configuration instruction;
the identifying unit is used for identifying the compiled source file and designating a corresponding script;
The rendering unit is used for rendering the compiled source file according to the script to obtain a compiled base file;
the reading unit is used for reading the compiling basic file and generating a compiling sequence, and the compiling sequence comprises target addressing and target content;
and the mapping matching unit is used for mapping all compiling sequences to target pieces corresponding to the target addresses in the verification environment respectively, and endowing the target contents to the target pieces.
Optionally, the compiling device further comprises a register complement unit;
And the register complement unit is used for screening the register which is not assigned in the character string pool in the verification environment as a pending register after mapping all compiling sequences to the target parts corresponding to the target addresses in the verification environment respectively, and assigning a unique random value to the pending register.
A computing device comprising a processor and a memory storing a computer program that, when executed by the processor, causes the processor to perform a compiling method for chip verification as described above.
In summary, the present application includes at least one of the following beneficial technical effects:
1. The scheme generates the compiled source file in the verification environment, has simple writing, supports the reference macro code group, also supports the direct calling of the built-in function in the verification environment, reduces the writing amount of the compiled source file dom, and increases the reusability of codes.
2. The designer can automatically generate a compiling source file through editing the configuration instruction, render and analyze the compiling source file into a compiling base file, and then register mapping is carried out according to the compiling sequence of each row, so that the recompilation time of the verification environment is saved, the verification efficiency is quickened, and the designer is facilitated to directly modify the register value.
3. The scheme not only can carry out mapping modification on register values, but also can carry out mapping modification on the values of identifiers in the verification environment.
4. After mapping is completed on all compiling sequences in the compiling basic file, undetermined registers which are not assigned in a character string pool in the verification environment are further screened, random numbers are assigned to the undetermined registers, and the condition that the registers in the character string pool use default values for a long time is avoided, so that interference faults occur when the verification environment performs simulation operation is avoided.
Drawings
FIG. 1 is a flowchart of a compiling method for chip verification according to a first embodiment of the invention;
FIG. 2 is a schematic diagram of the verification environment of FIG. 1;
FIG. 3 is a schematic block diagram of a compiling apparatus for chip verification according to a second embodiment of the invention;
fig. 4 is a schematic structural diagram of a computing device according to a third embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention. Unless otherwise defined, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and the like means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof without precluding other elements or items.
First embodiment:
The first embodiment of the invention provides a compiling method for chip verification, which is applied to a chip verification environment. Referring to fig. 1, the compiling method for chip verification includes the steps of:
Based on the verification environment, generating a corresponding compiling source file according to a configuration instruction from a user, rendering the compiling source file into a compiling base file by adopting a corresponding script according to an identification result of the compiling source file, reading the compiling base file to generate a compiling sequence, wherein the compiling sequence comprises target addressing and target content, mapping all the compiling sequences to target parts corresponding to the target addressing in the verification environment respectively, and endowing the target parts with the target content. A compiled source file is generated in the verification environment according to the configuration instructions of the user, and the compiled source file supports multiplexing (such as macro code groups or built-in functions) in the verification environment, so that the editing threshold is reduced. And mapping the compiling sequence in the compiling foundation file which is completed by rendering and compiling into the verification environment according to the sequence so as to facilitate the verification environment to execute the simulation process.
The implementation details of the compiling method for chip verification according to the present embodiment are specifically described below, and the following details are provided only for facilitating understanding, but are not essential to the present embodiment, and a specific flow is shown in fig. 1, and includes the following steps:
step 101, based on the verification environment, generating a corresponding compiled source file according to a configuration instruction from a user.
In particular, the verification environment generally refers to a test sequence, and typically the verification environment includes a plurality of string pools (one for each functional module) and an identifier, each string pool including at least one register.
Before step 101 is executed, the verification environment is configured, namely, an SV general file library is imported in the verification environment, so that the compiled source file generated in the verification environment can call built-in functions in the SV general file library.
Before editing the compiled source file (i.e. editing configuration instructions for generating the compiled source file in the verification environment), the staff adds the SV general file library into the file list of the compiled file, and simultaneously imports the SV general file library in the verification environment. When editing a compiled source file, a worker inputs configuration instructions to the execution body of step 101 through an SV general database in a file list of the compiled file, wherein the configuration instructions comprise code instructions and calling instructions, and the worker correspondingly writes out the calling instructions for calling the code groups in the SV general file library by checking the SV general file library of the file list of the compiled file, and writes out the calling instructions for the built-in functions in the verification environment through own knowledge of the verification environment. Therefore, the execution body of step 101 can accurately find the corresponding code set in the referenced SV general file library and the built-in function in the verification environment according to the configuration instruction after receiving the configuration instruction from the user.
Specifically, in step 101, generating a corresponding compiled source file according to a configuration instruction from a user includes S1-1, selecting a corresponding engine template according to the configuration instruction, and S1-2, generating a compiled source file according to a code instruction and a calling instruction in the configuration instruction, wherein the calling instruction is used for calling a macro code group in the engine template and a built-in function of the verification environment.
The SV general file library is provided with a plurality of engine templates, the configuration instruction edited by a user comprises three parts, namely an engine template selection instruction, a macro code group and a call instruction of a built-in function, and a code instruction written conventionally and manually, wherein the engine template selection instruction is necessary, and at least one of the call instruction and the code instruction is required.
For this purpose, the specification of the engine template is realized by selecting the corresponding engine template from the SV general file library through the step S1-1. Through step S1-2, generating corresponding native codes according to code instructions in the configuration instructions, generating a macro code group in a call engine template and a call code of a built-in function in a verification environment according to the call instructions in the configuration instructions, filling the native codes and the call code into the engine template, and generating a compiled source file. The scheme supports the compilation of macro code groups and built-in functions for source files, reduces the writing amount of the compiled source files, and increases the reusability of codes. In FIG. 2, the compiled source file is also referred to as a dom file.
Preferably, the engine template is a Python engine template, and the compiled source file is generated according to jinjia language. The jinjia language is a special engine in the Python engine template and has the characteristic of tree structure, and the nodes of the tree structure have three basic forms, namely, mapping, the value of which corresponds to the target part position (such as a register level and an identifier position) to be configured in the verification environment, a sequence, the value of which corresponds to the target part name (such as a register subscript and an identifier name) in the ordered list, and scalar, the value of which corresponds to the target content (such as a register value and an identifier value).
For example, compiled source files generated in jinjia language are:
module_a_reg_ral->register_b->random_randrange (0,3,1)。
module_a_reg_ral->register_c->5。
"Module_a_reg_ral-" represents a register hierarchy, "register_b-" and "register_c-" represent register names, "random_ randrange (0, 3, 1)" and "5" represent register values, where "5" belongs to native code and "random_ randrange (0, 3, 1)" belongs to calling code.
In some examples, the macro code sets are implemented using an automated macro that can directly replicate the part of an existing compiled source file (dom file), perform various syntactic and semantic checks, and then use the part of the compiled source file (dom file) as the source to which the macro code sets refer.
Therefore, each time the macro code set is referenced, grammar and semantic checks are performed to ensure that the generated compiled source file has no semantic problem. And locally displaying the dom file corresponding to the unrecognizable macro code set to a user for the user to correct.
And 102, rendering the compiled source file into a compiled base file by adopting a corresponding script according to the identification result of the compiled source file.
Specifically, the implementation of step 102 includes identifying an engine template of a compiled source file, and rendering the compiled source file by using a script corresponding to the engine template to obtain a compiled base file composed of basic elements.
Since each engine template has a specific style, the engine templates can be accurately identified according to the style of the compiled source file. When the engine template is a Python engine template, the corresponding script in this step is a Python script. The Python script identifies the macro code set and the built-in function according to the specific style of the Python engine template, identifies the macro code set according to { { }, and identifies the built-in function according to the specific character string. For example, random_ randrange (0, 3, 1) is identified as a random valued function in the built-in function.
And rendering the compiled source file by using a script corresponding to the engine template, namely calling the script corresponding to the engine template to run the compiled source file, updating the running result of calling codes (macro code groups in the engine template and built-in functions in the verification environment) in the compiled source file into corresponding target content, and keeping the original codes (code instruction generation) in the compiled source file to obtain a compiled base file of the corresponding compiled source file. For example, the call code "module_a_reg_ral- > register_b- > range_ randrange (0, 3, 1)" in the compiled source file is run using a script, the value 1 is randomized between 0-3 with a step size of 1, then "module_a_reg_ral- > register_b- > range_ randrange (0, 3, 1)" is rendered as "module_a_reg_ral- > register_b- >1", and then, for example, the original code "module_a_reg_ral- > register_c- >5" in the compiled source file remains as "module_a_reg_ral- > register_c- >5" after running using the script.
The step uses the script corresponding to the engine template to run the compiling source file to obtain the compiling base file. And running the macro code set and the built-in function in the compiled source file by adopting a script, and taking the running result as a part of the compiled base file. In fig. 2, the compiled base file is generated by parsing a compiled source file (dom file), and is represented by a dom.out file.
Step 103, reading the compiling base file to generate a compiling sequence, wherein the compiling sequence comprises target addressing and target content.
Specifically, the implementation of step 103 includes reading the compiling base file row by row, generating a compiling sequence corresponding to each row, wherein the compiling sequence includes a register hierarchy, a register name and a register value which are associated with each other, or an identifier address, an identifier name and an identifier value which are associated with each other.
The compiled base file after rendering is read row by row, where "row" refers to a code row, and not a natural row. Each line of code that will read the compiled base file is taken as a compiled sequence. The compiled sequence of register levels, register names, and register values indicates that a mapping assignment update is to be performed to registers in the verification environment. A compiled sequence of identifier addresses, identifier names, identifier values indicates that mapping assignment updates are made to identifiers in the verification environment.
For example, compiling the base file is:
module_a_reg_ral->register_b->1;
module_a_reg_ral->register_c->5。
The number of the compiling sequences generated by reading the compiling base file is two, wherein the first compiling sequence is 'module_a_reg_ral, register_b and 1', and the second compiling sequence is 'module_a_reg_ral, register_c and 5'.
And 104, mapping all the compiling sequences to target pieces corresponding to target addresses in the verification environment respectively, and endowing the target pieces with target contents.
Specifically, the compiling sequence is two, the first is composed of a register hierarchy, a register name and a register value and indicates that the mapping assignment update is performed to the register in the verification environment, and the second is composed of an identifier address, an identifier name and an identifier value and indicates that the mapping assignment update is performed to the identifier in the verification environment.
If the compiling sequence is the first one, step 104 includes, when the compiling sequence includes a register level, a register name and a register value, matching a corresponding target register in a character string pool in the verification environment according to the register level and the register name, discarding the compiling sequence read this time when the target register does not exist, reading the next compiling sequence, and when the target register exists, giving the register value to the target register.
When mapping and assigning the related register level, register name and register value in the compiling sequence, if a target register in the verification environment can be locked according to the register level and the register name, the register value is directly mapped into the target register as a value, if the target register in the verification environment cannot be locked according to the register level and the register name, the compiling sequence is directly discarded, and the compiling sequence of the next row in the compiling base file is read.
For example, referring to fig. 2, the compiling sequence is "module_a_reg_ral, register_b, 1", a corresponding string pool a is found according to the register hierarchy "module_a_reg_ral", a target register b is found from the string pool a according to the register name "register_b", and a register value "1" is assigned to the target register b by mapping. The compiling sequences are 'module_a_reg_ral and register_c and 5', a corresponding character string pool A is found according to the register level 'module_a_reg_ral', a target register c is found from the character string pool A according to the register name 'register_c', and a register value '1' is assigned to the target register c through mapping.
If the compiled sequence is the second type, step 104 includes, when the compiled sequence includes an identifier address, an identifier name, and an identifier value, matching a target identifier in the verification environment according to the identifier address and the identifier name, and assigning the identifier value to the target identifier. Assignment mapping of identifiers in the verification environment is also supported. When the scheme is operated, the method is not limited to mapping register values, and can be used for mapping values after some identifiers in a verification environment are declared by using macro code groups.
And 105, screening the unassigned registers in the character string pool as pending registers, and sequentially assigning unique random values to the pending registers.
Specifically, after all the compiling sequences generated by reading the compiling base file in step 103 are completed in step 104, it is checked whether the string pool corresponding to the register level has any unassigned registers, and these unassigned registers are used as pending registers. Random numbers are generated and assigned to the pending registers.
0065 Referring to fig. 2, for example, the string pool corresponding to the register hierarchy "module_a_reg_ral" is a, which includes register b, register c, and register d, after execution of step 104, register b is assigned 1, register c is assigned 5, register d is assigned, and register d is considered as the pending register. A random number of 9 is generated and the register d is assigned 9. Thereby ensuring that all registers in string pool a are assigned values. And ensuring that the registers in each character string pool are endowed with new values in the character string pools corresponding to all register levels in the compiling basic file, avoiding the registers in the character string pools from using default values for a long time, and interfering each other when the verification environment carries out simulation operation.
The above steps of the various methods are divided, for clarity of description, and may be combined into one step or split into multiple steps when implemented, so long as they include the same logic relationship, and all the steps are within the scope of protection of this patent, and adding insignificant modifications or introducing insignificant designs to the algorithm or the process, but not changing the core designs of the algorithm and the process are within the scope of protection of this patent.
Second embodiment:
A second embodiment of the present invention provides a compiling apparatus for chip verification. Referring to fig. 3, the compiling apparatus for chip verification includes an instruction fetch unit 301, a writing unit 302, an identifying unit 303, a rendering unit 304, a reading unit 305, a map matching unit 306, and a register complement unit 307;
an instruction acquisition unit 301 for acquiring a configuration instruction from a user;
the writing unit 302 is connected with the instruction obtaining unit 301 and is used for generating a corresponding compiling source file under a verification environment according to a configuration instruction;
an identifying unit 303, connected to the writing unit 302, for identifying the compiled source file and designating a corresponding script;
the rendering unit 304 is connected with the writing unit 302 and the identifying unit 303, and is used for rendering the compiled source file according to the script to obtain a compiled base file;
the reading unit 305 is connected with the rendering unit 304 and is used for reading the compiling basic file to generate a compiling sequence, wherein the compiling sequence comprises target addressing and target content;
the mapping matching unit 306 is connected with the reading unit 305 and the target piece, and is used for mapping all the compiling sequences to the target piece corresponding to the target addressing in the verification environment respectively, and giving the target content to the target piece;
And the register complement unit 307 is connected with the target and is used for screening the unassigned registers in the character string pool in the verification environment as pending registers and assigning unique random values to the pending registers.
The scheme generates the compiled source file in the verification environment, supports the quotation of the macro code set and the call of the built-in function, reduces the writing amount of the compiled source file dom, and increases the reusability of codes. When the scheme is used for editing the compiled source file, the compiled source file aiming at the target part is only needed to be written, full-text rewriting is not needed, the recompilation time of the verification environment is omitted, the verification efficiency is improved, and the register value can be directly modified by a designer. The random numbers are assigned to the pending registers, so that the registers in the character string pool are prevented from using default values for a long time, and interference faults occur in the verification environment during simulation operation.
Other implementation details and working manners of the compiling apparatus for chip verification disclosed in the present application are the same as or similar to the compiling method for chip verification described above, and are not described herein.
Third embodiment:
a third embodiment of the invention provides a computing device, referring to fig. 4, comprising a processor 401, and a memory 402 storing a computer program which, when executed by the processor 401, causes the processor 401 to perform a compiling method for chip authentication as described above.
While embodiments of the present invention have been described in detail hereinabove, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. It is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention described herein is capable of other embodiments and of being practiced or of being carried out in various ways.
Claims (11)
1. A compiling method for chip verification, the method comprising:
based on the verification environment, generating a corresponding compiled source file according to a configuration instruction from a user;
Rendering the compiled source file into a compiled base file by adopting a corresponding script according to the identification result of the compiled source file;
reading the compiling base file to generate a compiling sequence, wherein the compiling sequence comprises target addressing and target content;
mapping all compiling sequences to target parts corresponding to the target addresses in the verification environment respectively, and endowing the target contents to the target parts;
Wherein reading the compilation base file to generate a compilation sequence comprises:
Reading the compiling base file row by row to generate a compiling sequence corresponding to each row, wherein the compiling sequence comprises a register level, a register name and a register value which are mutually related to indicate that mapping assignment update is carried out on registers in a verification environment, or,
An associated identifier address, identifier name, and identifier value to indicate a mapping assignment update to an identifier in the verification environment.
2. The compiling method for chip verification according to claim 1, wherein before generating the corresponding compiling source file based on the verification environment according to the configuration instruction from the user, the method further comprises:
Importing an SV general file library in a verification environment, so that the compiled source file generated in the verification environment can call built-in functions in the SV general file library.
3. The compiling method for chip authentication according to claim 1, wherein the generating the corresponding compiling source file according to the configuration instruction from the user comprises:
And selecting a corresponding engine template according to the configuration instruction, and generating a compiled source file according to a code instruction and a calling instruction in the configuration instruction, wherein the calling instruction is used for calling a macro code group in the engine template and a built-in function of the verification environment.
4. A compiling method for a chip verification according to claim 3, wherein when the engine template is a Python engine template, the compiling source file is generated according to jinjia language.
5. A compiling method for chip verification according to claim 3, wherein rendering the compiled source file into a compiled base file using a corresponding script according to the identification result of the compiled source file comprises:
And identifying an engine template of the compiled source file, and rendering the compiled source file by using a script corresponding to the engine template to obtain a compiled base file composed of basic elements.
6. The compiling method for chip verification according to claim 1, wherein mapping all compiling sequences to target pieces corresponding to the target addresses in the verification environment, respectively, and assigning the target contents to the target pieces comprises:
When the compiling sequence comprises a register level, a register name and a register value, matching a corresponding target register in a character string pool in the verification environment according to the register level and the register name, discarding the compiling sequence read this time when the target register does not exist, reading the next compiling sequence, and giving the register value to the target register when the target register exists.
7. The compiling method for chip verification according to claim 6, wherein after mapping all compiling sequences to target pieces corresponding to the target addresses in the verification environment, respectively, the method further comprises:
And screening the registers which are not assigned in the character string pool as pending registers, and sequentially assigning unique random values to the pending registers.
8. The compiling method for chip verification according to claim 1, wherein mapping all compiling sequences to target pieces corresponding to the target addresses in the verification environment, respectively, and assigning the target contents to the target pieces comprises:
When the compiled sequence includes an identifier address, an identifier name, and an identifier value, the identifier value is assigned to a target identifier in the verification environment based on the identifier address and the identifier name matching the target identifier.
9. The compiling device for chip verification is characterized by comprising an instruction acquisition unit, a writing unit, an identification unit, a rendering unit, a reading unit and a mapping matching unit;
The instruction acquisition unit is used for acquiring a configuration instruction from a user;
the compiling unit is used for generating a corresponding compiling source file under the verification environment according to the configuration instruction;
the identifying unit is used for identifying the compiled source file and designating a corresponding script;
The rendering unit is used for rendering the compiled source file according to the script to obtain a compiled base file;
The reading unit is used for reading the compiling base file to generate a compiling sequence, wherein the compiling sequence comprises target addressing and target content, and concretely comprises the step of reading the compiling base file row by row to generate a compiling sequence corresponding to each row, wherein the compiling sequence comprises a register level, a register name and a register value which are mutually related to indicate that mapping assignment update is carried out on a register in a verification environment, or an identifier address, an identifier name and an identifier value which are mutually related to indicate that mapping assignment update is carried out on an identifier in the verification environment;
and the mapping matching unit is used for mapping all compiling sequences to target pieces corresponding to the target addresses in the verification environment respectively, and endowing the target contents to the target pieces.
10. The compiling apparatus for chip authentication according to claim 9, wherein the compiling apparatus further comprises a register complement unit;
And the register complement unit is used for screening the register which is not assigned in the character string pool in the verification environment as a pending register after mapping all compiling sequences to the target parts corresponding to the target addresses in the verification environment respectively, and sequentially assigning a unique random value to the pending register.
11. A computing device, comprising:
Processor, and
A memory storing a computer program which, when executed by the processor, causes the processor to perform the compiling method for chip verification according to any one of claims 1 to 8.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112270149A (en) * | 2020-10-16 | 2021-01-26 | 山东云海国创云计算装备产业创新中心有限公司 | Verification platform automation integration method and system, electronic equipment and storage medium |
| US11062077B1 (en) * | 2019-06-24 | 2021-07-13 | Amazon Technologies, Inc. | Bit-reduced verification for memory arrays |
| CN113722163A (en) * | 2021-08-20 | 2021-11-30 | 浪潮电子信息产业股份有限公司 | Chip verification method and device and chip verification platform |
| CN117034816A (en) * | 2023-08-07 | 2023-11-10 | 爱芯元智半导体(宁波)有限公司 | Register mapping method and device based on system level verification scene |
| CN117290209A (en) * | 2023-08-29 | 2023-12-26 | 格兰菲智能科技(北京)有限公司 | Test case generation method, chip verification system and medium |
-
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- 2024-10-30 CN CN202411524115.0A patent/CN119047384A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11062077B1 (en) * | 2019-06-24 | 2021-07-13 | Amazon Technologies, Inc. | Bit-reduced verification for memory arrays |
| CN112270149A (en) * | 2020-10-16 | 2021-01-26 | 山东云海国创云计算装备产业创新中心有限公司 | Verification platform automation integration method and system, electronic equipment and storage medium |
| CN113722163A (en) * | 2021-08-20 | 2021-11-30 | 浪潮电子信息产业股份有限公司 | Chip verification method and device and chip verification platform |
| CN117034816A (en) * | 2023-08-07 | 2023-11-10 | 爱芯元智半导体(宁波)有限公司 | Register mapping method and device based on system level verification scene |
| CN117290209A (en) * | 2023-08-29 | 2023-12-26 | 格兰菲智能科技(北京)有限公司 | Test case generation method, chip verification system and medium |
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