CN119031829A

CN119031829A - Semiconductor structure and method for manufacturing the same

Info

Publication number: CN119031829A
Application number: CN202310558851.7A
Authority: CN
Inventors: 黄猛
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2023-05-16
Filing date: 2023-05-16
Publication date: 2024-11-26

Abstract

The present disclosure provides a semiconductor structure and a method of fabricating the same. Wherein the semiconductor structure comprises: a substrate; the first capacitor electrode is positioned on the substrate and extends along a first direction; the second capacitor electrode at least comprises a first electrode, the first electrode penetrates through the inside of the first capacitor electrode along a second direction, a plurality of first electrodes arranged along the first direction are arranged in the same first capacitor electrode, and the second direction is intersected with the first direction; the capacitive dielectric layer at least comprises a first capacitive dielectric layer, and the first capacitive dielectric layer is positioned between the first electrode and the first capacitive electrode. The embodiment of the disclosure can realize the improvement of the capacitance value of the capacitor by improving the density of the first electrode.

Description

Semiconductor structure and preparation method thereof

Technical Field

The disclosure relates to the technical field of semiconductors, and in particular relates to a semiconductor structure and a preparation method thereof.

Background

The dynamic random access memory (Dynamic Random Access Memory, DRAM) is a semiconductor memory. Memory cells within DRAMs typically utilize capacitors to store charge to effect binary data storage.

With the development of semiconductor technology, the requirements of the performance of devices are higher and higher, and the capacitance value of the capacitor in the existing DRAM needs to be improved.

Disclosure of Invention

Based on the above, the embodiment of the disclosure provides a semiconductor structure and a preparation method thereof.

In one aspect, the present disclosure provides a semiconductor structure comprising:

A substrate;

a first capacitor electrode located on the substrate and extending along a first direction;

The second capacitor electrode at least comprises a first electrode, the first electrode penetrates through the first capacitor electrode along a second direction, a plurality of first electrodes are arranged in the same first capacitor electrode along a first direction, and the second direction is intersected with the first direction;

The capacitive medium layer at least comprises a first capacitive medium layer, and the first capacitive medium layer is positioned between the first electrode and the first capacitive electrode.

In one embodiment, the semiconductor structure includes at least two layers of the first capacitor electrodes stacked along the second direction, an isolation layer is disposed between the adjacent layers of the first capacitor electrodes, and the first electrodes extend along the second direction and penetrate through the at least two layers of the first capacitor electrodes.

In one of the embodiments of the present invention,

The semiconductor structure comprises a plurality of first capacitor electrode layer groups which are arranged along a third direction at intervals, each first capacitor electrode layer group comprises at least two layers of first capacitor electrodes which are arranged along a second direction in a stacked mode, the third direction is intersected with the first direction, and the second direction is perpendicular to the first direction and a plane determined by the third direction.

In one embodiment, the second capacitor electrode further includes a second electrode, the capacitor dielectric layer includes a second capacitor dielectric layer, the second capacitor dielectric layer extends along the first direction and is connected to each layer of the first capacitor electrode layer in the same first capacitor electrode layer group, and the second electrode is located on a side wall of the second capacitor dielectric layer away from the first capacitor electrode layer group.

In one embodiment, the second electrode and the second capacitive dielectric layer fill a region between adjacent groups of the first capacitive electrode layers along a third direction.

In one embodiment, an electrode seed layer is further disposed between the first capacitive electrode and the first capacitive dielectric layer.

In one embodiment, the substrate includes a transistor including a semiconductor pillar extending along a first direction, the first capacitive electrode being connected to the semiconductor pillar in the first direction.

The disclosure also provides a method for manufacturing a semiconductor structure, comprising the steps of:

providing a substrate;

forming a plurality of support columns on the substrate, wherein the support columns are arranged along a first direction, and extend along a second direction, and the second direction intersects with the first direction;

forming a first capacitor electrode around the side wall of the support column, wherein the same first capacitor electrode extends along the first direction and surrounds a plurality of support columns arranged along the first direction;

removing the support column to make the first capacitance electrode hollow;

the method comprises the steps of forming a capacitance medium layer and a second capacitance electrode, wherein the capacitance medium layer at least comprises a first capacitance medium layer, the second capacitance electrode at least comprises a first electrode, the first capacitance medium layer and the first electrode are formed inside the first capacitance electrode, and the first capacitance medium layer is located between the first capacitance electrode and the first electrode.

In one of the embodiments of the present invention,

The forming a plurality of support columns arranged along a first direction on the substrate includes:

forming at least two isolating layers arranged at intervals and a sacrificial layer positioned between the isolating layers on the substrate;

etching the isolation layer and the sacrificial layer to form a plurality of support holes arranged along a first direction;

Filling supporting materials into the supporting holes to form the supporting columns;

removing the sacrificial layer;

The first capacitor electrode is formed around the side wall of the support column, and comprises:

forming the first capacitor electrode on the side wall of the support column between the isolation layers;

The forming the capacitance dielectric layer and the second capacitance electrode comprises the following steps:

and forming the first capacitance medium layer and the first electrode in the supporting hole.

In one of the embodiments of the present invention,

The etching the isolation layer and the sacrificial layer to form a plurality of support holes arranged along a first direction comprises the following steps:

And etching the isolation layer and the sacrificial layer to form a plurality of support hole groups arranged along a third direction, wherein each support hole group comprises a plurality of support holes arranged along a first direction, and the third direction is intersected with the first direction.

In one embodiment, after the supporting hole is filled with the supporting material to form the supporting column, the method further includes:

and etching the isolating layer and the sacrificial layer between the adjacent supporting hole groups along the third direction to form a spacing groove.

In one embodiment, the capacitive dielectric layer further comprises a second capacitive dielectric layer, the second capacitive electrode further comprises a second electrode,

And forming the first capacitance medium layer and the first electrode in the supporting hole, and forming the second capacitance medium layer and the second electrode in the spacing groove.

In one embodiment, the second electrode and the second capacitance medium layer fill the support hole and the spacer groove.

In one of the embodiments of the present invention,

Before the support column is formed by filling the support material in the support hole, the method comprises the following steps:

Etching to remove part of the sacrificial layer along the side wall of the supporting hole to form a surrounding groove surrounding the supporting hole;

forming an electrode seed layer in the surrounding groove;

The first capacitor electrode is formed on the side wall of the support column between the isolation layers, and comprises:

and forming the first capacitance electrode on the surface of the electrode seed layer.

In one embodiment, the substrate includes a transistor including a semiconductor pillar extending along a first direction,

Forming a first capacitor electrode on the sidewall of the support column, including:

and forming a first capacitor electrode connected with the semiconductor column in a first direction on the side wall of the support column.

The second capacitor electrode at least comprises a first electrode positioned in the first capacitor electrode. And the same first capacitance electrode is internally provided with a plurality of first electrodes arranged along a first direction, so that the same first capacitance electrode can form a capacitor with the plurality of first electrodes. Therefore, the capacitance value of the capacitor can be increased by increasing the first electrode density.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments or the conventional techniques of the present disclosure, the drawings required for the descriptions of the embodiments or the conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to the drawings without inventive effort to those of ordinary skill in the art.

FIG. 1 is a flow chart of a method for fabricating a semiconductor structure according to one embodiment;

Fig. 2 to 11 are schematic perspective views of structures obtained in steps of a semiconductor structure manufacturing process according to an embodiment;

FIG. 12 is a schematic diagram of a semiconductor structure according to an embodiment;

FIG. 13 is a schematic top view of a semiconductor structure according to one embodiment;

fig. 14 is a schematic top view of a semiconductor structure provided in another embodiment.

Reference numerals illustrate:

100-substrate, 110-semiconductor column, 111-source region, 112-drain region, 113-channel region, 200-support column, 300-first capacitance electrode, 300 a-first capacitance electrode group, 400-capacitance dielectric layer, 500-second capacitance electrode, 600-isolation layer, 700-sacrificial layer, 800-electrode seed layer, 900-bit line, 10-support hole, 10 a-support hole group, 20-spacer groove, 30-surrounding groove, 40-insulation structure.

Detailed Description

In order that the disclosure may be understood, a more complete description of the disclosure will be rendered by reference to the appended drawings. Preferred embodiments of the present disclosure are shown in the drawings. This disclosure may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.

It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure; for example, the first doping type may be made the second doping type, and similarly, the second doping type may be made the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.

As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure, such that variations of the illustrated shapes due to, for example, manufacturing techniques and/or tolerances are to be expected. Thus, embodiments of the present disclosure should not be limited to the particular shapes of regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure.

In one embodiment, referring to fig. 1, a method for fabricating a semiconductor structure is provided. The method may be applied, but is not limited to, to forming a capacitor in a DRAM, comprising the steps of:

Step S10, providing a substrate 100, please refer to fig. 2;

step S20, forming a plurality of support columns 200 on the substrate 100 along a first direction, wherein the support columns 200 extend along a second direction, and the second direction intersects the first direction, please refer to fig. 8;

Step S30, a first capacitor electrode 300 is formed around the sidewall of the support column 200, and the same first capacitor electrode 300 extends along the first direction and surrounds the plurality of support columns 200 arranged along the first direction, please refer to fig. 9;

Step S40, remove the support pillar 200 to make the first capacitor electrode 300 hollow, please refer to fig. 10;

in step S50, a capacitor dielectric layer 400 and a second capacitor electrode 500 are formed, the capacitor dielectric layer 400 at least includes a first capacitor dielectric layer 410, the second capacitor electrode 500 at least includes a first electrode 510, the first capacitor dielectric layer 410 and the first electrode 510 are formed inside the first capacitor electrode 300, and the first capacitor dielectric layer 410 is located between the first capacitor electrode 300 and the first electrode 510, please refer to fig. 11.

In step S10, the base 100 may include a substrate. For example, the substrate may include a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III/V semiconductor substrate or II/VI semiconductor substrate. Or also for example, the substrate may comprise a Si/SiGe, si/SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator substrate, or the like. The type of substrate should not limit the scope of the present disclosure.

Further, in some examples, the substrate 100 may also include other film structures. For example, the base 100 may also include a dielectric layer or the like formed on the substrate.

In step S20, referring to fig. 8, a plurality of support columns 200 formed on the substrate 100 may be arranged at intervals along the first direction. The first direction may be parallel to the substrate 100, for example. Meanwhile, the support columns 200 extend in a second direction, which may be perpendicular or inclined to the substrate 100, for example.

The support column 200 may be cylindrical, or may be in other forms of columns (e.g., square columns). The spacing between adjacent support columns 200 may or may not be equal, and is not limited in this regard.

The material of the support column 200 may include, but is not limited to, an insulating material. The insulating material may be a material having a low dielectric constant.

In step S30, referring to fig. 9, the first capacitor electrode 300 may be formed by chemical vapor deposition or electroplating. The first capacitive electrode 300 may be formed around the sidewall of the support pillar 200. Also, the same capacitive electrode 300 may extend in the first direction so as to simultaneously surround the sidewalls of the plurality of support columns 200 arranged in the first direction. At this time, after the first capacitor electrode 300 is formed, the plurality of support columns 200 arranged along the first direction are inserted into the first capacitor electrode 300.

The material of the first capacitor electrode 300 may include, but is not limited to, conductive materials such as cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanate (TaTi), tungsten nitride (WN), titanium nitride (TiN), copper (Cu), and aluminum (Al).

In step S40, referring to fig. 10, after removing the support columns 200, the first capacitor electrode 300 is hollow at the position where each support column 200 is originally provided.

In step S50, referring to fig. 11, the second capacitor electrode 500, the capacitor dielectric layer 400 and the first capacitor electrode 300 may form a capacitor.

The material of the capacitive dielectric layer 400 may be a material having a high dielectric constant. For example, the material of the capacitor dielectric layer 400 may be aluminum oxide (Al ₂O₃), hafnium oxide (HfO ₂), hafnium oxynitride (HfON), zirconium oxide (ZrO ₂), tantalum oxide (Ta ₂O₅), titanium oxide (TiO ₂), or strontium titanium oxide (SrTiO ₃). Of course, the material of the capacitive dielectric layer 400 may be a material having a low dielectric constant, which is not limited herein.

The material of the second capacitor electrode 500 may include, but is not limited to, conductive materials such as cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanate (TaTi), tungsten nitride (WN), titanium nitride (TiN), copper (Cu), and aluminum (Al).

The capacitive dielectric layer 400 includes at least a first capacitive dielectric layer 410, and the second capacitive electrode 500 includes at least a first electrode 510.

The first capacitive dielectric layer 410 may be formed at each hollow inside the first capacitive electrode 300, and the first electrode 510 may be formed at a side surface of the first capacitive dielectric layer 410. As an example, the hollow portions inside the first capacitive electrode 300 may be filled up by the first electrode 510 and the first capacitive medium layer 410.

In this embodiment, a plurality of support columns 200 arranged along the first direction are formed first, and then the first capacitor electrode 300 is formed around the sidewall of each support column 200. The same first capacitor electrode 300 extends along the first direction to surround the plurality of support columns 200 arranged along the first direction. Accordingly, after the support columns 200 are subsequently removed, a plurality of first electrodes 510 may be formed at the locations where the support columns 200 were originally provided within the first capacitor electrode 300. At this time, the same first capacitive electrode 300 may be allowed to form a capacitor with the plurality of first electrodes 510 inside. Therefore, the present embodiment can achieve an increase in the capacitance value of the capacitor by increasing the density of the support columns 200 and thus the density of the first electrodes 510.

In one embodiment, step S20 includes:

step S21, forming at least two spacers 600 disposed between the spacers 600 and a sacrificial layer 700 between the spacers 600 on the substrate 100, please refer to fig. 2;

Step S22, etching the isolation layer 600 and the sacrificial layer 700 to form a plurality of support holes 10 aligned along the first direction, refer to fig. 3;

Step S24, filling the supporting holes 10 with supporting materials to form supporting columns 200, refer to FIG. 6;

in step S26, the sacrificial layer 700 is removed, see fig. 8.

Step S30 includes:

in step S31, referring to fig. 9, a first capacitor electrode 300 is formed on the sidewall of the support pillar 200 between the isolation layers 600.

In step S21, referring to fig. 2, the isolation layer 600 and/or the sacrificial layer 700 may be formed by a deposition process. The deposition process may include, but is not limited to, one or more of a chemical vapor deposition process (Chemical Vapor Deposition, CVD), an atomic layer deposition process (Atomic Layer Deposition, ALD), a high-density plasma deposition (HIGH DENSITY PLASMA, HDP) process, and Spin-on Dielectric (SOD) processes.

As an example, the underlying isolation layer 600 may be formed on the upper surface of the substrate 700, the underlying sacrificial layer 700 may be formed on the upper surface of the underlying isolation layer 600, and the isolation layer 600 and the sacrificial layer 700 may be repeatedly and alternately formed.

The material of the isolation layer 600 and/or the sacrificial layer 700 may include, but is not limited to, silicon oxide (SiO ₂), silicon nitride (Si ₃N₄), aluminum oxide (Al ₂O₃), or silicon oxynitride (SiON). Meanwhile, the material of the isolation layer 600 is different from that of the sacrificial layer 700. As an example, the material of the isolation layer 600 may be provided as silicon oxide, and the material of the sacrificial layer 700 as silicon nitride.

In step S22, referring to fig. 3, the isolation layers 600 and the sacrificial layers 700 may be etched by dry etching or the like, so as to form support holes 10 penetrating the isolation layers 600 and the sacrificial layers 700.

In step S24, referring to fig. 6, after the plurality of support holes 10 aligned along the first direction are filled with the support material, a plurality of support columns 200 aligned along the first direction may be formed. Each support column 200 may penetrate the respective isolation layer 600 and the respective sacrificial layer 700 so as to extend in the second direction.

As an example, a support material may be first formed in each support hole 10 and on the upper surface of the top spacer layer 600. Thereafter, the supporting material on the upper surface of the top spacer layer 600 may be removed by Chemical Mechanical Polishing (CMP) or the like.

The support material is different from the material of the isolation layer 600 and also from the material of the sacrificial layer 700, thereby facilitating the subsequent removal of the support post 200 at step S40. As an example, the support material may be a material having a low dielectric constant.

In step S26, referring to fig. 8, the sacrificial layer 700 may be removed by wet etching or the like. At this time, since the material of the sacrificial layer 700 is different from the material of the isolation layer 600 and the material of the support columns 200. Thus, after the sacrificial layer 700 is removed, the isolation layer 600 and the support columns 200 may remain.

Since the sacrificial layer 700 of the sidewall of the support column 200 between each adjacent isolation layer 600 is removed, the sidewall of the support column 200 between each adjacent isolation layer 600 is exposed.

In step S31, referring to fig. 9, a first capacitor electrode material surrounding the support columns 200 may be formed on the side walls of the support columns 200 between adjacent isolation layers 600 by deposition or electroplating. And, after depositing or plating for a predetermined time, the first capacitive electrode material surrounding the plurality of support columns 200 arranged along the first direction may be connected to form the first capacitive electrode 300.

Thereafter, referring to fig. 10, the support column 200 is removed in step S40. Then, in step S50, it may include:

In step S51, referring to fig. 11, a first capacitor dielectric layer 410 and a first electrode 510 are formed in the supporting hole 10.

At this time, the first capacitive dielectric layer 410 and the first electrode 510 extending in the second direction may be formed inside the first capacitive electrode 300.

In the present embodiment, after the sacrificial layer 700 is removed, the region between adjacent isolation layers 600 may be used to form the first capacitive electrode 300. The isolation layer 600 may effectively isolate the first capacitive electrode 300 from other film structures. Meanwhile, when the number of layers of the isolation layer 600 is greater than two, at least two first capacitor electrodes 300 are formed between each adjacent isolation layer 600. At this time, the first capacitive medium layer 410 and the first electrode 510 formed in the support hole 10 to extend in the second direction may form a multi-layered capacitor with each layer of the first capacitive electrode 300, so that an effective increase in memory cell density may be achieved per unit wafer area. Meanwhile, the isolation layer 600 may effectively isolate the respective layers of the capacitor.

In one embodiment, step S22 includes:

In step S221, referring to fig. 3, the isolation layer 600 and the sacrificial layer 700 are etched to form a plurality of support hole sets 10a arranged along a third direction, wherein each support hole set 10a includes a plurality of support holes 10 arranged along a first direction, and the third direction intersects the first direction.

At this time, after etching the isolation layer 600 and the sacrificial layer 700, a plurality of support holes 10 arranged in an array may be formed.

As an example, a plane defined by the third direction and the first direction may be parallel to the substrate 100. Meanwhile, the second direction may be perpendicular to the substrate 100.

Also, as an example, the specific etching process of the isolation layer 600 and the sacrificial layer 700 may be:

After the top-layer isolation layer 600 is formed in step S21, a mask material layer is formed on the top-layer isolation layer 600. For example, a sacrificial layer 700 may be formed as a masking material layer. Of course, other mask material layers different from the material of the sacrificial layer 700 may be formed on the top spacer layer 600.

The mask material layer, such as the sacrificial layer 700 formed over the top spacer layer 600, may then be patterned by a self-aligned double patterning technique (SADP), a self-aligned quad patterning technique (SAQP), or the like, to form a patterned mask layer. The patterned mask layer has a first opening therein exposing the spacer layer 600 of the top layer and defining the shape and location of the support hole 10. Thereafter, the isolation layers 600 and the sacrificial layers 700 thereunder may be etched based on the patterned mask layer, thereby forming the support holes 10. After the support holes 10 are formed, the patterned mask layer may be removed.

The density of the formed support holes 10 can be effectively increased by forming the patterned mask layer by self-aligned double patterning (SADP), self-aligned quad patterning (SAQP), and the like. Of course, the mask material layer may also be patterned by conventional photolithography techniques, thereby forming a patterned mask layer. This is not limiting here.

After forming the plurality of support hole groups 10a arranged in the third direction, in step S24, the support holes 10 arranged in an array may be filled with a support material, thereby forming the support columns 200 arranged in an array. Thereafter, the sacrificial layer 700 between the respective isolation layers 600 may be removed in step S26, thereby exposing the sidewalls of the support columns 200 between the respective isolation layers 600.

In this embodiment, the formed capacitor can be effectively arranged in both the third direction and the second direction.

In one embodiment, after step S24, further comprising:

In step S25, referring to fig. 3 and 7, the spacer grooves 20 are formed by etching the spacer layer 600 and the sacrificial layer 700 between the support hole sets 10a adjacent to each other in the third direction.

A patterned photoresist may be first formed on the upper surface of the top spacer layer 600 and the upper surface of the support columns 200. The patterned photoresist may have a second opening. The first openings may expose the top layer spacer layer 600 between the support hole groups 10a adjacent in the third direction. Thereafter, the isolation layers 600 and the sacrificial layers 700 thereunder may be etched based on the patterned photoresist, thereby forming the spacer grooves 20 extending in the first direction. After the spacer 20 is formed, the patterned photoresist may be removed.

In the present embodiment, after the spacer grooves 20 are formed, different support hole groups 10a may be spaced apart, so that it may be convenient to form a plurality of first capacitor electrodes 300 extending in the first direction and spaced apart in the third direction corresponding to the respective support hole groups 10a or a plurality of stacked first capacitor electrodes 300 extending in the first direction and spaced apart in the third direction corresponding to the respective support hole groups 10a in a subsequent step.

In one embodiment, step S25 is performed before step S26, i.e., after forming the spacer grooves 20, the sacrificial layer 700 is removed.

At this time, the sacrificial layer 700 may be more easily removed. For example, a wet etch may be used to remove the sacrificial layer 700. At this time, the etching liquid may rapidly and effectively etch the sacrificial layer 700 through the spacer grooves 20, thereby facilitating removal of the sacrificial layer 700.

In one embodiment, capacitive dielectric layer 400 further includes a second capacitive dielectric layer 420, and second capacitive electrode 500 further includes a second electrode 520.

Referring to fig. 11, in step S51, the first capacitor dielectric layer 410 and the first electrode 510 are formed in the supporting hole 10, and the second capacitor dielectric layer 420 and the second electrode 520 are also formed in the spacer 20, when step S24 is further followed by step S25.

At this time, a capacitance dielectric material layer may be first formed on the sidewalls of the support hole 10, the bottom of the support hole 10, the sidewalls of the spacer 20, the bottom of the spacer 20, and the upper surface of the isolation layer 600 on the top surface. Then, the capacitor dielectric material layer on the upper surfaces of the isolation layer 600 at the bottom of the support hole 10, the bottom of the spacer 20, and the top surface may be removed by anisotropic etching (e.g., dry etching), and the capacitor dielectric material layer remaining on the sidewalls of the support hole 10 and the sidewalls of the spacer 20 may be formed into the capacitor dielectric layer 400. At this time, the capacitive dielectric material layer on the sidewall of the supporting hole 10 forms a first capacitive dielectric layer 410, and the capacitive dielectric material layer on the sidewall of the spacer 20 forms a second capacitive dielectric layer 420.

Thereafter, a second capacitive electrode material layer may be formed on the surface of the capacitive dielectric layer 400 and the upper surface of the isolation layer 600 on the top surface. Then, the second capacitance electrode material layer on the upper surface of the isolation layer 600 on the top surface may be removed by Chemical Mechanical Polishing (CMP) or the like, and the second capacitance electrode material layer remaining in the support hole 10 and the spacer groove 20 forms the second capacitance 500. At this time, the second capacitance electrode material layer located in the support hole 10 forms the first electrode 510, and the second capacitance electrode material layer located in the space groove 20 forms the second electrode 520.

At this time, the capacitor dielectric layer 400 and the second capacitor electrode 500 are not only located inside the first capacitor electrode 300, but also located on the sidewall of the first capacitor electrode 300, so that the capacitance value of the capacitor can be effectively increased.

Meanwhile, as an example, after the second capacitor electrode 500 is formed, the second electrode 520 may fill up the support hole 10 and the spacer groove 20 together with the second capacitor dielectric layer 420, so that the first capacitor electrode 300 adjacent in the third direction may share the second electrode 520, thereby saving a chip area and increasing a capacitance capacity.

In one embodiment, step S24 is preceded by:

Step S231, referring to fig. 4, etching away a portion of the sacrificial layer 700 along the sidewall of the supporting hole 10 to form a surrounding groove 30 surrounding the supporting hole 10;

In step S232, referring to fig. 5, an electrode seed layer 800 is formed in the surrounding trench 30.

In step S231, the sacrificial layer 700 may be etched along the sidewall of the support hole 10 by an etching solution, for example, by wet etching. At this time, the sacrificial layer 700 located at the sidewall of the support hole 10 is partially etched away, thereby forming the surrounding groove 30 surrounding the support hole 10.

In step S232, a seed material layer may be first formed around the sidewalls of the trench 30, the sidewalls of the support hole 10, and the upper surface of the top spacer layer 600. Then, the seed material layer located at the sidewalls of the support holes 10 and the upper surface of the top spacer layer 600 may be etched away, and the seed material layer remaining at the sidewalls surrounding the trenches 30 forms the electrode seed layer 800. As an example, the electrode seed layer 800 may fill the surrounding trench 30. At this time, the electrode seed layer 800 sidewall is flush or nearly flush with the isolation layer 600 sidewall.

Of course, in other examples, the electrode seed layer 800 may not fill the surrounding trench 30. At this time, the sidewall of the electrode seed layer 800 may be recessed with respect to the sidewall of the isolation layer 600 within the support hole. At this time, the sidewalls of the support columns 200 formed in the subsequent step S24 may be outwardly protruded at positions between the adjacent isolation layers 600. Accordingly, the capacitor dielectric layer 400 and the second capacitor electrode 500 formed in the subsequent step S50 extending in the second direction are also protruded outwardly at the position between the adjacent isolation layers 600, so that the capacitance value of the capacitor formed between the second capacitor electrode 500 and each of the first capacitor electrodes 300 can be increased.

Or in other embodiments, the electrode seed layer 800 may not be formed in the surrounding trench 30. At this time, the capacitor dielectric layer 400 and the second capacitor electrode 500 formed in the subsequent step S50 extending in the second direction are also protruded outwardly at the position between the adjacent isolation layers 600, so that the capacitance value of the capacitor formed between the second capacitor electrode 500 and each of the first capacitor electrodes 300 can be increased.

At this time, step S31 includes:

In step S311, referring to fig. 9, a first capacitor electrode 300 is formed on the surface of the electrode seed layer 800.

At this time, the electrode seed layer 800 may serve as a seed for the first capacitive electrode 300, thereby facilitating formation of the first capacitive electrode 300 having good conductive properties. In forming the first capacitor electrode 300, a first capacitor electrode material layer may be first electroplated on the surface of the electrode seed layer 800, the sidewall of the isolation layer 600 in the spacer 20, the upper surface of the top isolation layer 600 and the upper surface of the support pillar 200. Then, the first capacitance electrode material layer in the spacer 20, the upper surface of the top isolation layer 600, the upper surface of the support column 200, and the top surface are etched away. And the first capacitive electrode material layer formed between the isolation layers 600 forms the first capacitive electrode 300.

In one embodiment, the substrate 100 includes a transistor. The transistor includes a semiconductor pillar 110 extending in a first direction.

Referring to fig. 13, the semiconductor pillar 110 extends along the first direction so as to have the same extension direction as the first capacitor electrode 300. Both ends of the semiconductor pillar 110 may be doped to form a source region 111 and a drain region 112. Semiconductor column 110 between source region 111 and drain region 112 forms channel region 113. One of source region 111 and drain region 112 may be connected to bit line 900, and the other may be connected to first capacitive electrode 300, thereby being connected to a capacitor.

At this time, step S30 includes:

the first capacitor electrode 300 connected to the semiconductor pillar 110 in the first direction is formed on the sidewall of the support pillar 200.

When the multi-layered first capacitor electrode 300 is formed between the plurality of isolation layers 600, the multi-layered semiconductor pillars 110 may also be formed on the substrate 100. Each layer of the first capacitor electrode 300 may be correspondingly connected to one layer of the semiconductor pillars 110.

Also, when the plurality of first capacitor electrodes 300 arranged at intervals in the third direction are included in the same layer of first capacitor electrodes 300, each layer of semiconductor pillars 110 may include a plurality of semiconductor pillars 110 arranged at intervals in the third direction. Each of the first capacitor electrodes 300 may be connected to one of the semiconductor pillars 110.

It will be appreciated that at this time, the semiconductor pillar 110 (specifically, the source region or the drain region of the semiconductor pillar 110) is insulated from the second capacitor electrode 500 while being connected to the first capacitor electrode 300.

Based on this, referring to fig. 13, when the second capacitor electrode 500 includes both the first electrode 510 and the second electrode 520 (i.e., the second capacitor electrode 500 is located inside the first capacitor electrode 300 and on the sidewall of the first capacitor electrode 300), for example, the width of the first capacitor electrode 300 may be greater than or equal to the width of the corresponding semiconductor pillar 110, so that the semiconductor pillar 110 is insulated from the second electrode 520.

Of course, the width of the first capacitor electrode 300 may be set smaller than the width of the corresponding semiconductor pillar 110. At this time, referring to fig. 14, the semiconductor pillar 110 may be isolated from the second electrode 520 by other means. For example, after the second electrode 520 is formed, a portion thereof may be removed near one end of the semiconductor pillar 110; the etched-out region is then filled with insulating structure 40, thereby isolating semiconductor pillars 110 from second electrode 520.

In other embodiments, the transistor may be formed after the second capacitor electrode 500 is formed, thereby completing the capacitor fabrication, which is not limited herein.

It should be understood that, although the steps in the flowchart of fig. 1 are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in fig. 1 may include a plurality of steps or stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily sequential, but may be performed in rotation or alternatively with at least a portion of the steps or stages in other steps or other steps.

In one embodiment, referring to fig. 11 or 12, and also referring to fig. 13 or 14, there is further provided a semiconductor structure comprising: the substrate 100, the first capacitor electrode 300, the capacitor dielectric layer 400 and the second capacitor electrode 500.

The base 100 may include a substrate. For example, the substrate may include a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III/V semiconductor substrate or II/VI semiconductor substrate. Or also for example, the substrate may comprise a Si/SiGe, si/SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator substrate, or the like. The type of substrate should not limit the scope of the present disclosure. Further, in some examples, the substrate 100 may also include other film structures. For example, the base 100 may also include a dielectric layer or the like formed on the substrate.

The first capacitor electrode 300 is disposed on the substrate 100 and extends along a first direction. The material of the first capacitor electrode 300 may include, but is not limited to, conductive materials such as cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanate (TaTi), tungsten nitride (WN), titanium nitride (TiN), copper (Cu), and aluminum (Al).

The second capacitive electrode 500 includes at least a first electrode 510. The first electrode 510 penetrates through the first capacitor electrode 300 along the second direction. The second direction intersects the first direction. The first direction may be parallel to the substrate 100, for example. The second direction may be perpendicular or oblique to the substrate 100, for example.

The same first capacitor electrode 300 has a plurality of first electrodes 510 arranged along a first direction therein.

The capacitive dielectric layer 400 is located between the second capacitive electrode 500 and the first capacitive electrode 300. At this time, the capacitive dielectric layer 400 may include at least the first capacitive dielectric layer 410. The first capacitance dielectric layer 410 is located in the first capacitance electrode 300 and is located between the first electrode 510 and the first capacitance electrode 300.

In this embodiment, the same first capacitive electrode 300 may form a capacitor with the plurality of first electrodes 510 inside. Accordingly, an increase in the capacitance value of the capacitor can be achieved by increasing the density of the first electrode 510.

In one embodiment, referring to fig. 12, the semiconductor structure includes at least two first capacitor electrodes 300 stacked along the second direction. An isolation layer 600 is disposed between adjacent first capacitor electrodes 300.

The material of the isolation layer 600 may include, but is not limited to, silicon oxide (SiO ₂), silicon nitride (Si ₃N₄), aluminum oxide (Al ₂O₃), or silicon oxynitride (SiON). As an example, the material of the isolation layer 600 may be provided as silicon oxide.

Meanwhile, as an example, the isolation layer 600 may be located under the bottom layer first capacitive electrode 300 and/or over the top layer first capacitive electrode 300, in addition to being located between adjacent layer first capacitive electrodes 300.

The first electrode 510 of the second capacitor electrode 500 extends along the second direction and penetrates at least two layers of the first capacitor electrodes 300. The first capacitive dielectric layer 410 between the first electrode 510 and the first capacitive electrode 300 may also extend along the second direction and penetrate at least two layers of the first capacitive electrode 300.

In the present embodiment, the first electrode 510 extending in the second direction may form a multi-layer capacitor with each layer of the first capacitive electrode 300, so that an effective increase in memory cell density per unit wafer area may be achieved. Meanwhile, the isolation layer 600 may effectively isolate the respective layers of the capacitor.

In one embodiment, referring to fig. 11, the semiconductor structure includes a plurality of first capacitor electrode groups 300a arranged along a third direction and spaced apart, each first capacitor electrode group 300a includes at least two first capacitor electrodes 300 stacked along a second direction, the third direction intersects the first direction, and the second direction intersects a plane defined by the first direction and the third direction. As an example, the planes defined by the first direction and the third direction may be parallel to the substrate 100.

In one embodiment, referring to fig. 11, the second capacitor electrode 500 further includes a second electrode 520. The second electrode 520 is located between the first capacitive electrode layer groups 300a adjacent in the third direction.

At this time, the capacitive dielectric layer 400 may further include a second capacitive dielectric layer 420, where the second capacitive dielectric layer 420 is located between the second electrode 520 and the first capacitive electrode layer 300.

The second capacitive dielectric layer 420 may extend along the first direction along with the first capacitive electrode layer 300 and connect the first capacitive electrode layers 300 of each layer within the same first capacitive electrode layer group 300 a. The second electrode 520 may be located on a sidewall of the second capacitive dielectric layer 420 remote from the first capacitive electrode layer group 300 a.

In one embodiment, referring to fig. 11, the second electrode 520 and the second capacitor dielectric layer 420 fill the area between the first capacitor electrode layer groups 300a adjacent in the third direction.

At this time, the first capacitive electrodes 300 adjacent in the third direction may be made to share the second electrode 520, so that a chip area may be saved and a capacitance capacity may be increased.

In one embodiment, referring to fig. 11, an electrode seed layer 800 is further disposed between the first capacitor electrode 300 and the first capacitor dielectric layer 410. The electrode seed layer 800 is applied as a seed for the first capacitive electrode 300 during the manufacturing process.

In one embodiment, referring to fig. 13 or 14, the substrate includes a transistor. The transistor includes a semiconductor pillar 110 extending in a first direction. The first capacitor electrode 300 is connected to the semiconductor pillar 110 in a first direction.

The first capacitor electrode 300 and the semiconductor pillar 110 may be directly connected in the first direction, or may be connected through metal silicide or the like, which is not limited herein.

The semiconductor pillar 110 extends in the first direction so as to have the same extension direction as the first capacitive electrode 300. Both ends of the semiconductor pillar 110 may be doped to form a source region 111 and a drain region 112. Semiconductor column 110 between source region 111 and drain region 112 forms channel region 113. One of source region 111 and drain region 112 may be connected to bit line 900, and the other may be connected to first capacitive electrode 300, thereby being connected to a capacitor.

The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples merely represent a few embodiments of the present disclosure, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that variations and modifications can be made by those skilled in the art without departing from the spirit of the disclosure, which are within the scope of the disclosure. Accordingly, the scope of protection of the present disclosure should be determined by the following claims.

Claims

1. A semiconductor structure, comprising:

A substrate;

2. The semiconductor structure of claim 1, wherein the semiconductor structure comprises at least two layers of the first capacitor electrodes stacked along the second direction, an isolation layer is disposed between adjacent layers of the first capacitor electrodes, and the first electrodes extend along the second direction and penetrate through the at least two layers of the first capacitor electrodes.

3. The semiconductor structure of claim 2, wherein,

4. The semiconductor structure of claim 3, wherein the second capacitor electrode further comprises a second electrode, the capacitor dielectric layer comprises a second capacitor dielectric layer extending along the first direction and connecting each of the first capacitor electrode layers in the same first capacitor electrode layer set, the second electrode being located on a sidewall of the second capacitor dielectric layer remote from the first capacitor electrode layer set.

5. The semiconductor structure of claim 4, wherein the second electrode and the second capacitive dielectric layer fill a region between adjacent groups of the first capacitive electrode layers along a third direction.

6. The semiconductor structure of claim 1, wherein an electrode seed layer is further disposed between the first capacitive electrode and the first capacitive dielectric layer.

7. The semiconductor structure of claim 1, wherein the substrate comprises a transistor comprising a semiconductor pillar extending along a first direction, the first capacitive electrode connecting the semiconductor pillar in the first direction.

8. A method of fabricating a semiconductor structure, comprising the steps of:

providing a substrate;

removing the support column to make the first capacitance electrode hollow;

9. The method of manufacturing a semiconductor structure as claimed in claim 8, wherein,

removing the sacrificial layer;

10. The method of manufacturing a semiconductor structure as claimed in claim 9, wherein,

11. The method of fabricating a semiconductor structure according to claim 10, wherein after filling the support holes with a support material to form the support columns, further comprising:

12. The method of claim 11, wherein the capacitive dielectric layer further comprises a second capacitive dielectric layer, the second capacitive electrode further comprises a second electrode,

And forming the first capacitance medium layer and the first electrode in the supporting hole, and forming the second capacitance medium layer and the second electrode in the interval groove, wherein the second capacitance medium layer is positioned between the first capacitance electrode and the second electrode.

13. The method of claim 12, wherein the second electrode and the second capacitor dielectric layer fill the support hole and the spacer trench.

14. The method for manufacturing a semiconductor structure according to any one of claims 9 to 13, wherein,

forming an electrode seed layer in the surrounding groove;

15. The method of fabricating a semiconductor structure of claim 9, wherein the substrate comprises a transistor comprising a semiconductor pillar extending along a first direction,