CN119029037A - Semiconductor structure and method for forming the same - Google Patents
Semiconductor structure and method for forming the same Download PDFInfo
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- CN119029037A CN119029037A CN202411111987.4A CN202411111987A CN119029037A CN 119029037 A CN119029037 A CN 119029037A CN 202411111987 A CN202411111987 A CN 202411111987A CN 119029037 A CN119029037 A CN 119029037A
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Abstract
一种半导体结构及其形成方法，方法包括：提供基底，基底包括衬底和位于衬底上的外延层；对基底进行刻蚀，形成位于外延层内的栅极沟槽；对栅极沟槽暴露出的基底进行掺杂处理，形成位于栅极沟槽下的注入掺杂区，注入掺杂区的位置与栅极沟槽的位置相对应；在栅极沟槽内形成栅极结构。栅极沟槽的存在使得相同注入能量下的注入掺杂区嵌入到漂移区内的深度大于从外延层表面注入形成的注入掺杂区的深度，注入掺杂区可以更大程度的耗尽漂移区，提升了半导体器件的击穿电压；此外，注入掺杂区位于栅极沟槽下，且注入掺杂区的位置与栅极沟槽的位置对应，形成注入掺杂区和形成栅极沟槽使用同一张掩膜减少了一次光刻工艺节约了一张掩膜，降低了工艺成本。
A semiconductor structure and a method for forming the same, the method comprising: providing a substrate, the substrate comprising a substrate and an epitaxial layer located on the substrate; etching the substrate to form a gate groove located in the epitaxial layer; performing doping treatment on the substrate exposed by the gate groove to form an implanted doped region located under the gate groove, the position of the implanted doped region corresponding to the position of the gate groove; forming a gate structure in the gate groove. The existence of the gate groove makes the implanted doped region embedded in the drift region at the same implantation energy deeper than the implanted doped region formed by implantation from the surface of the epitaxial layer, the implanted doped region can deplete the drift region to a greater extent, and improve the breakdown voltage of the semiconductor device; in addition, the implanted doped region is located under the gate groove, and the position of the implanted doped region corresponds to the position of the gate groove, and the same mask is used to form the implanted doped region and the gate groove, thereby reducing one photolithography process, saving one mask, and reducing the process cost.
Description
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the same.
Background
Trench gate Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices are widely used in power conversion circuits. The on-resistance and breakdown voltage of the trench gate metal oxide semiconductor field effect transistor are important parameter indexes, higher breakdown voltage is obtained, and the lower on-resistance can improve the competitiveness of the product. In order to improve the on-resistance of medium-high voltage (50-200V) trench gates, super junction-trench gate concepts implemented by implantation are proposed, typically the bottom end of the implanted region that assists the drift region depletion will be as close as possible to the highly doped substrate to make the depletable drift region long.
However, current superjunction-trench gate mosfet devices have shortcomings.
Disclosure of Invention
The problem addressed by the present invention is how to deepen the depth of the implanted region so that the bottom end of the implanted region is as close as possible to the bottom of the substrate, thereby making the implanted region as depleted as possible of the drift region.
In order to solve the above problems, the present invention provides a semiconductor structure, comprising: a substrate comprising a drift region; a gate structure partially within the drift region; and the doping type of the injection doping region is opposite to that of the drift region, the injection doping region is positioned under the gate structure, and the position of the injection doping region corresponds to that of the gate structure.
Optionally, the projection of the implanted doped region on the substrate surface at least partially overlaps with the projection of the gate structure on the substrate surface.
Optionally, the projection of the gate structure on the substrate surface is located within the range of the projection of the implanted doped region on the substrate surface.
Optionally, the method further comprises: and the transition doped region is positioned between the grid structure and the injection doped region and has the same doping type, the transition doped region is electrically contacted with the injection doped region, and the position of the transition doped region corresponds to the injection doped region.
Optionally, the doping concentration of the transitional doping region is greater than the doping concentration of the implanted doping region.
Optionally, the projection of the implanted doped region on the substrate surface at least partially overlaps with the projection of the transitional doped region on the substrate surface.
Optionally, the projection of the implantation doped region on the substrate surface is located in the projection range of the transition doped region on the substrate surface.
Optionally, the transitional doped region also extends between the gate structure and the drift region.
Optionally, the method further comprises: a bulk doped region located on the drift region, the bulk doped region having a doping type opposite to a doping type of the drift region; the gate structure penetrates through the body doping region along a direction perpendicular to the substrate surface and the body doping region is electrically connected with the transition doping region.
Optionally, the transitional doped region also extends between the gate structure and the body doped region.
Optionally, the method further comprises: the first heavily doped layer is positioned on the body doped region, and the doping type of the first heavily doped layer is opposite to that of the body doped region; the gate structure penetrates through the first heavily doped layer along the direction vertical to the surface of the substrate.
Optionally, the method further comprises: a conductive plug passing through the first heavily doped layer, the conductive plug being electrically connected with the body doped region; the second heavily doped layer is positioned at the bottom of the conductive plug, is electrically connected with the conductive plug, has the same doping type as the doping type of the bulk doped region, and has a doping concentration greater than that of the bulk doped region.
Correspondingly, the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate comprises a substrate and an epitaxial layer positioned on the substrate; etching the substrate to form a gate trench in the epitaxial layer; doping the substrate exposed by the gate trench to form an implantation doping region positioned below the gate trench, wherein the position of the implantation doping region corresponds to the position of the gate trench; and forming a gate structure in the gate trench.
Optionally, the step of etching the substrate to form a gate trench in the epitaxial layer includes: forming a hard mask layer with an opening on the substrate; and etching the substrate by taking the hard mask layer as a mask to form a grid groove in the epitaxial layer.
Optionally, in the process of doping the substrate exposed by the gate trench to form the doped region under the gate trench, the substrate exposed by the gate trench is doped with the hard mask layer as a mask.
Optionally, after doping the substrate exposed by the gate trench to form an implanted doped region under the gate trench, before forming a gate structure in the gate trench, the method further includes: and doping the substrate between the gate trench and the implantation doping region to form a transition doping region between the bottom of the gate trench and the implantation doping region, wherein the transition doping region is electrically connected with the implantation doping region, and the position of the transition doping region corresponds to the position of the implantation doping region.
Optionally, in the process of doping the substrate located between the gate trench and the implanted doped region to form a transitional doped region located between the bottom of the gate trench and the implanted doped region, the substrate located between the gate trench and the implanted doped region is doped with the hard mask layer as a mask.
Optionally, doping treatment is performed on the substrate exposed by the gate trench, so that the doping amount of doping treatment for forming an implantation doping region located under the gate trench is smaller than that of doping treatment for forming a transition doping region located between the bottom of the gate trench and the implantation doping region.
Optionally, doping treatment is performed on the substrate between the gate trench and the implanted doped region, and in the process of forming a transitional doped region between the bottom of the gate trench and the implanted doped region, an included angle between an implantation direction of the doping treatment and a normal direction of the substrate ranges from 15 degrees to 45 degrees.
Optionally, the method further comprises: after the step of etching the substrate to form a gate trench in the epitaxial layer, doping the substrate exposed by the gate trench to form an implanted doped region under the gate trench, and performing oxidation repair treatment on the gate trench to form a sacrificial protection layer on the surface of the gate trench; and in the step of doping the substrate exposed by the gate trench to form an implantation doped region under the gate trench, doping the substrate exposed by the gate trench with the sacrificial protection layer on the surface of the trench to form the implantation doped region under the gate trench.
Optionally, the method further comprises: after forming the transitional doped region, the hard mask layer and the sacrificial protection layer are removed before forming a gate structure in the gate trench.
Optionally, the step of forming a gate structure in the gate trench includes: forming a first gate oxide layer on the side wall of the gate trench and the bottom of the gate trench by adopting a low-temperature thermal oxidation process; forming a second gate oxide layer on the first gate oxide layer by adopting a deposition process; forming a gate layer in a gate trench having a first gate oxide layer and a second gate oxide layer on the first gate oxide layer to form the gate structure.
Optionally, before etching the substrate to form the gate trench in the epitaxial layer, the method further includes: and doping the epitaxial layer to form a drift region and an initial body doping region positioned on the drift region.
Optionally, the method further comprises: and after the grid structure is formed, carrying out doping treatment on the initial body doping regions positioned at two sides of the grid structure to form a first heavily doped layer.
Compared with the prior art, the technical scheme of the invention has the following advantages:
In the semiconductor structure of the technical scheme of the invention, the injection doped region is positioned under the gate structure and corresponds to the position of the gate structure, the depth of the injection doped region is larger, the bottom of the injection doped region is closer to the bottom of the substrate, the drift region can be depleted to a greater extent, and the breakdown voltage of the semiconductor device is improved.
In the method for forming the semiconductor structure, the substrate exposed by the gate trench is doped to form the implantation doping region under the gate trench, the implantation doping region with the same implantation energy is embedded into the drift region to a depth greater than that of the implantation doping region formed by implantation from the surface of the epitaxial layer, the bottom of the implantation doping region is closer to the bottom of the substrate, the implantation doping region can deplete the drift region to a greater extent, and the breakdown voltage of the semiconductor device is improved; in addition, the implantation doping region is positioned below the gate trench, the position of the implantation doping region corresponds to the position of the gate trench, and the same mask is used for forming the implantation doping region and the gate trench, so that one mask is saved by one photoetching process, and the process cost is reduced.
Drawings
FIGS. 1-2 are schematic diagrams illustrating a semiconductor structure according to one embodiment;
Fig. 3 to 16 are schematic structural views of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As known from the background art, the super junction-trench gate in the prior art has a plurality of problems. The reason for the problem caused by the super junction-trench gate analysis is combined with the following steps:
Referring to fig. 1 and 2, fig. 2 is a cross-sectional view of fig. 1 at AA1, the semiconductor structure comprising: a substrate 100, the substrate 100 comprising a drift region; a gate structure 103 partially located within the drift region; an implanted doped region 104 having a doping type opposite to that of the drift region, the implanted doped region 104 being located between 2 adjacent gate structures 103.
The base 100 includes a substrate 101 and an epitaxial layer 102 on the substrate 101. And doping the epitaxial layer 102 to form the drift region.
The step of forming a gate structure 103 partially within the drift region comprises: forming a first mask layer having an opening on the substrate 100; etching the substrate 100 by using the first mask layer as a mask to form a gate trench in the epitaxial layer 102; the gate structure 103 is formed within the gate trench.
The opening of the first mask layer is adapted to define the position of the gate structure 103.
The step of forming the implant doped region 104 having a doping type opposite to that of the drift region comprises: forming a second mask layer having an opening on the substrate 100; the second mask layer is used as a mask to dope the substrate 100, so as to form an implanted doped region 104 between 2 adjacent gate structures 103.
The opening of the second mask layer is adapted to define the location of the implanted doped region 104.
The second mask layer is used as a mask for the implantation doping region 104, the first mask layer is used as a mask for the gate trench, 2 masks are needed for forming the implantation doping region 104 and the gate trench, and 2 photolithography processes are performed, so that the process cost is high; in addition, the implantation energy of the implantation doping region 104 needs to be greater than 2500KeV to make the bottom end of the implantation doping region 104 as close to the bottom of the highly doped substrate 100 as possible, but the high energy implantation makes the process integration very difficult.
In order to solve the technical problem, the invention provides a method for forming a semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate comprises a substrate and an epitaxial layer positioned on the substrate; etching the substrate to form a gate trench in the epitaxial layer; doping the substrate exposed by the gate trench to form an implantation doping region positioned below the gate trench, wherein the position of the implantation doping region corresponds to the position of the gate trench; and forming a gate structure in the gate trench.
In the method for forming the semiconductor structure, compared with the method for forming the gate structure and then forming the injection doped regions between 2 gate structures, the method for forming the semiconductor structure comprises the steps of doping the substrate exposed by the gate trench to form the injection doped regions under the gate trench, wherein the depth of the injection doped regions embedded into the drift region under the same injection energy is larger than the depth of the injection doped regions formed by injection from the surface of the epitaxial layer due to the existence of the gate trench, and the injection doped regions can deplete the drift region to a greater extent, so that the breakdown voltage of the semiconductor device is improved; in addition, the implantation doping region is positioned below the gate trench, the position of the implantation doping region corresponds to the position of the gate trench, and the same mask is used for forming the implantation doping region and the gate trench, so that one mask is saved by one photoetching process, and the process cost is reduced.
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Referring to fig. 3, a base 200 is provided, the base 200 including a substrate 201 and an epitaxial layer 202 on the substrate 201.
The materials of the substrate 201 include: silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide; the material of the epitaxial layer 202 includes: silicon, germanium, silicon carbide, gallium arsenide, or indium gallium. Specifically, in some embodiments of the present invention, the material of the substrate 201 is silicon, and the material of the epitaxial layer 202 is silicon.
Specifically, in some embodiments of the present invention, after providing the substrate 200, further includes: the epitaxial layer 202 is doped to form a drift region 203 and an initial body doped region 204 located on the drift region 203.
Specifically, in some embodiments of the present invention, the substrate 201 is doped N-type, the drift region 203 is doped N-type, and the doping concentration range of the drift region 203 is: 5E15atom/cm 3～1E17atom/cm3. The initial bulk doped region 204 is P-type doped. In other embodiments, the substrate further comprises a P-type doping, the drift region further comprises a P-type doping, and the initial body doped region further comprises an N-type doping.
After forming the initial body doped region 204, it further includes: the initial bulk doped region 204 is subjected to a thermal drive-in process. Compared with performing the thermal drive-in process after the formation of the implant doped region 209, the thermal drive-in process prevents the implant doped region 209 from excessive lateral diffusion under the thermal drive-in process before the formation of the implant doped region 209, which is beneficial to control the morphology of the implant doped region 209.
Referring to fig. 4 to 5, the substrate 200 is etched to form a gate trench 207 in the epitaxial layer 202.
The step of etching the substrate 200 to form a gate trench 207 in the epitaxial layer 202 includes: as shown in fig. 4, a hard mask layer 206 having an opening is formed on the substrate 200; as shown in fig. 5, the substrate 200 is etched using the hard mask layer 206 as a mask, to form a gate trench 207 in the epitaxial layer 202.
Specifically, in some embodiments of the present invention, before forming the hard mask layer 206 with an opening on the substrate 200, the method further includes: a barrier layer 205 is formed on the substrate 200. The material of the barrier layer 205 comprises silicon nitride. The method of forming the barrier layer 205 includes deposition. The barrier layer 205 acts as an etch stop layer for subsequent removal of the hard mask layer 206 to reduce wear on the substrate 200.
The step of forming the hard mask layer 206 includes: forming a hard mask material layer on the barrier layer 205; forming a photoresist material layer on the hard mask material layer; photoetching the photoetching material layer to form a photoetching adhesive layer; the hard mask material layer is etched using the photoresist layer as a mask, forming a hard mask layer 206 with openings. Specifically, in some embodiments of the present invention, after forming the hard mask layer 206 with the opening, the method further includes: and removing the photoresist layer.
The location of the opening of the hard mask layer 206 defines the location of the gate trench 207.
Specifically, in some embodiments of the present invention, the material of the hard mask layer 206 comprises silicon oxide, and the method of forming the hard mask material layer comprises deposition.
Specifically, in some embodiments of the present invention, the width of the gate trench 207 is less than 1 μm. The width of the gate trench 207 is: the gate trenches 207 are sized in a direction in which one gate trench 207 points toward an adjacent gate trench 207.
Referring to fig. 6, after the step of etching the substrate 200 to form the gate trench 207 in the epitaxial layer 202, an oxidation repair process is performed on the gate trench 207 to form a sacrificial protection layer 208 on the surface of the gate trench 207.
Specifically, in some embodiments of the present invention, the hard mask layer 206 is not removed during the oxidation repair process. The oxidation repair process is used to repair damage and defects on the surface of the gate trench 207.
Specifically, in some embodiments of the present invention, the material of the sacrificial protective layer 208 includes silicon oxide.
Referring to fig. 7, the substrate 200 exposed by the gate trench 207 is doped to form an implanted doped region 209 under the gate trench 207, where the position of the implanted doped region 209 corresponds to the position of the gate trench 207.
The substrate 200 exposed by the gate trench 207 is doped, and the formed implantation doped region 209 under the gate trench 207 is deeper by means of the depth of the gate trench 207, so that the maximum implantation depth of the implantation doped region 209 is deeper under the same implantation energy, the bottom of the implantation doped region 209 is closer to the bottom of the substrate 200, and the implantation doped region 209 can deplete the drift region 203 to a greater extent, thereby improving the breakdown voltage of the semiconductor device.
The location of the implanted doped region 209 corresponds to the location of the gate trench 207, namely: the projection of the implanted doped region 209 on the surface of the substrate 200 at least partially overlaps with the projection of the gate trench 207 on the surface of the substrate 200. Specifically, in some embodiments of the present invention, the projection of the gate trench 207 on the surface of the substrate 200 is within the range of the projection of the implanted doped region 209 on the surface of the substrate 200.
The hard mask layer 206 is not removed during the oxidation repair process, so that during the doping process of the substrate 200 exposed by the gate trench 207, the doping process is performed on the substrate 200 exposed by the gate trench 207 by using the hard mask layer 206 as a mask during the formation of the implanted doped region 209 under the gate trench 207.
The implantation doping region 209 is located under the gate trench 207, and the position of the implantation doping region 209 corresponds to the position of the gate trench 207, so that the same mask is used for forming the implantation doping region 209 and the gate trench 207, one mask is saved by one lithography process, and the process cost is reduced.
Specifically, in some embodiments of the present invention, in the step of doping the substrate 200 exposed by the gate trench 207 to form the implantation doped region 209 under the gate trench 207, the substrate 200 exposed by the gate trench 207 having the sacrificial protection layer 208 on the trench surface is doped to form the implantation doped region 209 under the gate trench 207.
The sacrificial protection layer 208 is adapted to act as a protection liner for the gate trench 207 during the doping process of the substrate 200 exposed by the gate trench 207 to form an implanted doped region 209 under the gate trench 207, protecting the surface of the gate trench 207.
Specifically, in some embodiments of the present invention, the substrate 200 exposed by the gate trench 207 is doped, and in the process of forming the doped region 209 under the gate trench 207, an included angle between an implantation direction of the doping process and a normal direction of the substrate 200 is in a range of: 0-7 deg.
Specifically, in some embodiments of the present invention, the dopant ions of the implanted doped region 209 are boron ions; the implantation dosage range of the implantation doped region 209 is: 1E12atom/cm 2～1E13atom/cm2; the implantation energy range of the implantation doping region 209 is: 50KeV to 4000KeV.
Referring to fig. 8 to 10, fig. 8 is a top view of fig. 9 and 10, fig. 9 is a cross-sectional view of fig. 8 at BB1, fig. 10 is a cross-sectional view of fig. 8 at CC1, and fig. 8 does not show the hard mask layer 206 and the blocking layer 205. After the substrate 200 exposed by the gate trench 207 is doped to form an implant doped region 209 under the gate trench 207, the substrate 200 between the gate trench 207 and the implant doped region 209 is doped to form a transition doped region 210 between the bottom of the gate trench 207 and the implant doped region 209, the transition doped region 210 being electrically connected to the implant doped region 209 and the position of the transition doped region 210 corresponding to the position of the implant doped region 209.
The location of the transitional doped region 210 corresponds to the location of the implanted doped region 209, namely: the projection of the implanted doped region 209 onto the surface of the substrate 200 at least partially overlaps with the projection of the transitional doped region 210 onto the surface of the substrate 200. Specifically, in some embodiments of the present invention, the projection of the doped implant region 209 on the surface of the substrate 200 is within the projection range of the doped transition region 210 on the surface of the substrate 200.
Specifically, referring to fig. 10, in some embodiments of the present invention, the transitional doped region 210 further extends between the gate trench 207 and the drift region 203. The transitional doped region 210 also extends between the gate trench 207 and the initial body doped region 204.
Specifically, referring to fig. 10, in some embodiments of the present invention, the length of the gate trench 207 is greater than 10 μm. The length of the gate trench 207 is: the gate trench 207 is sized along the extension direction of the gate trench 207.
In the process of doping the substrate 200 between the gate trench 207 and the implantation doping region 209 to form a transition doping region 210 between the bottom of the gate trench 207 and the implantation doping region 209, the substrate 200 between the gate trench 207 and the implantation doping region 209 is doped with the hard mask layer 206 as a mask.
The transitional doped region 210 is located between the bottom of the gate trench 207 and the implanted doped region 209, and the position of the transitional doped region 210 corresponds to the position of the implanted doped region 209, so that a new mask is not required to be introduced to form the transitional doped region 210, and the process cost is reduced.
The substrate 200 exposed by the gate trench 207 is doped to form an implanted doped region 209 under the gate trench 207 with a smaller doping amount than the substrate 200 between the gate trench 207 and the implanted doped region 209, forming a transitional doped region 210 between the bottom of the gate trench 207 and the implanted doped region 209. The transitional doped region 210 is heavily doped and implanted, and the doping concentration of the transitional doped region 210 is greater than the doping concentration of the implanted doped region 209.
The transitional doped region 210 is used for electrically connecting the implanted doped region 209, and the doping concentration of the transitional doped region 210 is higher, so that the resistance of the semiconductor device is reduced, and the response speed is increased.
The implant dose range of the transitional doped region 210 is: 1E14atom/cm 2～5E15atom/cm2; the implantation energy range of the transitional doped region 210 is: 10KeV to 100KeV. Specifically, in some embodiments of the present invention, when the ion implanted into the transitional doped region 210 is boron (B), the implantation energy ranges from 2KeV to 25KeV, and the implantation dose ranges from 1E14atom/cm 2～5E15cmatom/cm2; when the ion implantation of the transitional doped region 210 is boron difluoride (BF 2), the implantation energy ranges from 10KeV to 100KeV, and the implantation dose ranges from 1e14atom/cm 2～5E15 atom/cm2.
Table 1 is a data plot of breakdown voltage of a device as a function of dopant amount of the transitional doped region 210.
TABLE 1
As the amount of dopant in the transitional doped region 210 increases, the resistance of the transitional doped region 210 decreases, increasing the response speed of the device. Meanwhile, as can be seen from table 1, as the amount of dopant in the transitional doped region 210 increases, the breakdown voltage of the device decreases.
Therefore, the dopant amount of the transitional doped region 210 needs to be controlled, so as to avoid the excessive dopant amount of the transitional doped region 210, which causes the breakdown voltage of the device to be reduced; too small a dopant amount of the transitional doped region 210 is avoided, resulting in too slow a response speed of the device.
The substrate 200 between the gate trench 207 and the implanted doped region 209 is doped, and an included angle between an implantation direction of the doping process and a normal direction of the substrate 200 is 15 ° to 45 ° in a process of forming a transitional doped region 210 between a bottom of the gate trench 207 and the implanted doped region 209. The inclined implantation angle is adopted, so that the cross-sectional area of a transitional doping region 210 which is the same type as the implantation doping region 209 and formed at the side wall of the gate trench 207 and the bottom of the gate trench 207 is larger in the direction parallel to the surface of the substrate, the contact area between the transitional doping region 210 and the initial body doping region 204 is increased, and the electrical connection between the transitional doping region 210 and the initial body doping region 204 is enhanced.
Referring to fig. 11, the view angle of fig. 11 is the same as that of fig. 9, and after the transitional doped region 210 is formed, the hard mask layer 206 (shown in fig. 9) and the sacrificial protection layer 208 (shown in fig. 9) are removed.
Specifically, in some embodiments of the present invention, a wet etch is used to remove the hard mask layer 206 and the sacrificial protection layer 208. The hard mask layer 206 and the sacrificial protection layer 208 are removed in one step, saving process costs.
Referring to fig. 12, a gate structure 211 is formed in the gate trench 207.
The step of forming the gate structure 211 in the gate trench 207 includes: forming a gate dielectric layer 212 on the side wall of the gate trench 207 and the bottom of the gate trench 207; a gate layer 213 is formed within the gate trench 207 having the gate dielectric layer 212.
Specifically, in some embodiments of the present invention, a low temperature thermal oxidation process is used to form a first gate oxide layer on the sidewall of the gate trench 207 and the bottom of the gate trench 207; forming a second gate oxide layer on the first gate oxide layer by adopting a deposition process; a gate layer 213 is formed within the gate trench 207 having a first gate oxide layer and a second gate oxide layer located over the first gate oxide layer to form the gate structure 211.
Specifically, in some embodiments of the present invention, the step of forming the second gate oxide layer includes: depositing a TEOS silicon oxide layer; the TEOS silicon oxide layer is rapidly annealed. The purpose of the rapid anneal is to densify the TEOS silicon oxide layer.
The gate layer 213 is made of polysilicon. The step of forming the gate layer 213 includes: forming an initial gate layer within a gate trench 207 having a first gate oxide layer and a second gate oxide layer located on the first gate oxide layer; and flattening the initial gate layer to form the gate layer 213.
The planarization method includes a mechanical polishing method, a chemical polishing method, a fluid polishing method, a chemical mechanical polishing method, and the like. Specifically, in this embodiment, the first planarization method is a chemical mechanical polishing method. Unlike traditional mechanical polishing method, chemical mechanical polishing method has the combined chemical and mechanical effect to avoid the damage of the surface caused by mechanical polishing and the low polishing speed, poor surface flatness and polishing consistency caused by chemical polishing. Chemical mechanical polishing is widely used for high planarization polishing of various materials on the nanometer scale.
Specifically, in some embodiments of the present invention, the thickness range of the first gate oxide layer is: 100-400 angstroms; the oxidation temperature range of the low-temperature thermal oxidation process is as follows: 800-930 ℃; the low temperature thermal oxidation process takes less than 30 minutes.
The first gate oxide layer and the second gate oxide layer adopt a mode of combining low-temperature oxidation and deposition, so that the thermal process introduced by thermal growth is reduced, and the degree of lateral diffusion of the implanted doped region 209 is reduced.
The transition doped region 210 is doped by heavily doping, and after thermal diffusion, the diffusion speed of the transition doped region 210 in the direction parallel to the surface of the substrate 200 is greater than the diffusion speed of the implanted doped region 209 in the direction parallel to the surface of the substrate 200.
Referring to fig. 13, after the gate structure 211 is formed, the initial body doped regions 204 (as shown in fig. 12) located at two sides of the gate structure 211 are doped to form a first heavily doped layer 214 and a body doped region 217; forming an interlayer dielectric layer 215 on the gate structure 211 and the first heavily doped layer 214; forming a through hole penetrating through the first heavily doped layer 214 and the interlayer dielectric layer 215; and doping the body doped region exposed at the bottom of the through hole to form a second heavily doped layer 216.
The first heavily doped layer 214 is a source heavily doped layer. Specifically, in some embodiments of the present invention, the first heavily doped layer 214 is heavily doped N-type, and the second heavily doped layer 216 is heavily doped P-type. In other embodiments, the first heavily doped layer may be P-type heavily doped, and the second heavily doped layer may be N-type heavily doped.
Specifically, in some embodiments of the present invention, the transitional doped region 210 also extends between the gate structure 211 and the body doped region 217.
The step of forming a via hole through the first heavily doped layer 214 and the interlayer dielectric layer 215 includes: forming a mask layer on the interlayer dielectric layer 215, wherein a part of the interlayer dielectric layer 215 is exposed out of the mask layer; and etching the interlayer dielectric layer 215 by taking the mask layer as a mask to form a through hole penetrating through the first heavily doped layer 214 and the interlayer dielectric layer 215. Specifically, in some embodiments of the present invention, the mask layer is not removed after the via is formed.
Doping treatment is performed on the body doped region 217 exposed at the bottom of the through hole, and the step of forming the second heavily doped layer 216 includes: and doping the body doped region 217 exposed at the bottom of the through hole by using the mask layer as a mask to form a second heavily doped layer 216. The second heavily doped layer 216 is of opposite doping type to the first heavily doped layer 214. Specifically, in some embodiments of the present invention, the second heavily doped layer 216 is P-type heavily doped, and in other embodiments, the second heavily doped layer may also be N-type heavily doped.
After forming the second heavily doped layer 216, further includes: a conductive plug 218 is formed within the via.
Referring to fig. 14 to 16, fig. 14 is a top view of fig. 15 and 16, fig. 15 is a cross-sectional view of fig. 14 at BB1, and fig. 16 is a cross-sectional view of fig. 14 at CC 1. Forming a drain metal layer 219 on a side of the substrate 201 facing away from the epitaxial layer 202; a source metal layer 220 is formed over the conductive plug 218 and a gate metal layer 221 is formed over the gate structure 211.
Correspondingly, an embodiment of the present invention further provides a semiconductor structure, referring to fig. 15, including: a substrate 200, the substrate 200 comprising a drift region 203; a gate structure 211 partially within the drift region 203; an implant doped region 209 having a doping type opposite to that of the drift region 203, the implant doped region 209 being located under the gate structure 211, the location of the implant doped region 209 corresponding to the location of the gate structure 211.
The semiconductor structure includes: a substrate 200, said substrate 200 comprising a drift region 203.
The base 200 includes a substrate 201 and an epitaxial layer 202 (shown in fig. 5) on the substrate 201, and the drift region 203 is located within the epitaxial layer 202.
The materials of the substrate 201 include: silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide; the material of the epitaxial layer 202 includes: silicon, germanium, silicon carbide, gallium arsenide, or indium gallium. Specifically, in some embodiments of the present invention, the material of the substrate 201 is silicon, and the material of the epitaxial layer 202 is silicon.
Specifically, in some embodiments of the present invention, the substrate 201 is doped N-type, the epitaxial layer 202 is doped N-type, and the doping concentration of the epitaxial layer 202 is in the following range: 5E15atom/cm 3～1E17atom/cm3.
The semiconductor structure includes: and a body doped region 217 on the drift region 203, wherein the doping type of the body doped region 217 is opposite to the doping type of the drift region 203. Specifically, in some embodiments of the present invention, the body doped region 217 is a P-type dopant. In other embodiments, the substrate further comprises a P-type doping, the epitaxial layer further comprises a P-type doping, and the body doped region 217 further comprises an N-type doping.
The semiconductor structure includes: a gate structure 211 is partially located within the drift region 203.
The gate structure 211 includes a gate dielectric layer 212 and a gate layer 213 on the gate dielectric layer 212; specifically, in some embodiments of the present invention, the gate structure 211 includes: a first gate oxide layer, a second gate oxide layer on the first gate oxide layer, and a gate layer 213 on the second gate oxide layer.
The first gate oxide layer is made of silicon oxide; the second gate oxide layer is made of silicon oxide; the gate layer 213 is made of polysilicon. The thickness range of the first gate oxide layer is as follows: 100 angstroms to 400 angstroms.
The semiconductor structure includes: an implant doped region 209 having a doping type opposite to that of the drift region 203, the implant doped region 209 being located under the gate structure 211, the location of the implant doped region 209 corresponding to the location of the gate structure 211.
The projection of the implanted doped region 209 on the surface of the substrate 200 at least partially overlaps with the projection of the gate structure 211 on the surface of the substrate 200. Specifically, in some embodiments of the present invention, the projection of the gate structure 211 on the surface of the substrate 200 is within the range of the projection of the implanted doping region 209 on the surface of the substrate 200.
The semiconductor structure includes: a transition doped region 210 having the same doping type is located between the gate structure 211 and the implantation doped region 209, the transition doped region 210 is electrically contacted with the implantation doped region 209, and a position of the transition doped region 210 corresponds to the implantation doped region 209.
The doping concentration of the transitional doping region 210 is greater than the doping concentration of the implanted doping region 209.
The projection of the implanted doped region 209 onto the surface of the substrate 200 at least partially overlaps with the projection of the transitional doped region 210 onto the surface of the substrate 200.
The projection of the implanted doped region 209 on the surface of the substrate 200 is within the projection range of the transitional doped region 210 on the surface of the substrate 200.
The transitional doped region 210 also extends between the gate structure 211 and the drift region 203.
The gate structure 211 extends through the body doped region in a direction perpendicular to the surface of the substrate 200 and the body doped region 217 is electrically connected to the transition doped region 210.
The transitional doped region 210 also extends between the gate structure 211 and the body doped region 217.
The semiconductor structure includes: a first heavily doped layer 214 located on the bulk doped region 217, the doping type of the first heavily doped layer 214 being opposite to the doping type of the bulk doped region 217.
The gate structure 211 penetrates the first heavily doped layer 214 in a direction perpendicular to the surface of the substrate 200.
The semiconductor structure includes: a conductive plug 218 extending through the first heavily doped layer 214, the conductive plug 218 being electrically connected to the body doped region; and a second heavily doped layer 216 located at the bottom of the conductive plug 218, the second heavily doped layer 216 being electrically connected to the conductive plug 218, the second heavily doped layer 216 having a doping type identical to that of the bulk doped region, and the second heavily doped layer 216 having a doping concentration greater than that of the bulk doped region.
The semiconductor structure includes: a drain metal layer 219 on a side of the substrate 201 facing away from the epitaxial layer 202.
The semiconductor structure includes: a source metal layer 220 on the conductive plug 218 and a gate metal layer 221 on the gate structure 211.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (23)
1. A semiconductor structure, comprising:
a substrate comprising a drift region;
A gate structure partially within the drift region;
and the doping type of the injection doping region is opposite to that of the drift region, the injection doping region is positioned under the gate structure, and the position of the injection doping region corresponds to that of the gate structure.
2. The semiconductor structure of claim 1, wherein a projection of the implanted doped region onto a substrate surface at least partially overlaps with a projection of the gate structure onto the substrate surface.
3. The semiconductor structure of claim 1, wherein a projection of the gate structure onto the substrate surface is within a range of a projection of the implanted doping region onto the substrate surface.
4. The semiconductor structure of claim 1, further comprising: and the transition doped region is positioned between the grid structure and the injection doped region and has the same doping type, the transition doped region is electrically contacted with the injection doped region, and the position of the transition doped region corresponds to the injection doped region.
5. The semiconductor structure of claim 4, wherein a doping concentration of the transitional doped region is greater than a doping concentration of the implanted doped region.
6. The semiconductor structure of claim 4, wherein a projection of the implant doped region onto the substrate surface at least partially overlaps with a projection of the transition doped region onto the substrate surface.
7. The semiconductor structure of claim 4, wherein a projection of the implant doped region onto the substrate surface is within a projection of the transition doped region onto the substrate surface.
8. The semiconductor structure of claim 4, wherein the transitional doped region further extends between the gate structure and the drift region.
9. The semiconductor structure of claim 4, further comprising: a bulk doped region located on the drift region, the bulk doped region having a doping type opposite to a doping type of the drift region; the gate structure penetrates through the body doping region along a direction perpendicular to the substrate surface and the body doping region is electrically connected with the transition doping region.
10. The semiconductor structure of claim 9, wherein the transitional doped region further extends between the gate structure and the bulk doped region.
11. The semiconductor structure of claim 9, further comprising: the first heavily doped layer is positioned on the body doped region, and the doping type of the first heavily doped layer is opposite to that of the body doped region;
The gate structure penetrates through the first heavily doped layer along the direction vertical to the surface of the substrate.
12. The semiconductor structure of claim 11, further comprising: a conductive plug passing through the first heavily doped layer, the conductive plug being electrically connected with the body doped region; the second heavily doped layer is positioned at the bottom of the conductive plug, is electrically connected with the conductive plug, has the same doping type as the doping type of the bulk doped region, and has a doping concentration greater than that of the bulk doped region.
13. A method of forming a semiconductor structure, comprising:
Providing a substrate, wherein the substrate comprises a substrate and an epitaxial layer positioned on the substrate;
etching the substrate to form a gate trench in the epitaxial layer;
doping the substrate exposed by the gate trench to form an implantation doping region positioned below the gate trench, wherein the position of the implantation doping region corresponds to the position of the gate trench;
and forming a gate structure in the gate trench.
14. The method of forming a semiconductor structure of claim 13, wherein etching the substrate to form a gate trench in the epitaxial layer comprises:
forming a hard mask layer with an opening on the substrate;
and etching the substrate by taking the hard mask layer as a mask to form a grid groove in the epitaxial layer.
15. The method of claim 14, wherein the substrate exposed by the gate trench is doped with the hard mask layer as a mask during the forming of the implanted region under the gate trench.
16. The method of forming a semiconductor structure of claim 14, wherein after doping the exposed substrate of the gate trench to form an implant doped region under the gate trench, prior to forming a gate structure in the gate trench, further comprising: and doping the substrate between the gate trench and the implantation doping region to form a transition doping region between the bottom of the gate trench and the implantation doping region, wherein the transition doping region is electrically connected with the implantation doping region, and the position of the transition doping region corresponds to the position of the implantation doping region.
17. The method of claim 16, wherein the doping process is performed on the substrate between the gate trench and the implanted region using the hard mask layer as a mask during the forming of the transition doped region between the bottom of the gate trench and the implanted region.
18. The method of claim 17, wherein doping the exposed substrate of the gate trench to form an implanted doped region beneath the gate trench has a doping dose less than a doping dose of doping the substrate between the gate trench and the implanted doped region to form a transitional doped region between the bottom of the gate trench and the implanted doped region.
19. The method of claim 16, wherein a doping process is performed on the substrate between the gate trench and the implanted doped region, and an angle between an implantation direction of the doping process and a normal direction of the substrate ranges from 15 ° to 45 ° during formation of a transition doped region between a bottom of the gate trench and the implanted doped region.
20. The method of forming a semiconductor structure of claim 13, further comprising: after the step of etching the substrate to form a gate trench in the epitaxial layer, doping the substrate exposed by the gate trench to form an implanted doped region under the gate trench, and performing oxidation repair treatment on the gate trench to form a sacrificial protection layer on the surface of the gate trench;
And in the step of doping the substrate exposed by the gate trench to form an implantation doped region under the gate trench, doping the substrate exposed by the gate trench with the sacrificial protection layer on the surface of the trench to form the implantation doped region under the gate trench.
21. The method of forming a semiconductor structure of claim 13, wherein forming a gate structure within the gate trench comprises:
Forming a first gate oxide layer on the side wall of the gate trench and the bottom of the gate trench by adopting a low-temperature thermal oxidation process;
Forming a second gate oxide layer on the first gate oxide layer by adopting a deposition process;
forming a gate layer in a gate trench having a first gate oxide layer and a second gate oxide layer on the first gate oxide layer to form the gate structure.
22. The method of forming a semiconductor structure of claim 13, further comprising, prior to etching the substrate to form a gate trench in the epitaxial layer: and doping the epitaxial layer to form a drift region and an initial body doping region positioned on the drift region.
23. The method of forming a semiconductor structure of claim 22, further comprising: and after the grid structure is formed, carrying out doping treatment on the initial body doping regions positioned at two sides of the grid structure to form a first heavily doped layer.
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