CN119028264A

CN119028264A - Pixel circuit, driving method and display device

Info

Publication number: CN119028264A
Application number: CN202310611988.4A
Authority: CN
Inventors: 玄明花; 郑皓亮; 齐琪
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd
Priority date: 2023-05-26
Filing date: 2023-05-26
Publication date: 2024-11-26
Also published as: WO2024244764A1

Abstract

The present invention provides a pixel circuit, a driving method and a display device. The pixel circuit includes a driving circuit, a first on-off control circuit, a light-emitting element, a second on-off control circuit, a first control circuit and a second control circuit; the first on-off control circuit controls the connection or disconnection between the second node and the third node under the control of the potential of the first control node; the second on-off control circuit controls the connection or disconnection between the second pole of the light-emitting element and the first voltage terminal under the control of the potential of the second control node; the first control circuit controls the potential of the first control node according to the first time control data voltage under the control of the first control signal; the second control circuit controls the potential of the second control node according to the second time control data voltage under the control of the second control signal. The present invention realizes different grayscales by coordinating current regulation and light-emitting time regulation.

Description

Pixel circuit, driving method and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a pixel circuit, a driving method, and a display device.

Background

With the market and popularization of Mini LED direct display products, micro LED display technology is also urgent. The Micro LED has the characteristics of high photoelectric conversion efficiency under high current density, low photoelectric conversion efficiency under low current density, different brightness among LED chips under low current density and color shift. As the size of LEDs decreases from Mini LEDs to Micro LED levels, the duty cycle of the decrease in photo-electric efficiency caused by defects in the LED process may be amplified, resulting in low efficiency of Micro LEDs. The problems of low photoelectric efficiency and low color and brightness of the Micro LED under low current density lead to that the pixel driving circuit adopted by the Mini LED cannot be directly used, and the corresponding pixel circuit needs to be developed according to the characteristics of the Micro LED.

Disclosure of Invention

In one aspect, an embodiment of the present invention provides a pixel circuit including a driving circuit, a first on-off control circuit, a light emitting element, a second on-off control circuit, a first control circuit, and a second control circuit;

the first end of the driving circuit is electrically connected with the first node, and the second end of the driving circuit is electrically connected with the second node; the driving circuit is used for generating driving current for driving the light-emitting element under the control of the potential of the control end of the driving circuit;

The first on-off control circuit is used for controlling the connection or disconnection between the second node and the third node under the control of the potential of the first control node;

a first electrode of the light emitting element is electrically connected to the third node;

The second on-off control circuit is used for controlling connection or disconnection between the second pole and the first voltage end of the light-emitting element under the control of the potential of the second control node;

the first control circuit is electrically connected with a first control end, a data line, a first light-emitting time control end, a second light-emitting time control end and the first control node respectively and is used for controlling the first light-emitting time control end or the second light-emitting time control end to be communicated with the first control node according to a first time control data voltage provided by the data line under the control of a first control signal provided by the first control end;

The second control circuit is electrically connected with the second control end, the data line, the second light-emitting time control end, the third light-emitting time control end and the second control node respectively, and is used for controlling the second light-emitting time control end or the third light-emitting time control end to be communicated with the second control node according to the second time control data voltage provided by the data line under the control of the second control signal provided by the second control end.

Optionally, the first control circuit includes a first write circuit, a first tank circuit, a first switch control circuit, and a second switch control circuit;

The first write circuit is electrically connected with a first control end, the data line and a first switch node respectively and is used for writing the first time control data voltage into the first switch node under the control of a first control signal provided by the first control end;

the first energy storage circuit is electrically connected with the first switch node and is used for maintaining the potential of the first switch node;

the first switch control circuit is respectively and electrically connected with the first switch node, the second light-emitting time control end and the first control node and is used for controlling the connection or disconnection between the first control node and the second light-emitting time control end under the control of the potential of the first switch node;

The second switch control circuit is respectively and electrically connected with the first switch node, the first light-emitting time control end and the first control node and is used for controlling the connection or disconnection between the first control node and the first light-emitting time control end under the control of the potential of the first switch node.

Optionally, the second control circuit includes a second write circuit, a second tank circuit, a third switch control circuit, and a fourth switch control circuit;

the second write circuit is electrically connected with a second control end, the data line and a second switch node respectively and is used for writing a second time control data voltage provided by the data line into the second switch node under the control of a second control signal provided by the second control end;

the second energy storage circuit is electrically connected with the second switch node and is used for maintaining the potential of the second switch node;

The third switch control circuit is respectively and electrically connected with a second switch node, a third light-emitting time control end and the second control node and is used for controlling the connection or disconnection between the second control node and the third light-emitting time control end under the control of the potential of the second switch node;

the fourth switch control circuit is respectively and electrically connected with the second switch node, the second light-emitting time control end and the second control node and is used for controlling the connection or disconnection between the second control node and the second light-emitting time control end under the control of the potential of the second switch node.

Optionally, the first control circuit includes a third write circuit, a fourth write circuit, a fifth switch control circuit, a sixth switch control circuit, a third tank circuit, and a fourth tank circuit; the first control end comprises a first reset control end and a second reset control end;

The third write circuit is electrically connected with the first reset control end, the data line and the third switch node respectively and is used for writing a third time control data voltage provided by the data line into the third switch node under the control of a first reset control signal provided by the first reset control end;

the third energy storage circuit is electrically connected with the third switch node and is used for maintaining the potential of the third switch node;

The fourth write circuit is electrically connected with the second reset control end, the data line and the fourth switching node respectively and is used for writing a fourth time control data voltage provided by the data line into the fourth switching node under the control of a second reset control signal provided by the second reset control end;

the fourth energy storage circuit is electrically connected with the fourth switching node and is used for maintaining the potential of the fourth switching node;

The fifth switch control circuit is respectively and electrically connected with the third switch node, the second light-emitting time control end and the first control node and is used for controlling the connection or disconnection between the second light-emitting time control end and the first control node under the control of the potential of the third switch node;

The sixth switch control circuit is electrically connected with the fourth switch node, the first light-emitting time control end and the first control node respectively and is used for controlling the connection or disconnection between the first light-emitting time control end and the first control node under the control of the potential of the fourth switch node.

Optionally, the second control circuit includes a fifth write circuit, a sixth write circuit, a seventh switch control circuit, an eighth switch control circuit, a fifth tank circuit, and a sixth tank circuit; the second control end comprises a third reset control end and a fourth reset control end;

the fifth writing circuit is electrically connected with the third reset control end, the data line and a fifth switch node respectively and is used for writing a fifth time control data voltage provided by the data line into the fifth switch node under the control of a third reset control signal provided by the third reset control end;

The fifth energy storage circuit is electrically connected with the fifth switch node and is used for maintaining the potential of the fifth switch node;

The sixth write circuit is electrically connected with the fourth reset control end, the data line and a sixth switching node respectively, and is used for writing a sixth time control data voltage provided by the data line into the sixth switching node under the control of a fourth reset control signal provided by the fourth reset control end;

the sixth energy storage circuit is electrically connected with the sixth switching node and is used for maintaining the potential of the sixth switching node;

The seventh switch control circuit is electrically connected with the fifth switch node, the second light-emitting time control end and the second control node respectively and is used for controlling the connection or disconnection between the second light-emitting time control end and the second control node under the control of the potential of the fifth switch node;

The eighth switch control circuit is electrically connected with the sixth switch node, the third light-emitting time control end and the second control node respectively and is used for controlling the connection or disconnection between the third light-emitting time control end and the second control node under the control of the potential of the sixth switch node.

Optionally, the driving circuit includes a driving transistor;

The grid electrode of the driving transistor is electrically connected with the control end of the driving circuit, the first electrode of the driving circuit is electrically connected with the first node, and the second electrode of the driving circuit is electrically connected with the second node;

The first on-off control circuit comprises a first control transistor, and the second on-off control circuit comprises a second control transistor;

The grid electrode of the first control transistor is electrically connected with the first control node, the first pole of the first control transistor is electrically connected with the second node, and the second pole of the first control transistor is electrically connected with the third node;

the grid electrode of the second control transistor is electrically connected with the second control node, the first electrode of the second control transistor is electrically connected with the second electrode of the light emitting element, and the second electrode of the second control transistor is electrically connected with the first voltage end.

Optionally, the first write circuit includes a first transistor, the first tank circuit includes a first capacitor, the first switch control circuit includes a second transistor, and the second switch control circuit includes a third transistor;

The grid electrode of the first transistor is electrically connected with the first control end, the first electrode of the first transistor is electrically connected with the data line, and the second electrode of the first transistor is electrically connected with the first switch node;

A first end of the first capacitor is electrically connected with the first switch node, and a second end of the first capacitor is electrically connected with an initial voltage end;

The grid electrode of the second transistor is electrically connected with a first switch node, the first electrode of the second transistor is electrically connected with the second light-emitting time control end, and the second electrode of the second transistor is electrically connected with the first control node;

The gate of the third transistor is electrically connected to the first switching node, the first pole of the third transistor is electrically connected to the first light-emitting time control terminal, and the second pole of the third transistor is electrically connected to the first control node.

Optionally, the second write circuit includes a fourth transistor, the second tank circuit includes a second capacitor, the third switch control circuit includes a fifth transistor, and the fourth switch control circuit includes a sixth transistor;

The grid electrode of the fourth transistor is electrically connected with the second control end, the first electrode of the fourth transistor is electrically connected with the data line, and the second electrode of the fourth transistor is electrically connected with the second switch node;

the first end of the second capacitor is electrically connected with the second switch node, and the second end of the second capacitor is electrically connected with the initial voltage end;

The grid electrode of the fifth transistor is electrically connected with the second switch node, the first electrode of the fifth transistor is electrically connected with the third light-emitting time control end, and the second electrode of the fifth transistor is electrically connected with the second control node;

the grid electrode of the sixth transistor is electrically connected with the second switch node, the first electrode of the sixth transistor is electrically connected with the second light-emitting time control end, and the second electrode of the sixth transistor is electrically connected with the second control node.

Optionally, the third write circuit includes a seventh transistor, the fourth write circuit includes an eighth transistor, the third tank circuit includes a third capacitor, the fourth tank circuit includes a fourth capacitor, the fifth switch control circuit includes a ninth transistor, and the sixth switch control circuit includes a tenth transistor;

The grid electrode of the seventh transistor is electrically connected with the first reset control end, the first electrode of the seventh transistor is electrically connected with the data line, and the second electrode of the seventh transistor is electrically connected with the third switch node;

the first end of the third capacitor is electrically connected with the third switch node, and the second end of the third capacitor is electrically connected with the initial voltage end;

The grid electrode of the eighth transistor is electrically connected with the second reset control end, the first electrode of the eighth transistor is electrically connected with the data line, and the second electrode of the eighth transistor is electrically connected with the fourth joint point;

the first end of the fourth capacitor is electrically connected with the fourth switching point, and the second end of the fourth capacitor is electrically connected with the initial voltage end;

the grid electrode of the ninth transistor is electrically connected with the third switch node, the first electrode of the ninth transistor is electrically connected with the second light-emitting time control end, and the second electrode of the ninth transistor is electrically connected with the first control node;

the grid electrode of the tenth transistor is electrically connected with the fourth joint point, the first electrode of the tenth transistor is electrically connected with the first light-emitting time control end, and the second electrode of the tenth transistor is electrically connected with the first control node.

Optionally, the fifth write circuit includes an eleventh transistor, the sixth write circuit includes a twelfth transistor, the seventh switch control circuit includes a thirteenth transistor, the eighth switch control circuit includes a fourteenth transistor, the fifth tank circuit includes a fifth capacitor, and the sixth tank circuit includes a sixth capacitor;

The grid electrode of the eleventh transistor is electrically connected with the third reset control end, the first electrode of the eleventh transistor is electrically connected with the data line, and the second electrode of the eleventh transistor is electrically connected with the fifth switch node;

the first end of the fifth capacitor is electrically connected with the fifth switch node, and the second end of the fifth capacitor is electrically connected with the initial voltage end;

the grid electrode of the twelfth transistor is electrically connected with the fourth reset control end, the first electrode of the twelfth transistor is electrically connected with the data line, and the second electrode of the twelfth transistor is electrically connected with the sixth switching point;

The first end of the sixth capacitor is electrically connected with the sixth joint point, and the second end of the sixth capacitor is electrically connected with the initial voltage end;

the grid electrode of the thirteenth transistor is electrically connected with the fifth switch node, the first electrode of the thirteenth transistor is electrically connected with the second light-emitting time control end, and the second electrode of the thirteenth transistor is electrically connected with the second control node;

The grid electrode of the fourteenth transistor is electrically connected with the sixth switching point, the first electrode of the fourteenth transistor is electrically connected with the third light-emitting time control end, and the second electrode of the fourteenth transistor is electrically connected with the second control node.

Optionally, the pixel circuit according to at least one embodiment of the present invention further includes a data writing circuit, a compensation control circuit, and a seventh tank circuit;

the data writing circuit is respectively and electrically connected with the scanning line, the data line and the first node and is used for writing current control data voltage provided by the data line into the first node under the control of a scanning signal provided by the scanning line;

the compensation control circuit is respectively and electrically connected with the scanning line, the control end of the driving circuit and the second node and is used for controlling the connection or disconnection between the control end of the driving circuit and the second node under the control of the scanning signal;

the seventh energy storage circuit is electrically connected with the control end of the driving circuit and is used for storing electric energy.

Optionally, the pixel circuit according to at least one embodiment of the present invention further includes a first initialization circuit and a second initialization circuit;

The first initializing circuit is respectively and electrically connected with a first control end, an initial voltage end and a control end of the driving circuit and is used for writing initial voltage provided by the initial voltage end into the control end of the driving circuit under the control of a first control signal provided by the first control end;

The second initializing circuit is electrically connected with the first control terminal, the initial voltage terminal and the first electrode of the light emitting element respectively, and is used for writing the initial voltage into the first electrode of the light emitting element under the control of the first control signal.

Optionally, the pixel circuit according to at least one embodiment of the present invention further includes a light emission control circuit;

The light-emitting control circuit is respectively and electrically connected with the second light-emitting time control end, the power voltage end and the first node and is used for controlling the communication between the power voltage end and the first node under the control of a second light-emitting time control signal provided by the second light-emitting time control end.

Optionally, the first control end includes a first reset control end and a second reset control end;

the pixel circuit further comprises a first initialization circuit and a second initialization circuit;

The first initialization circuit is respectively and electrically connected with a first reset control end, an initial voltage end and a control end of the driving circuit, and is used for writing the initial voltage provided by the initial voltage end into the control end of the driving circuit under the control of a first reset control signal provided by the first reset control end;

The second initialization circuit is electrically connected with the first reset control terminal, the initial voltage terminal and the first electrode of the light emitting element respectively, and is used for writing the initial voltage into the first electrode of the light emitting element under the control of the first reset control signal.

Optionally, the pixel circuit according to at least one embodiment of the present invention further includes a compensation control circuit, a data writing circuit, and an eighth tank circuit; the first node is electrically connected with a power supply voltage end;

The first end of the eighth energy storage circuit is electrically connected with the control end of the driving circuit; the eighth energy storage circuit is used for storing electric energy;

The compensation control circuit is respectively and electrically connected with the scanning line, the control end of the driving circuit and the second node and is used for controlling the connection or disconnection between the control end of the driving circuit and the second node under the control of a scanning signal provided by the scanning line;

the data writing circuit is electrically connected with the scanning line, the data line and the second end of the eighth energy storage circuit respectively and is used for writing current control data voltage provided by the data line into the second end of the eighth energy storage circuit under the control of the scanning signal.

Optionally, the pixel circuit according to at least one embodiment of the present invention further includes a reference voltage writing circuit;

The reference voltage writing circuit is electrically connected with the first control end, the second light-emitting time control end, the reference voltage end and the second end of the eighth energy storage circuit respectively, and is used for writing the reference voltage provided by the reference voltage end into the second end of the eighth energy storage circuit under the control of the first control signal provided by the first control end and writing the reference voltage into the second end of the eighth energy storage circuit under the control of the second light-emitting time control signal provided by the second light-emitting time control end.

Optionally, the data writing circuit includes a fifteenth transistor, the compensation control circuit includes a sixteenth transistor, and the seventh tank circuit includes a first storage capacitor;

a gate of the fifteenth transistor is electrically connected to the scan line, a first electrode of the fifteenth transistor is electrically connected to the data line, and a second electrode of the fifteenth transistor is electrically connected to the first node;

a gate of the sixteenth transistor is electrically connected to the scan line, a first electrode of the sixteenth transistor is electrically connected to the control terminal of the driving circuit, and a second electrode of the sixteenth transistor is electrically connected to the second node;

The first end of the first storage capacitor is electrically connected with the control end of the driving circuit, and the second end of the first storage capacitor is electrically connected with the power supply voltage end.

Optionally, the first initializing circuit includes a seventeenth transistor, and the second initializing circuit includes an eighteenth transistor;

A grid electrode of the seventeenth transistor is electrically connected with the first control end, a first electrode of the seventeenth transistor is electrically connected with the initial voltage end, and a second electrode of the seventeenth transistor is electrically connected with the control end of the driving circuit;

The grid electrode of the eighteenth transistor is electrically connected with the first control end, the first electrode of the eighteenth transistor is electrically connected with the initial voltage end, and the second electrode of the eighteenth transistor is electrically connected with the first electrode of the light-emitting element.

Optionally, the light emission control circuit includes a nineteenth transistor;

The grid electrode of the nineteenth transistor is electrically connected with the second light-emitting time control end, the first electrode of the nineteenth transistor is electrically connected with the power supply voltage end, and the second electrode of the nineteenth transistor is electrically connected with the first node.

a gate of the seventeenth transistor is electrically connected to the first reset control terminal, a first pole of the seventeenth transistor is electrically connected to the initial voltage terminal, and a second pole of the seventeenth transistor is electrically connected to the control terminal of the driving circuit;

The gate of the eighteenth transistor is electrically connected to the first reset control terminal, the first electrode of the eighteenth transistor is electrically connected to the initial voltage terminal, and the second electrode of the eighteenth transistor is electrically connected to the first electrode of the light emitting element.

Optionally, the compensation control circuit includes a sixteenth transistor, the data writing circuit includes a fifteenth transistor, and the eighth tank circuit includes a second storage capacitor;

The first end of the second storage capacitor is electrically connected with the control end of the driving circuit;

the gate of the fifteenth transistor is electrically connected to the scan line, the first electrode of the fifteenth transistor is electrically connected to the data line, and the second electrode of the fifteenth transistor is electrically connected to the second end of the second storage capacitor.

Optionally, the reference voltage writing circuit includes a nineteenth transistor and a twentieth transistor;

A grid electrode of the nineteenth transistor is electrically connected with the first control end, a first electrode of the nineteenth transistor is electrically connected with the reference voltage end, and a second electrode of the nineteenth transistor is electrically connected with the second end of the eighth energy storage circuit;

The grid electrode of the twentieth transistor is electrically connected with the second light-emitting time control end, the first electrode of the twentieth transistor is electrically connected with the reference voltage end, and the second electrode of the twentieth transistor is electrically connected with the second end of the eighth energy storage circuit.

In a second aspect, an embodiment of the present invention provides a driving method, which is applied to the above pixel circuit, and includes:

the driving circuit generates driving current for driving the light emitting element under the control of the potential of the control end of the driving circuit;

the first on-off control circuit controls the connection or disconnection between the second node and the third node under the control of the potential of the first control node;

The second on-off control circuit is used for controlling the connection or disconnection between the second pole and the first voltage end of the light-emitting element under the control of the potential of the second control node;

The first control circuit controls the data voltage according to the first time provided by the data line under the control of the first control signal, and controls the communication between the first light-emitting time control end or the second light-emitting time control end and the first control node;

the second control circuit controls the communication between the second light-emitting time control end or the third light-emitting time control end and the second control node according to the second time control data voltage provided by the data line under the control of the second control signal.

In a third aspect, an embodiment of the present invention provides a display device including the above pixel circuit.

Drawings

FIG. 1 is a block diagram of a pixel circuit according to at least one embodiment of the invention;

FIG. 2 is a block diagram of a pixel circuit according to at least one embodiment of the invention;

FIG. 3 is a block diagram of a pixel circuit according to at least one embodiment of the invention;

FIG. 4 is a block diagram of a pixel circuit according to at least one embodiment of the invention;

FIG. 5 is a block diagram of a pixel circuit according to at least one embodiment of the invention;

FIG. 6 is a block diagram of a pixel circuit according to at least one embodiment of the invention;

FIG. 7 is a circuit diagram of a pixel circuit according to at least one embodiment of the invention;

FIG. 8 is a timing diagram illustrating operation of at least one embodiment of the pixel circuit shown in FIG. 7 according to the present invention;

FIG. 9A is a schematic diagram illustrating an operation of at least one embodiment of the pixel circuit shown in FIG. 7 in a first stage according to the present invention;

FIG. 9B is a schematic diagram illustrating an operation state of at least one embodiment of the pixel circuit shown in FIG. 7 in a second stage according to the present invention;

FIG. 9C is a schematic diagram illustrating an operation of at least one embodiment of the pixel circuit shown in FIG. 7 in a third stage according to the present invention;

FIG. 9D is a schematic diagram illustrating a fourth stage of operation of at least one embodiment of the pixel circuit shown in FIG. 7 according to the present invention;

FIG. 9E is a schematic diagram illustrating a fifth stage of operation of at least one embodiment of the pixel circuit shown in FIG. 7 according to the present invention;

FIG. 10 is a timing diagram illustrating operation of at least one embodiment of the pixel circuit shown in FIG. 7 according to the present invention;

FIG. 11 is a timing diagram illustrating operation of at least one embodiment of the pixel circuit shown in FIG. 7 according to the present invention;

FIG. 12 is a timing diagram illustrating operation of at least one embodiment of the pixel circuit of FIG. 7 according to the present invention;

FIG. 13 is a circuit diagram of a pixel circuit according to at least one embodiment of the invention;

FIG. 14 is a timing diagram illustrating operation of at least one embodiment of the pixel circuit shown in FIG. 13 in accordance with the present invention; fig. 15 is a circuit diagram of a pixel circuit according to at least one embodiment of the invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The transistors used in all embodiments of the present invention may be thin film transistors or field effect transistors or other devices having the same characteristics. In the embodiment of the invention, in order to distinguish the two poles of the transistor except the grid electrode, one pole is called a first pole, and the other pole is called a second pole.

In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or the first pole may be a source and the second pole may be a drain.

The embodiment of the invention provides a novel Micro LED pixel driving circuit, which can realize a high-quality Micro LED display device without damage to gamma, and can realize high gray scale, low gray scale, medium gray scale and even super low gray scale through the pixel driving circuit and a matched time sequence.

The Gamma2.2 curve is a gray scale curve which is relatively suitable for human eyes, and usually, an OLED (organic light emitting diode) display panel or an LED display panel cannot fit the Gamma2.2 curve at a low gray scale or an ultra-low gray scale because of intrinsic defects of a TFT (thin film transistor) device or defects of a light emitting device. The lossless gamma is realized by matching several light emitting durations, and all points of 8 bits (bit, 8bit is 256 gray scale) or 10 bits (1024 gray scale) can be realized on the gamma2.2 curve.

In at least one embodiment of the present invention, when 256 gray scales are provided, L128 to L255 may be middle-high gray scales, L0 to L127 may be middle-low gray scales, L16 or less may be ultra-low gray scales, and low gray scales may be L17 to L127, wherein L128 is gray scale 128, L255 is gray scale 255, L0 is gray scale 0, L127 is gray scale 127, and L17 is gray scale 17;

but is not limited thereto.

The pixel circuit disclosed by the embodiment of the invention realizes different gray scales by the coordination of current regulation and light-emitting time regulation, and realizes medium-high gray scales, medium-low gray scales, low gray scales and ultra-low gray scales by different light-emitting currents and the duty ratios of light-emitting time control signals provided by all light-emitting time control ends.

As shown in fig. 1, a pixel circuit according to at least one embodiment of the present invention includes a driving circuit 10, a first on-off control circuit 11, a light emitting element EL, a second on-off control circuit 12, a first control circuit 13, and a second control circuit 14;

A first end of the driving circuit 10 is electrically connected with the first node N1, and a second end of the driving circuit 10 is electrically connected with the second node N2; the driving circuit 10 is used for generating a driving current for driving the light emitting element EL under the control of the potential of the control end;

the first on-off control circuit 11 is electrically connected with a first control node NC1, a second node N2 and a third node N3, and is configured to control connection or disconnection between the second node N2 and the third node N3 under the control of the potential of the first control node NC 1;

A first electrode of the light emitting element EL is electrically connected to the third node N3;

the second on-off control circuit 12 is electrically connected to the second control node NC2, the second pole of the light emitting element EL, and the first voltage terminal V1, and is configured to control the connection or disconnection between the second pole of the light emitting element EL and the first voltage terminal V1 under the control of the potential of the second control node NC 2;

The first control circuit 13 is electrically connected to the first control terminal R1, the data line DL, the first light-emitting time control terminal HF, the second light-emitting time control terminal EML, and the first control node NC1, and is configured to control, under control of a first control signal provided by the first control terminal R1, communication between the first light-emitting time control terminal HF or the second light-emitting time control terminal EML and the first control node NC1 according to a first time control data voltage provided by the data line DL;

The second control circuit 14 is electrically connected to the second control terminal SL, the data line DL, the second light-emitting time control terminal EML, the third light-emitting time control terminal EMS, and the second control node NC2, and is configured to control, under control of a second control signal provided by the second control terminal SL, the second light-emitting time control terminal EML or the third light-emitting time control terminal EMS to communicate with the second control node NC2 according to a second time control data voltage provided by the data line DL.

Optionally, the first voltage terminal may be a low voltage terminal, but is not limited thereto.

In operation, at least one embodiment of the pixel circuit shown in fig. 1 of the present invention may include a first stage, a second stage, and a third stage that are sequentially arranged;

In the first stage, under the control of the first control signal provided by the first control terminal R1, the first control circuit 13 controls the first emission time control terminal HF or the second emission time control terminal EML to communicate with the first control node NC1 according to the first time control data voltage provided by the data line DL;

When the ultra-low gray scale is displayed, the first control circuit 13 may control the communication between the first lighting time control terminal HF and the first control node NC 1;

When the middle-high gray scale and the middle-low gray scale are displayed, the first control circuit 13 may control the second emission time control terminal EML to communicate with the first control node NC 1;

when displaying low gray scale, the first control circuit 13 may control the communication between the first lighting time control terminal HF and the first control node NC 1;

The first light emitting time control end HF is used for providing a first light emitting time control signal, and the second light emitting time control end EML is used for providing a second light emitting time control signal;

The second stage is a compensation stage and data voltage writing time for controlling the luminous current;

In the third stage, the second control circuit 14 controls the second emission time control terminal EML or the third emission time control terminal EMS to communicate with the second control node NC2 according to a second time control data voltage provided by the data line DL under the control of a second control signal;

when the ultra-low gray scale is displayed, the second control circuit 14 controls the communication between the third light-emitting time control end EMS and the second control node NC 2;

when displaying the middle and high gray scales, the second control circuit 14 controls the second emission time control terminal EML to communicate with the second control node NC 2;

When displaying middle and low gray scales, the second control circuit 14 controls the communication between the third light emitting time control terminal EMS and the second control node NC2

When displaying low gray scale, the second control circuit 14 controls the communication between the third emission time control end EMS and the second control node NC 2;

The third emission time control terminal EMS is configured to provide a third emission time control signal.

In a specific implementation, when the transistor included in the first on-off control circuit 11 is a p-type transistor and the transistor included in the second on-off control circuit 12 is a p-type transistor, the duty ratio of the first light-emitting time control signal provided by the first light-emitting time control terminal HF is greater than the duty ratio of the third light-emitting time control signal provided by the third light-emitting time control terminal EMS, and the duty ratio of the third light-emitting time control signal is greater than the duty ratio of the second light-emitting time control signal provided by the second light-emitting time control terminal EML;

When the transistor included in the first on-off control circuit 11 is an n-type transistor and the transistor included in the second on-off control circuit 12 is an n-type transistor, the duty ratio of the first light-emitting time control signal provided by the first light-emitting time control terminal HF is smaller than the duty ratio of the third light-emitting time control signal provided by the third light-emitting time control terminal EMS, and the duty ratio of the third light-emitting time control signal is smaller than the duty ratio of the second light-emitting time control signal provided by the second light-emitting time control terminal EML;

but is not limited thereto.

In at least one embodiment of the present invention, the first control circuit includes a first write circuit, a first tank circuit, a first switch control circuit, and a second switch control circuit;

In a specific implementation, the first control circuit may include a first write circuit, a first energy storage circuit, a first switch control circuit and a second switch control circuit, where the first write circuit writes a first time control data voltage into a first switch node under the control of a first control signal, the first energy storage circuit maintains the potential of the first switch node, and the first switch control circuit controls the connection or disconnection between the first control node and the second light-emitting time control end under the control of the potential of the first switch node; the second switch control circuit controls the connection or disconnection between the first control node and the first light-emitting time control end under the control of the potential of the first switch node.

In at least one embodiment of the present invention, the second control circuit includes a second write circuit, a second tank circuit, a third switch control circuit, and a fourth switch control circuit;

In a specific implementation, the second control circuit may include a second write circuit, a second tank circuit, a third switch control circuit, and a fourth switch control circuit; the second write circuit writes a second time control data voltage into the second switch node under the control of a second control signal; the second energy storage circuit maintains the potential of the second switch node; the third switch control circuit controls the connection or disconnection between the second control node and the third light-emitting time control end under the control of the potential of the second switch node; the fourth switch control circuit controls the connection or disconnection between the second control node and the second light-emitting time control end under the control of the potential of the second switch node.

As shown in fig. 2, the first control circuit includes a first write circuit 21, a first tank circuit 22, a first switch control circuit 23, and a second switch control circuit 24, based on at least one embodiment of the pixel circuit shown in fig. 1;

The first write circuit 21 is electrically connected to the first control terminal R1, the data line DL, and the first switch node NK1, and is configured to write a first time control data voltage provided by the data line DL into the first switch node NK1 under the control of a first control signal provided by the first control terminal R1;

the first tank circuit 22 is electrically connected to the first switch node NK1, and is configured to maintain a potential of the first switch node NK 1;

The first switch control circuit 23 is electrically connected to the first switch node NK1, the second light-emitting time control terminal EML, and the first control node NC1, and is configured to control the connection or disconnection between the first control node NC1 and the second light-emitting time control terminal EML under the control of the potential of the first switch node NK 1;

The second switch control circuit 24 is electrically connected to the first switch node NK1, the first light-emitting time control terminal HF, and the first control node NC1, and is configured to control the connection or disconnection between the first control node NC1 and the first light-emitting time control terminal HF under the control of the potential of the first switch node NK 1;

the second control circuit comprises a second write circuit 25, a second energy storage circuit 26, a third switch control circuit 27 and a fourth switch control circuit 28;

The second write circuit 25 is electrically connected to the second control terminal SL, the data line DL, and the second switching node NK2, and is configured to write a second time control data voltage provided by the data line DL into the second switching node NK2 under control of a second control signal provided by the second control terminal SL;

the second tank circuit 26 is electrically connected to the second switch node NK2, and is configured to maintain the potential of the second switch node NK 2;

The third switch control circuit 27 is electrically connected to the second switch node NK2, the third light-emitting time control terminal EMS, and the second control node NC2, and is configured to control connection or disconnection between the second control node NC2 and the third light-emitting time control terminal EMS under the control of the potential of the second switch node NK 2;

the fourth switch control circuit 28 is electrically connected to the second switch node NK2, the second light-emitting time control terminal EML, and the second control node NC2, and is configured to control the connection or disconnection between the second control node NC2 and the second light-emitting time control terminal EML under the control of the potential of the second switch node NK 2.

In operation, at least one embodiment of the pixel circuit shown in fig. 2 of the present invention may include a first stage, a second stage, and a third stage sequentially arranged;

In the first stage, the first write circuit 21 writes the first time control data voltage provided by the data line DL into the first switch node NK1 under the control of the first control signal provided;

When the ultra-low gray scale is displayed, the second switch control circuit 24 controls the first control node NC1 to be communicated with the first light-emitting time control terminal HF under the control of the potential of the first switch node NK 1;

When displaying middle and high gray scales, the first switch control circuit 23 controls the first control node NC1 to communicate with the second emission time control terminal EML under the control of the potential of the first switch node NK 1;

when displaying middle and low gray scales, the first switch control circuit 23 controls the first control node NC1 to communicate with the second emission time control terminal EML under the control of the potential of the first switch node NK 1;

When displaying low gray scales, the second switch control circuit 24 controls the first control node NC1 to communicate with the first light-emitting time control terminal HF under the control of the potential of the first switch node NK 1;

in the third stage, the second write circuit 25 writes the second time control data voltage provided by the data line DL into the second switching node NK2 under the control of the second control signal provided by the second control terminal SL;

When the ultra-low gray scale is displayed, the third switch control circuit 27 controls the second control node NC2 to communicate with the third emission time control terminal EMS under the control of the potential of the second switch node NK 2;

When displaying the middle and high gray scales, the fourth switch control circuit 28 controls the second control node NC2 to communicate with the second emission time control terminal EML under the control of the potential of the second switch node NK2;

when displaying middle and low gray scales, the third switch control circuit 27 controls the second control node NC2 to communicate with the third emission time control terminal EMS under the control of the potential of the second switch node NK 2;

when displaying low gray scales, the third switch control circuit 27 controls the communication between the second control node NC2 and the third emission time control terminal EMS under the control of the potential of the second switch node NK 2.

In at least one embodiment of the present invention, the first control circuit includes a third write circuit, a fourth write circuit, a fifth switch control circuit, a sixth switch control circuit, a third tank circuit, and a fourth tank circuit; the first control end comprises a first reset control end and a second reset control end;

In a specific implementation, the first control circuit may include a third write circuit, a fourth write circuit, a fifth switch control circuit, a sixth switch control circuit, a third tank circuit, and a fourth tank circuit; the first control end comprises a first reset control end and a second reset control end; the third write circuit writes a third time control data voltage into the third switch node under the control of the first reset control signal; the third energy storage circuit maintains the potential of the third switch node; the fourth write circuit writes a fourth time control data voltage into the fourth switch node under the control of a second reset control signal; the fourth energy storage circuit maintains the potential of the fourth switch node; the fifth switch control circuit controls the connection or disconnection between the second light-emitting time control end and the first control node under the control of the potential of the third switch node; the sixth switch control circuit controls the connection or disconnection between the first light-emitting time control end and the first control node under the control of the potential of the fourth switch node.

In at least one embodiment of the present invention, the second control circuit includes a fifth write circuit, a sixth write circuit, a seventh switch control circuit, an eighth switch control circuit, a fifth tank circuit, and a sixth tank circuit; the second control end comprises a third reset control end and a fourth reset control end;

In a specific implementation, the second control circuit may include a fifth write circuit, a sixth write circuit, a seventh switch control circuit, an eighth switch control circuit, a fifth tank circuit, and a sixth tank circuit; the second control end comprises a third reset control end and a fourth reset control end; the fifth writing circuit writes a fifth time control data voltage into the fifth switch node under the control of a third reset control signal; the fifth energy storage circuit maintains the potential of the fifth switch node; the sixth write circuit writes a sixth time control data voltage into the sixth switch node under the control of a fourth reset control signal; the sixth tank circuit maintains the potential of the sixth switch node; the seventh switch control circuit controls the connection or disconnection between the second light-emitting time control end and the second control node under the control of the potential of the fifth switch node; the eighth switch control circuit controls the connection or disconnection between the third light-emitting time control end and the second control node under the control of the potential of the sixth switch node.

As shown in fig. 3, in at least one embodiment of the pixel circuit shown in fig. 1, the first control circuit includes a third write circuit 31, a fourth write circuit 32, a fifth switch control circuit 33, a sixth switch control circuit 34, a third tank circuit 35, and a fourth tank circuit 36; the first control end comprises a first reset control end RA and a second reset control end RB;

The third write circuit 31 is electrically connected to the first reset control terminal RA, the data line DL, and the third switch node NK3, and is configured to write a third time control data voltage provided by the data line DL into the third switch node NK3 under the control of a first reset control signal provided by the first reset control terminal RA;

the third tank circuit 35 is electrically connected to the third switch node NK3, and is configured to maintain the potential of the third switch node NK 3;

The fourth write circuit 32 is electrically connected to the second reset control terminal RB, the data line DL, and the fourth switching point NK4, and is configured to write a fourth time control data voltage provided by the data line DL into the fourth switching point NK4 under the control of a second reset control signal provided by the second reset control terminal RB;

the fourth tank circuit 36 is electrically connected to the fourth switching point NK4, and is configured to maintain the potential of the fourth switching point NK 4;

The fifth switch control circuit 33 is electrically connected to the third switch node NK3, the second light-emitting time control terminal EML, and the first control node NC1, and is configured to control the connection or disconnection between the second light-emitting time control terminal EML and the first control node NC1 under the control of the potential of the third switch node NK 3;

The sixth switch control circuit 34 is electrically connected to the fourth switch node NK4, the first light-emitting time control terminal HF, and the first control node NC1, and is configured to control the connection or disconnection between the first light-emitting time control terminal HF and the first control node NC1 under the control of the potential of the fourth switch node NK 4;

The second control circuit includes a fifth write circuit 37, a sixth write circuit 38, a seventh switch control circuit 39, an eighth switch control circuit 310, a fifth tank circuit 311, and a sixth tank circuit 312; the second control end comprises a third reset control end RC and a fourth reset control end RD;

the fifth write circuit 37 is electrically connected to the third reset control terminal RC, the data line DL, and the fifth switching node NK5, and is configured to write a fifth time control data voltage provided by the data line DL into the fifth switching node NK5 under control of a third reset control signal provided by the third reset control terminal RC;

The fifth tank circuit 311 is electrically connected to the fifth switch node NK5, and is configured to maintain a potential of the fifth switch node NK 5;

The sixth write circuit 38 is electrically connected to the fourth reset control terminal RD, the data line DL, and the sixth open joint point NK6, and is configured to write a sixth time control data voltage provided by the data line DL into the sixth open joint point NK6 under control of a fourth reset control signal provided by the fourth reset control terminal RD;

The sixth tank circuit 312 is electrically connected to the sixth open joint point NK6, and is configured to maintain the potential of the sixth open joint point NK 6;

the seventh switch control circuit 39 is electrically connected to the fifth switch node NK5, the second light-emitting time control terminal EML, and the second control node NC2, and is configured to control the connection or disconnection between the second light-emitting time control terminal EML and the second control node NC2 under the control of the potential of the fifth switch node NK5;

The eighth switch control circuit 310 is electrically connected to the sixth switch node NK6, the third light-emitting time control terminal EMS, and the second control node NC2, and is configured to control the NC2 between the third light-emitting time control terminal EMS and the second control node to be connected or disconnected under the control of the potential of the sixth switch node NK 6.

In operation, at least one embodiment of the pixel circuit shown in fig. 3 of the present invention may include a first stage, a second stage, and a third stage that are sequentially arranged;

In the first stage, the third write circuit 31 writes the third time control data voltage provided by the data line DL into the third switch node NK3 under the control of the first reset control signal provided by the first reset control terminal RA; the third tank circuit 35 maintains the potential of the third switching node NK3; the fourth write circuit 32 writes the fourth time control data voltage provided by the data line DL into the fourth switching point NK4 under the control of the second reset control signal provided by the second reset control terminal RB; the fourth tank circuit 36 maintains the potential of the fourth switch node NK4;

when the ultra-low gray scale and the low gray scale are displayed, the sixth switch control circuit 34 controls the first light-emitting time control terminal HF to be communicated with the first control node NC1 under the control of the potential of the fourth switch node NK 4;

when the middle-high gray scale and the middle-low gray scale are displayed, the fifth switch control circuit 33 controls the second light-emitting time control terminal EML to be communicated with the first control node NC1 under the control of the potential of the third switch node NK 3;

In the third stage, the fifth write circuit 37 writes the fifth time control data voltage provided by the data line DL into the fifth switching node NK5 under the control of the third reset control signal provided by the third reset control terminal RC; the fifth tank circuit 311 maintains the potential of the fifth switch node NK5; the sixth write circuit 38 writes the sixth time control data voltage provided by the data line DL into the sixth open joint NK6 under the control of the fourth reset control signal provided by the fourth reset control terminal RD; the sixth tank circuit 312 maintains the potential of the sixth switching node NK6;

When the ultra-low gray scale, the medium-low gray scale and the low gray scale are displayed, the eighth switch control circuit 310 controls NC2 between the third emission time control terminal EMS and the second control node to be connected or disconnected under the control of the potential of the sixth switch node NK 6;

When the middle-high gray scale is displayed, the seventh switch control circuit 39 controls the second emission time control terminal EML to communicate with the second control node NC2 under the control of the potential of the fifth switch node NK 5.

The pixel circuit according to at least one embodiment of the present invention further includes a data writing circuit, a compensation control circuit, and a seventh tank circuit;

In a specific implementation, the pixel circuit may further include a data writing circuit, a compensation control circuit, and a seventh energy storage circuit, where the data writing circuit writes the current control data voltage provided by the data line into the first node under the control of the scan signal; and the compensation control circuit controls the connection or disconnection between the control end of the driving circuit and the second node under the control of the scanning signal.

The pixel circuit according to at least one embodiment of the present invention further includes a first initialization circuit and a second initialization circuit;

In a specific implementation, the pixel circuit may further include a first initialization circuit and a second initialization circuit; the first initializing circuit writes the initial voltage provided by the initial voltage end into the control end of the driving circuit under the control of a first control signal so as to initialize the potential of the control end of the driving circuit; the second initializing circuit writes the initial voltage to the first electrode of the light emitting element under the control of the first control signal to initialize the potential of the first electrode of the light emitting element.

The pixel circuit according to at least one embodiment of the present invention further includes a light emission control circuit;

The light-emitting control circuit is respectively and electrically connected with the second light-emitting time control end, the power voltage end and the first node and is used for controlling the connection or disconnection between the power voltage end and the first node under the control of a second light-emitting time control signal provided by the second light-emitting time control end.

In a specific implementation, the pixel circuit may further include a light emission control circuit, where the light emission control circuit is configured to control, under control of a second light emission time control signal provided by the second light emission time control terminal, connection or disconnection between the power supply voltage terminal and the first node, so as to perform light emission control.

As shown in fig. 4, on the basis of at least one embodiment of the pixel circuit shown in fig. 2, the pixel circuit according to at least one embodiment of the present invention may further include a data writing circuit 41, a compensation control circuit 42, and a seventh tank circuit 43;

The data writing circuit 41 is electrically connected to the scan line GL, the data line DL and the first node N1, respectively, and is configured to write the current control data voltage provided by the data line DL into the first node N1 under the control of the scan signal provided by the scan line GL;

The compensation control circuit 42 is electrically connected to the scan line GL, the control end of the driving circuit 10, and the second node N2, respectively, and is configured to control the connection or disconnection between the control end of the driving circuit 10 and the second node N2 under the control of the scan signal;

The seventh energy storage circuit 43 is electrically connected to the control terminal of the driving circuit 10, and is configured to store electric energy;

The pixel circuit according to at least one embodiment of the present invention further includes a first initialization circuit 44 and a second initialization circuit 45;

The first initializing circuit 44 is electrically connected to the first control terminal R1, the initial voltage terminal I1, and the control terminal of the driving circuit 10, and is configured to write an initial voltage Vinit provided by the initial voltage terminal I1 into the control terminal of the driving circuit 10 under the control of a first control signal provided by the first control terminal R1;

the second initializing circuit 45 is electrically connected to the first control terminal R1, the initial voltage terminal I1, and the first electrode of the light emitting element EL, and is configured to write the initial voltage Vinit into the first electrode of the light emitting element EL under the control of the first control signal;

The pixel circuit according to at least one embodiment of the present invention may further include a light emission control circuit 46;

The light emission control circuit 46 is electrically connected to the second light emission time control terminal EML, the power supply voltage terminal ELVDD, and the first node N1, and is configured to control the connection or disconnection between the power supply voltage terminal ELVDD and the first node N1 under the control of a second light emission time control signal provided by the second light emission time control terminal EML.

In operation, at least one embodiment of the pixel circuit shown in fig. 4 of the present invention may include a first phase and a second phase arranged in succession;

In a first phase, the first initializing circuit 44 writes the initial voltage Vinit provided by the initial voltage terminal I1 into the control terminal of the driving circuit 10 under the control of the first control signal provided by the first control terminal R1, so that the driving circuit 10 can conduct the connection between the first terminal and the second terminal thereof at the beginning of the second phase; the second initializing circuit 45 writes the initial voltage Vinit to the first electrode of the light emitting element EL under the control of the first control signal to control the light emitting element EL not to emit light and to clear the first electrode of the light emitting element EL of residual electric charges;

In the second stage, the data writing circuit 41 writes the current control data voltage Vdata supplied from the data line DL into the first node N1 under the control of the scan signal supplied from the scan line GL; the compensation control circuit 42 controls the communication between the control end of the driving circuit 10 and the second node N2 under the control of the scanning signal;

At the beginning of the second phase, the driving circuit 10 turns on the connection between the first node N1 and the second node N2 to charge the seventh tank circuit 43 by the current control data voltage Vdata, so as to raise the potential of the control terminal of the driving circuit 10 until the potential of the control terminal of the driving circuit 10 becomes vdata+vth, where Vth is the threshold voltage of the driving transistor included in the driving circuit 10, and the driving circuit 10 turns off the connection between the first node N1 and the second node N2, and stops charging to perform threshold voltage compensation.

In at least one embodiment of the present invention, the first control terminal includes a first reset control terminal and a second reset control terminal;

As shown in fig. 5, on the basis of at least one embodiment of the pixel circuit shown in fig. 3, the pixel circuit according to at least one embodiment of the present invention may further include a data writing circuit 41, a compensation control circuit 42, and a seventh tank circuit 43;

The first initializing circuit 44 is electrically connected to the first reset control terminal RA, the initial voltage terminal I1, and the control terminal of the driving circuit 10, and is configured to write the initial voltage Vinit provided by the initial voltage terminal I1 into the control terminal of the driving circuit 10 under the control of the first reset control signal provided by the first reset control terminal RA;

The second initializing circuit 45 is electrically connected to the first reset control terminal RA, the initial voltage terminal I1, and the first electrode of the light emitting element EL, and is configured to write the initial voltage Vinit into the first electrode of the light emitting element EL under the control of the first reset control signal;

In operation, at least one embodiment of the pixel circuit shown in fig. 5 of the present invention may include a first phase and a second phase arranged in succession;

In a first phase, the first initializing circuit 44 writes the initial voltage Vinit provided by the initial voltage terminal I1 into the control terminal of the driving circuit 10 under the control of the first reset control signal, so that the driving circuit 10 can conduct the connection between the first terminal and the second terminal thereof at the beginning of the second phase; the second initializing circuit 45 writes the initial voltage Vinit to the first electrode of the light emitting element EL under the control of the first reset control signal to control the light emitting element EL not to emit light and to clear the first electrode of the light emitting element EL of residual electric charges;

The pixel circuit according to at least one embodiment of the present invention further includes a compensation control circuit, a data writing circuit, and an eighth tank circuit; the first node is electrically connected with a power supply voltage end;

The pixel circuit according to at least one embodiment of the present invention further includes a reference voltage writing circuit;

The reference voltage writing circuit is electrically connected with the first control end, the second light-emitting time control end, the reference voltage end and the second end of the eighth energy storage circuit respectively, and is used for pressing the reference voltage provided by the reference voltage end into the second end of the eighth energy storage circuit under the control of the first control signal provided by the first control end and writing the reference voltage into the second end of the eighth energy storage circuit under the control of the second light-emitting time control signal provided by the second light-emitting time control end.

As shown in fig. 6, based on at least one embodiment of the pixel circuit shown in fig. 2,

The pixel circuit according to at least one embodiment of the present invention further includes a compensation control circuit 42, a data writing circuit 41, and an eighth tank circuit 40; the first node N1 is electrically connected to the power voltage terminal ELVDD;

a first end of the eighth tank circuit 40 is electrically connected to the control end of the driving circuit 10; the eighth tank circuit 40 is configured to store electrical energy;

The compensation control circuit 42 is electrically connected to the scan line GL, the control end of the driving circuit 10, and the second node, and is configured to control the connection or disconnection between the control end of the driving circuit 10 and the second node N2 under the control of the scan signal provided by the scan line GL;

The data writing circuit 41 is electrically connected to the second ends of the scan line GL, the data line DL and the eighth tank circuit 40, respectively, and is configured to write the current control data voltage Vdata provided by the data line DL into the second end of the eighth tank circuit 40 under the control of the scan signal;

The pixel circuit according to at least one embodiment of the present invention further includes a first initialization circuit 44;

The pixel circuit according to at least one embodiment of the present invention further includes a reference voltage writing circuit 47;

The reference voltage writing circuit 47 is electrically connected to the first control terminal R1, the second emission time control terminal EML, the reference voltage terminal VR and the second terminal of the eighth tank circuit 40, respectively, and is configured to write the reference voltage Vref provided by the reference voltage terminal VR into the second terminal of the eighth tank circuit 40 under the control of the first control signal provided by the first control terminal R1, and write the reference voltage Vref into the second terminal of the eighth tank circuit 40 under the control of the second emission time control signal provided by the second emission time control terminal EML.

In operation, at least one embodiment of the pixel circuit shown in fig. 6 of the present invention may include a first phase and a second phase arranged in succession;

In a first phase, the first initializing circuit 44 writes the initial voltage Vinit provided by the initial voltage terminal I1 into the control terminal of the driving circuit 10 under the control of the first control signal provided by the first control terminal R1, so that the driving circuit 10 can conduct the connection between the power voltage terminal ELVDD and the second node N2 at the beginning of the second phase; the reference voltage writing circuit 47 writes the reference voltage Vref provided by the reference voltage terminal VR into the second terminal of the eighth tank circuit 40 under the control of the first control signal, so as to initialize the potential of the second terminal of the eighth tank circuit 40, so that the potential of the second terminal of the eighth tank circuit 40 is Vref;

in the second stage, the data writing circuit 41 is electrically connected to the second ends of the scan line GL, the data line DL and the eighth tank circuit 40, respectively, and is configured to write the current control data voltage Vdata provided by the data line DL into the second end of the eighth tank circuit 40 under the control of the scan signal; the compensation control circuit 42 controls the connection between the control terminal of the driving circuit 10 and the second node N2 under the control of the scan signal, so as to charge the eighth tank circuit 40, until the driving circuit 10 disconnects the power voltage terminal ELVDD and the second node N2 under the control of the potential of the control terminal thereof, so as to perform threshold voltage compensation.

In at least one embodiment of the present invention, the light emitting device may be a micro light emitting diode, but is not limited thereto. In actual operation, the light emitting element may be a mini light emitting diode, an organic light emitting diode, or other types of light emitting elements.

As shown in fig. 7, in at least one embodiment of the pixel circuit shown in fig. 4, the light emitting element is a micro light emitting diode ML;

The first write circuit comprises a first transistor T1, the first energy storage circuit comprises a first capacitor C1, the first switch control circuit comprises a second transistor T2, and the second switch control circuit comprises a third transistor T3;

The gate of the first transistor T1 is electrically connected to the first control terminal R1, the source of the first transistor T1 is electrically connected to the data line DL, and the drain of the first transistor T1 is electrically connected to the first switch node NK 1;

A first end of the first capacitor C1 is electrically connected to the first switch node NK1, and a second end of the first capacitor is electrically connected to the initial voltage end I1; the initial voltage terminal I1 is used for providing an initial voltage Vinit;

The gate of the second transistor T2 is electrically connected to the first switch node NK1, the source of the second transistor T2 is electrically connected to the second emission time control terminal EML, and the drain of the second transistor T2 is electrically connected to the first control node NC 1;

a gate of the third transistor T3 is electrically connected to the first switch node NK1, a source of the third transistor T3 is electrically connected to the first light-emitting time control terminal HF, and a drain of the third transistor T3 is electrically connected to the first control node NC 1;

t1 and T2 are p-type transistors, and T3 is an n-type transistor;

The second write circuit comprises a fourth transistor T4, the second energy storage circuit comprises a second capacitor C2, the third switch control circuit comprises a fifth transistor T5, and the fourth switch control circuit comprises a sixth transistor T6;

the gate of the fourth transistor T4 is electrically connected to the second control terminal SL, the source of the fourth transistor T4 is electrically connected to the data line DL, and the drain of the fourth transistor T4 is electrically connected to the second switching node NK 2;

The first end of the second capacitor C2 is electrically connected to the second switch node NK2, and the second end of the second capacitor C2 is electrically connected to the initial voltage end I1;

The gate of the fifth transistor T5 is electrically connected to the second switch node NK2, the source of the fifth transistor T5 is electrically connected to the third emission time control terminal EMS, and the drain of the fifth transistor T5 is electrically connected to the second control node NC 2;

The gate of the sixth transistor T6 is electrically connected to the second switching node NK2, the source of the sixth transistor T6 is electrically connected to the second emission time control terminal EML, and the drain of the sixth transistor T6 is electrically connected to the second control node NC 2;

t4 and T5 are p-type transistors, and T6 is an n-type transistor;

the driving circuit includes a driving transistor T0;

the grid electrode of the driving transistor T0 is connected with a driving control node N0, the source electrode of the driving transistor T0 is electrically connected with the first node N1, and the drain electrode of the driving transistor T0 is electrically connected with the second node N2;

The first on-off control circuit comprises a first control transistor TC1, and the second on-off control circuit comprises a second control transistor TC2;

The gate of the first control transistor TC1 is electrically connected to the first control node NC1, the source of the first control transistor TC1 is electrically connected to the second node N2, and the drain of the first control transistor TC1 is electrically connected to the third node N3; the third node N3 is electrically connected with the anode of the micro light emitting diode ML;

the gate of the second control transistor TC2 is electrically connected to the second control node NC2, the source of the second control transistor TC2 is electrically connected to the cathode of the micro light emitting diode ML, and the drain of the second control transistor TC2 is electrically connected to the low voltage terminal ELVSS;

T0 is a p-type transistor, and TC1 and TC2 are p-type transistors;

The data writing circuit includes a fifteenth transistor T15, the compensation control circuit includes a sixteenth transistor T16, and the seventh tank circuit includes a first storage capacitor Cs1;

A gate of the fifteenth transistor T15 is electrically connected to the scanning line GL, a source of the fifteenth transistor T15 is electrically connected to the data line DL, and a drain of the fifteenth transistor T15 is electrically connected to the first node N1;

A gate of the sixteenth transistor T16 is electrically connected to the scanning line GL, a source of the sixteenth transistor T16 is electrically connected to the driving control node N0, and a drain of the sixteenth transistor T16 is electrically connected to the second node N2;

t15 and T16 are p-type transistors;

a first end of the first storage capacitor Cs1 is electrically connected to the control end of the driving circuit 10, and a second end of the first storage capacitor Cs1 is electrically connected to the power voltage end ELVDD;

the first initialization circuit includes a seventeenth transistor T17, and the second initialization circuit includes an eighteenth transistor T18;

A gate of the seventeenth transistor T17 is electrically connected to the first control terminal R1, a source of the seventeenth transistor T17 is electrically connected to the initial voltage terminal I1, and a drain of the seventeenth transistor T17 is electrically connected to the driving control node N0;

The gate of the eighteenth transistor T18 is electrically connected to the first control terminal R1, the source of the eighteenth transistor T18 is electrically connected to the initial voltage terminal I1, and the drain of the eighteenth transistor T18 is electrically connected to the anode of the micro light emitting diode ML;

the light emission control circuit includes a nineteenth transistor T19;

A gate of the nineteenth transistor T19 is electrically connected to the second emission time control terminal EML, a source of the nineteenth transistor T19 is electrically connected to the power supply voltage terminal ELVDD, and a drain of the nineteenth transistor T19 is electrically connected to the first node N1;

t17, T18, and T19 are p-type transistors.

As shown in fig. 8, in operation, at least one embodiment of the pixel circuit shown in fig. 7 of the present invention includes a first stage t1, a second stage t2, a third stage t3, a fourth stage t4 and a fifth stage t5, which are sequentially arranged when displaying ultra-low gray scale;

In the first stage T1, EML provides a high voltage signal, R1 provides a low voltage signal, GL provides a high voltage signal, SL provides a high voltage signal, DL provides a high voltage signal, EMS provides a high voltage signal, HF provides a high voltage signal, as shown in fig. 9A, T1 is turned on, C1 maintains the potential of NK1 at a high voltage, T3 is turned on to control communication between NC1 and HF, and TC1 is turned off; t17 is turned on to write the initial voltage Vinit to the driving control node N0 so that T0 can be turned on when the second phase T2 starts; t18 is conducted to write Vinit into the anode of the ML to initialize the anode potential of the ML and remove the residual charge of the anode of the ML;

As shown in fig. 9A, in the first stage T1, T19 is turned off, T16 is turned off, T15 is turned off, and T4 is turned off;

In the second phase t2, EML provides a high voltage signal, R1 provides a high voltage signal, GL provides a low voltage signal, SL provides a high voltage signal, DL provides a current control data voltage Vdata, EMS provides a high voltage signal, and HF provides a high voltage signal; as shown in fig. 9B, C1 maintains the potential of NK1 at a high voltage, T3 is turned on to control communication between NC1 and HF, and TC1 is turned off; t15 is turned on to write Vdata to the first node N1, T16 is turned on;

At the beginning of the second phase T2, T0 is turned on to charge Cs1 by Vdata until T0 is turned off, the potential of N0 becomes vdata+vth, vth is the threshold voltage of T0;

as shown in fig. 9B, in the second phase T2, T19 is off, T17 is off, T18 is off, T1 is off, T4 is off;

In a third phase t3, EML provides a high voltage signal, R1 provides a high voltage signal, GL provides a high voltage signal, SL provides a low voltage signal, DL provides a low voltage signal, EMS provides a high voltage signal, and HF provides a high voltage signal; as shown in fig. 9C, T4 is turned on, C2 maintains the potential of NK2 at a low voltage, T5 is turned on, and communication between NK2 and EMS is controlled so that the potential of NK2 is at a high voltage, TC2 is turned off;

As shown in fig. 9C, in the third phase T3, T19 off, T15 off, T17 off, T16 off, T18 off, TC1 off, T2 off, T6 off;

In the fourth stage T4, EML provides a low voltage signal, R1 provides a high voltage signal, GL provides a high voltage signal, SL provides a high voltage signal, DL provides a low voltage signal, EMS provides a high voltage signal, T19 is turned on, C1 maintains the potential of NK1 at a high voltage, T3 is turned on to control communication between HF and NC1, and TC1 is turned on when HF provides a low voltage signal, as shown in fig. 9D; the potential of NK2 is maintained to be low voltage by C2, T5 is opened, NC2 is communicated with EMS, TC2 is turned off, and O1 does not emit light;

as shown in fig. 9D, T15 is turned off, T17 is turned off, T18 is turned off, T16 is turned off, T1 is turned off, T2 is turned off, T4 is turned off, and T6 is turned off;

in the fifth stage T5, R1 provides a high voltage signal, GL provides a high voltage signal, SL provides a high voltage signal, T3 is turned on as shown in fig. 9E, HF is turned on with NC1, T5 is turned on, EMS is turned on with NC2, and when EML, HF and EMS all provide low voltage signals, T0 drives O1 to emit light as shown in fig. 9E;

As shown in fig. 9E, T2 is turned off, T1 is turned off, T4 is turned off, T6 is turned off, T16 is turned off, T17 is turned off, and T17 is turned off.

The first phase t1 may be an initialization phase and a first data writing phase, the second phase t2 may be a second data writing phase and a compensation phase, the third phase t3 may be a third data writing time, and the long-time light emission and the short-time light emission selection time, the fourth phase t4 may be a selection light emission phase, and the fifth phase t5 may be a light emission phase.

In fig. 8, the driving current generated by the driving transistor T0 is denoted by Id.

In operation, in at least one embodiment of the pixel circuit shown in fig. 7, vdata written in DL determines a light emitting current in the second stage t2, the range of Vdata may be greater than or equal to 12V and less than or equal to 18V, in the first stage t1 and the third stage t3, the voltage value of the voltage signal written in DL controls the corresponding transistor to be turned on or off, when the voltage signal written in DL controls the n-type transistor to be turned on, the voltage value of the voltage signal may be greater than or equal to 14V and less than or equal to 18V, and when the voltage signal written in DL controls the p-type transistor to be turned on, the voltage value of the voltage signal may be greater than or equal to-2V and less than or equal to 0V.

In at least one embodiment of the present invention, the voltage value of the low voltage signal provided by ELVSS may be 2V, and the voltage value of the power voltage signal provided by elvdd may be 16V, but not limited thereto.

In operation, at least one embodiment of the pixel circuit of fig. 7 of the present invention, in a second phase t2,

When displaying middle and high gray scales, the voltage value of Vdata provided by DL can be more than or equal to 12V and less than or equal to 15V;

When displaying middle and low gray scales, the voltage value of Vdata provided by DL can be larger than or equal to 15V and smaller than or equal to 18V;

but is not limited thereto.

FIG. 10 is a timing diagram illustrating operation of at least one embodiment of the pixel circuit of FIG. 7 in displaying high gray scale. FIG. 11 is a timing diagram illustrating operation of at least one embodiment of the pixel circuit of FIG. 7 in displaying low and medium gray levels.

FIG. 12 is a timing diagram illustrating operation of at least one embodiment of the pixel circuit of FIG. 7 in displaying low gray levels.

As shown in fig. 10, at least one embodiment of the pixel circuit of fig. 7 of the present invention is configured to display high gray levels,

In the first stage T1, DL provides a low voltage signal, T2 is conducted, and EML is communicated with NC 1;

in the third stage T3, DL provides a high voltage signal, T6 is turned on, and EML communicates with NC 2.

As shown in fig. 11, at least one embodiment of the pixel circuit of fig. 7 of the present invention is configured to display a medium and low gray levels,

in the third stage T3, DL provides a low voltage signal, T5 is turned on, and EMS is connected to NC 2.

As shown in fig. 12, at least one embodiment of the pixel circuit of fig. 7 of the present invention is configured to display a low gray level,

In the first stage T1, DL provides a high voltage signal, T3 is conducted, and HF is communicated with NC 1;

As shown in fig. 13, in at least one embodiment of the pixel circuit shown in fig. 5, the light emitting element is a micro light emitting diode ML;

the third write circuit comprises a seventh transistor T7, the fourth write circuit comprises an eighth transistor T8, the third energy storage circuit comprises a third capacitor C3, the fourth energy storage circuit comprises a fourth capacitor C4, the fifth switch control circuit comprises a ninth transistor T9, and the sixth switch control circuit comprises a tenth transistor T10;

A gate of the seventh transistor T7 is electrically connected to the first reset control terminal RA, a source of the seventh transistor T7 is electrically connected to the data line DL, and a drain of the seventh transistor T7 is electrically connected to the third switch node NK 3;

the first end of the third capacitor C3 is electrically connected to the third switching node NK3, and the second end of the third capacitor C3 is electrically connected to the initial voltage end I1; the initial voltage terminal I1 is used for providing an initial voltage Vinit;

The gate of the eighth transistor T8 is electrically connected to the second reset control terminal RB, the source of the eighth transistor T8 is electrically connected to the data line DL, and the drain of the eighth transistor T8 is electrically connected to the fourth switching point NK 4;

The first end of the fourth capacitor C4 is electrically connected to the fourth switching point NK4, and the second end of the fourth capacitor C4 is electrically connected to the initial voltage terminal I1;

a gate of the ninth transistor T9 is electrically connected to the third switching node NK3, a source of the ninth transistor T9 is electrically connected to the second emission time control terminal EML, and a drain of the ninth transistor T9 is electrically connected to the first control node NC 1;

The gate of the tenth transistor T10 is electrically connected to the fourth switching point NK4, the source of the tenth transistor T10 is electrically connected to the first light-emitting time control terminal HF, and the drain of the tenth transistor T10 is electrically connected to the first control node NC 1;

The fifth write circuit includes an eleventh transistor T11, the sixth write circuit includes a twelfth transistor T12, the seventh switch control circuit includes a thirteenth transistor T13, the eighth switch control circuit includes a fourteenth transistor T14, the fifth tank circuit includes a fifth capacitor C5, and the sixth tank circuit includes a sixth capacitor C6;

A gate of the eleventh transistor T11 is electrically connected to the third reset control terminal RC, a source of the eleventh transistor T11 is electrically connected to the data line DL, and a drain of the eleventh transistor T11 is electrically connected to the fifth switching node NK 5;

a first end of the fifth capacitor C5 is electrically connected to the fifth switch node NK5, and a second end of the fifth capacitor C5 is electrically connected to the initial voltage terminal I1;

The gate of the twelfth transistor T12 is electrically connected to the fourth reset control terminal RD, the source of the twelfth transistor T12 is electrically connected to the data line DL, and the drain of the twelfth transistor T12 is electrically connected to the sixth switching point NK 6;

the first end of the sixth capacitor C6 is electrically connected to the sixth switching point NK6, and the second end of the sixth capacitor C6 is electrically connected to the initial voltage terminal I1;

A gate of the thirteenth transistor T13 is electrically connected to the fifth switching node NK5, a source of the thirteenth transistor T13 is electrically connected to the second emission time control terminal EML, and a drain of the thirteenth transistor T13 is electrically connected to the second control node NC 2;

the gate of the fourteenth transistor T14 is electrically connected to the sixth switching point NK6, the source of the fourteenth transistor T14 is electrically connected to the third emission time control terminal EMS, and the drain of the fourteenth transistor T14 is electrically connected to the second control node NC 2;

the driving circuit includes a driving transistor T0;

A first end of the first storage capacitor Cs1 is electrically connected to the driving control node N0, and a second end of the first storage capacitor Cs1 is electrically connected to the power voltage end ELVDD;

A gate of the seventeenth transistor T17 is electrically connected to the first reset control terminal RA, a source of the seventeenth transistor T17 is electrically connected to the initial voltage terminal I1, and a drain of the seventeenth transistor T17 is electrically connected to the driving control node N0; the initial voltage terminal I1 is used for providing an initial voltage Vinit;

The gate of the eighteenth transistor T18 is electrically connected to the first reset control terminal RA, the source of the eighteenth transistor T18 is electrically connected to the initial voltage terminal I1, and the drain of the eighteenth transistor T18 is electrically connected to the anode of the micro light emitting diode ML;

the light emission control circuit includes a nineteenth transistor T19;

The gate of the nineteenth transistor T19 is electrically connected to the second emission time control terminal EML, the source of the nineteenth transistor T19 is electrically connected to the power supply voltage terminal ELVDD, and the drain of the nineteenth transistor T19 is electrically connected to the first node N1.

In at least one embodiment of the pixel circuit shown in fig. 13, all the transistors are p-type transistors, but not limited thereto.

As shown in fig. 14, in operation, in at least one embodiment of the pixel circuit shown in fig. 13, when displaying an ultra-low gray level, the display period includes a first stage t1, a second stage t2, a third stage t3, a fourth stage t4, a fifth stage t5, and a sixth stage t6 sequentially arranged;

in a first phase T1, RA provides a low voltage signal, T17 and T18 open, I1 provides an initial voltage Vinit to the drive control node N0 and the third node N3; DL provides a high voltage signal, T7 is conducted, NK3 has high voltage, and T9 is turned off; RB, RC and RD provide high voltage signals, EML provides high voltage signals, T19 is turned off, GL provides high voltage signals, and ML does not emit light;

In the second stage T2, the EML provides a high voltage signal, T19 remains off, the EMS provides a high voltage signal, HF provides a high voltage signal, RA provides a high voltage signal, T17 and T18 are off, GL provides a low voltage signal, T15 and T16 are on, and DL provides a current control data voltage Vdata, N0 and N2;

At the beginning of the second stage T2, T0 is turned on to charge Cs1 by Vdata until T0 is turned off, and the potential of N0 is vdata+vth; vth is a threshold voltage of T0;

In a third stage T3, the EML provides a high voltage signal, T19 remains off, RA, RC and RD all provide high voltage signals, T7, T11 and T12 are off, RB provides a low voltage signal, T8 is on, DL provides a low voltage signal, NK4 has a low voltage, T10 is on, NC1 is in communication with HF, HF provides a high voltage signal, and NC1 has a high voltage;

In the fourth stage T4, the EML provides a high voltage signal, T19 remains off, RA, RB and RD all provide high voltage signals, T7, T8 and T12 are off, RC provides a low voltage signal, T11 is on, DL provides a high voltage signal, NK5 has a high voltage signal, and T13 is off;

in the fifth stage T5, the EML provides a high voltage signal, T9 remains off, RA, RB and RC all provide high voltage signals, T7, T8 and T11 all turn off, RD provides a low voltage signal, T12 turns on, DL provides a low voltage signal, NK6 has a low voltage signal, T14 turns on, NC2 communicates with EMS, and NC2 has a high voltage.

In the sixth stage T6, RA, RB, RC and RD all supply high voltage signals, GL supplies high voltage signals, EML supplies low voltage signals, T19 is turned on, C3 and C5 maintain the potential of NK3 and the potential of NK5 at high voltages, C4 and C6 maintain the potential of NK4 and the potential of NK6 at low voltages, T10 and T14 are turned on, when HF and EMS simultaneously supply low voltage signals, the potential of NC1 and the potential of NC2 are low voltages, TC1 and TC2 are turned on, and T0 drives O1 to emit light.

At least one embodiment of the pixel circuit of figure 13 of the present invention displays medium and low gray levels,

In the first stage, RA provides a low voltage signal, RB provides a high voltage signal, RC and RD provide high voltage signals, DL provides a low voltage signal, T7 and T9 are conductive, and EML is communicated with NC 1;

In the third stage, RC provides a high voltage signal, RD provides a low voltage signal, RA and RB both provide high voltage signals, DL provides a low voltage signal, T12 and T14 are on, and EMS communicates with NC 2.

At least one embodiment of the pixel circuit of figure 13 of the present invention is shown in a low gray level,

In the first stage, RA provides a high voltage signal, RB provides a low voltage signal, RC and RD provide high voltage signals, DL provides a low voltage signal, T8 and T10 are conductive, and HF is communicated with NC 1;

In at least one embodiment of the pixel circuit shown in fig. 13 of the present invention, the gate of T17 and the gate of T18 may be replaced by being electrically connected to the first control terminal R1.

As shown in fig. 15, in at least one embodiment of the pixel circuit shown in fig. 6, the light emitting element is a micro light emitting diode ML;

t1 and T2 are p-type transistors, and T3 is an n-type transistor;

t4 and T5 are p-type transistors, and T6 is an n-type transistor;

the driving circuit includes a driving transistor T0;

The grid electrode of the driving transistor T0 is connected with a driving control node N0, the source electrode of the driving transistor T0 is electrically connected with a power supply voltage end ELVDD, and the drain electrode of the driving transistor T0 is electrically connected with a second node N2;

T0 is a p-type transistor, and TC1 and TC2 are p-type transistors;

The first initialization circuit includes a seventeenth transistor T17;

T17 is a p-type transistor;

The compensation control circuit comprises a sixteenth transistor T16, the data writing circuit comprises a fifteenth transistor T15, and the eighth energy storage circuit comprises a second storage capacitor Cs2;

a first end of the second storage capacitor Cs2 is electrically connected to the driving control node N0;

A gate of the fifteenth transistor T15 is electrically connected to the scanning line GL, a source of the fifteenth transistor T15 is electrically connected to the data line DL, and a drain of the fifteenth transistor T15 is electrically connected to the second end of the second storage capacitor Cs 2;

t15 and T16 are both p-type transistors;

The reference voltage writing circuit includes a nineteenth transistor T19 and a twentieth transistor T20;

A gate of the nineteenth transistor T19 is electrically connected to the first control terminal R1, a source of the nineteenth transistor T19 is electrically connected to the reference voltage terminal VR, and a drain of the nineteenth transistor T19 is electrically connected to the second terminal of the second storage capacitor Cs 2;

A gate of the twentieth transistor T20 is electrically connected to the second emission time control terminal EML, a source of the twentieth transistor T20 is electrically connected to the reference voltage terminal VR, and a drain of the twentieth transistor T20 is electrically connected to the second terminal of the second storage capacitor Cs 2;

t19 and T20 are both p-type transistors.

In operation, at least one embodiment of the driving circuit shown in fig. 15 of the present invention displays an ultra-low gray level, wherein the display period includes a first stage, a second stage, a third stage, a fourth stage and a fifth stage t5 sequentially arranged;

In the first stage, EML provides a high voltage signal, R1 provides a low voltage signal, GL provides a high voltage signal, SL provides a high voltage signal, DL provides a high voltage signal, EMS provides a high voltage signal, HF provides a high voltage signal, T1 is turned on, C1 maintains the potential of NK1 to be high voltage, T3 is turned on to control communication between NC1 and HF, and TC1 is turned off; t17 is turned on to write the initial voltage Vinit to the driving control node N0 so that T0 can be turned on when the second phase T2 starts; VR provides a reference voltage Vref, T19 is turned on to write Vref to the second terminal of Cs 2;

In the second stage, EML provides a high voltage signal, R1 provides a high voltage signal, GL provides a low voltage signal, SL provides a high voltage signal, DL provides a current control data voltage Vdata, EMS provides a high voltage signal, and HF provides a high voltage signal; c1 maintains the potential of NK1 to be high voltage, T3 is opened to control the communication between NC1 and HF, and TC1 is turned off; t15 is opened to write Vdata to the second end of C2, and T16 is conducted;

at the beginning of the second stage, T0 is conducted to charge Cs2 until T0 is turned off, the potential of N0 becomes Vdd+Vth, vdd is the voltage value of the power supply voltage signal provided by ELVDD, and Vth is the threshold voltage of T0;

In the third stage, EML provides a high voltage signal, R1 provides a high voltage signal, GL provides a high voltage signal, SL provides a low voltage signal, DL provides a low voltage signal, EMS provides a high voltage signal, and HF provides a high voltage signal; t4 is opened, potential of NK2 is maintained to be low voltage by C2, T5 is opened, communication between NK2 and EMS is controlled, potential of NK2 is enabled to be high voltage, and TC2 is turned off;

In the fourth stage, EML provides a low voltage signal, R1 provides a high voltage signal, GL provides a high voltage signal, SL provides a high voltage signal, DL provides a low voltage signal, EMS provides a high voltage signal, T19 is turned on, C1 maintains the potential of NK1 at a high voltage, T3 is turned on to control communication between HF and NC1, and TC1 is turned on when HF provides a low voltage signal; the potential of NK2 is maintained to be low voltage by C2, T5 is opened, NC2 is communicated with EMS, TC2 is turned off, and O1 does not emit light;

In the fourth stage, VR provides a reference voltage Vref, EML provides a low voltage signal, T20 is conducted, cs2 is changed from Vdata to Vref, and N0 is changed to Vdd+Vth+Vref-Vdata;

In the fifth stage, R1 provides a high voltage signal, GL provides a high voltage signal, SL provides a high voltage signal, T3 is on, HF communicates with NC1, T5 is on, EMS communicates with NC2, and when EML, HF and EMS all provide low voltage signals, T0 drives O1 to emit light.

At least one embodiment of the pixel circuit of figure 15 of the present invention displays a medium to high gray level,

In the first stage, DL provides a low voltage signal, T2 is conducted, and EML is communicated with NC 1;

in the third stage, DL provides a high voltage signal, T6 is on, and EML communicates with NC 2.

At least one embodiment of the pixel circuit of figure 15 of the present invention displays medium and low gray levels,

In the third stage, DL provides a low voltage signal, T5 is on, and EMS is in communication with NC 2.

At least one embodiment of the pixel circuit of figure 15 of the present invention is shown in a low gray level,

In the first stage, DL provides a high voltage signal, T3 is conducted, and HF is communicated with NC 1;

The operation timing diagram of at least one embodiment of the pixel circuit shown in fig. 15 of the present invention may be the same as that of at least one embodiment of the pixel circuit shown in fig. 7 of the present invention, but is not limited thereto.

An embodiment of the present invention provides a driving method, which is applied to the above pixel circuit, and includes:

The embodiment of the invention provides a display device which comprises the pixel circuit.

While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that various modifications and adaptations can be made without departing from the principles of the present invention, and such modifications and adaptations are intended to be comprehended within the scope of the present invention.

Claims

1. A pixel circuit, comprising a driving circuit, a first on-off control circuit, a light-emitting element, a second on-off control circuit, a first control circuit and a second control circuit;

The first end of the driving circuit is electrically connected to the first node, and the second end of the driving circuit is electrically connected to the second node; the driving circuit is used to generate a driving current for driving the light-emitting element under the control of the potential of its control end;

The first on-off control circuit is used to control the connection or disconnection between the second node and the third node under the control of the potential of the first control node;

The first electrode of the light emitting element is electrically connected to the third node;

The second on-off control circuit is used to control the connection or disconnection between the second electrode of the light-emitting element and the first voltage terminal under the control of the potential of the second control node;

The first control circuit is electrically connected to the first control terminal, the data line, the first light-emitting time control terminal, the second light-emitting time control terminal and the first control node respectively, and is used to control the connection between the first light-emitting time control terminal or the second light-emitting time control terminal and the first control node according to the first time control data voltage provided by the data line under the control of the first control signal provided by the first control terminal;

The second control circuit is electrically connected to the second control terminal, the data line, the second luminous time control terminal, the third luminous time control terminal and the second control node, respectively, and is used to control the connection between the second luminous time control terminal or the third luminous time control terminal and the second control node according to the second time control data voltage provided by the data line under the control of the second control signal provided by the second control terminal.

2. The pixel circuit according to claim 1, wherein the first control circuit comprises a first writing circuit, a first energy storage circuit, a first switch control circuit and a second switch control circuit;

The first writing circuit is electrically connected to the first control terminal, the data line and the first switch node respectively, and is used to write the first time control data voltage into the first switch node under the control of the first control signal provided by the first control terminal;

The first energy storage circuit is electrically connected to the first switch node and is used to maintain the potential of the first switch node;

The first switch control circuit is electrically connected to the first switch node, the second light-emitting time control terminal and the first control node respectively, and is used to control the connection or disconnection between the first control node and the second light-emitting time control terminal under the control of the potential of the first switch node;

The second switch control circuit is electrically connected to the first switch node, the first light-emitting time control end and the first control node respectively, and is used to control the connection or disconnection between the first control node and the first light-emitting time control end under the control of the potential of the first switch node.

3. The pixel circuit according to claim 1, wherein the second control circuit comprises a second writing circuit, a second energy storage circuit, a third switch control circuit and a fourth switch control circuit;

The second writing circuit is electrically connected to the second control terminal, the data line and the second switch node respectively, and is used to write the second time control data voltage provided by the data line into the second switch node under the control of the second control signal provided by the second control terminal;

The second energy storage circuit is electrically connected to the second switch node, and is used to maintain the potential of the second switch node;

The third switch control circuit is electrically connected to the second switch node, the third light-emitting time control terminal and the second control node respectively, and is used to control the connection or disconnection between the second control node and the third light-emitting time control terminal under the control of the potential of the second switch node;

The fourth switch control circuit is electrically connected to the second switch node, the second luminous time control terminal and the second control node respectively, and is used to control the connection or disconnection between the second control node and the second luminous time control terminal under the control of the potential of the second switch node.

4. The pixel circuit according to claim 1, characterized in that the first control circuit comprises a third writing circuit, a fourth writing circuit, a fifth switch control circuit, a sixth switch control circuit, a third energy storage circuit and a fourth energy storage circuit; the first control terminal comprises a first reset control terminal and a second reset control terminal;

The third writing circuit is electrically connected to the first reset control terminal, the data line and the third switch node respectively, and is used to write the third time control data voltage provided by the data line into the third switch node under the control of the first reset control signal provided by the first reset control terminal;

The third energy storage circuit is electrically connected to the third switch node, and is used to maintain the potential of the third switch node;

The fourth writing circuit is electrically connected to the second reset control terminal, the data line and the fourth switch node respectively, and is used to write the fourth time control data voltage provided by the data line into the fourth switch node under the control of the second reset control signal provided by the second reset control terminal;

The fourth energy storage circuit is electrically connected to the fourth switch node, and is used to maintain the potential of the fourth switch node;

The fifth switch control circuit is electrically connected to the third switch node, the second light-emitting time control terminal and the first control node respectively, and is used to control the connection or disconnection between the second light-emitting time control terminal and the first control node under the control of the potential of the third switch node;

The sixth switch control circuit is electrically connected to the fourth switch node, the first light-emitting time control terminal and the first control node respectively, and is used to control the connection or disconnection between the first light-emitting time control terminal and the first control node under the control of the potential of the fourth switch node.

5. The pixel circuit according to claim 1, wherein the second control circuit comprises a fifth writing circuit, a sixth writing circuit, a seventh switch control circuit, an eighth switch control circuit, a fifth energy storage circuit and a sixth energy storage circuit; the second control terminal comprises a third reset control terminal and a fourth reset control terminal;

The fifth writing circuit is electrically connected to the third reset control terminal, the data line and the fifth switch node respectively, and is used to write the fifth time control data voltage provided by the data line into the fifth switch node under the control of the third reset control signal provided by the third reset control terminal;

The fifth energy storage circuit is electrically connected to the fifth switch node, and is used to maintain the potential of the fifth switch node;

The sixth writing circuit is electrically connected to the fourth reset control terminal, the data line and the sixth switch node respectively, and is used to write the sixth time control data voltage provided by the data line into the sixth switch node under the control of the fourth reset control signal provided by the fourth reset control terminal;

The sixth energy storage circuit is electrically connected to the sixth switch node, and is used to maintain the potential of the sixth switch node;

The seventh switch control circuit is electrically connected to the fifth switch node, the second light-emitting time control terminal and the second control node respectively, and is used to control the connection or disconnection between the second light-emitting time control terminal and the second control node under the control of the potential of the fifth switch node;

The eighth switch control circuit is electrically connected to the sixth switch node, the third light-emitting time control terminal and the second control node respectively, and is used to control the connection or disconnection between the third light-emitting time control terminal and the second control node under the control of the potential of the sixth switch node.

6. The pixel circuit according to claim 1, wherein the driving circuit comprises a driving transistor;

The gate of the driving transistor is electrically connected to the control terminal of the driving circuit, the first electrode of the driving circuit is electrically connected to the first node, and the second electrode of the driving circuit is electrically connected to the second node;

The first on-off control circuit includes a first control transistor, and the second on-off control circuit includes a second control transistor;

The gate of the first control transistor is electrically connected to the first control node, the first electrode of the first control transistor is electrically connected to the second node, and the second electrode of the first control transistor is electrically connected to the third node;

The gate of the second control transistor is electrically connected to the second control node, the first electrode of the second control transistor is electrically connected to the second electrode of the light emitting element, and the second electrode of the second control transistor is electrically connected to the first voltage terminal.

7. The pixel circuit according to claim 2, wherein the first writing circuit comprises a first transistor, the first energy storage circuit comprises a first capacitor, the first switch control circuit comprises a second transistor, and the second switch control circuit comprises a third transistor;

The gate of the first transistor is electrically connected to the first control terminal, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the first switch node;

A first end of the first capacitor is electrically connected to the first switch node, and a second end of the first capacitor is electrically connected to an initial voltage end;

The gate of the second transistor is electrically connected to the first switch node, the first electrode of the second transistor is electrically connected to the second light emitting time control terminal, and the second electrode of the second transistor is electrically connected to the first control node;

A gate of the third transistor is electrically connected to the first switch node, a first electrode of the third transistor is electrically connected to the first light emitting time control terminal, and a second electrode of the third transistor is electrically connected to the first control node.

8. The pixel circuit according to claim 3, wherein the second writing circuit comprises a fourth transistor, the second energy storage circuit comprises a second capacitor, the third switch control circuit comprises a fifth transistor, and the fourth switch control circuit comprises a sixth transistor;

The gate of the fourth transistor is electrically connected to the second control terminal, the first electrode of the fourth transistor is electrically connected to the data line, and the second electrode of the fourth transistor is electrically connected to the second switch node;

A first end of the second capacitor is electrically connected to the second switch node, and a second end of the second capacitor is electrically connected to the initial voltage end;

The gate of the fifth transistor is electrically connected to the second switch node, the first electrode of the fifth transistor is electrically connected to the third light emitting time control terminal, and the second electrode of the fifth transistor is electrically connected to the second control node;

A gate of the sixth transistor is electrically connected to the second switch node, a first electrode of the sixth transistor is electrically connected to the second light emitting time control terminal, and a second electrode of the sixth transistor is electrically connected to the second control node.

9. The pixel circuit according to claim 4, wherein the third writing circuit comprises a seventh transistor, the fourth writing circuit comprises an eighth transistor, the third energy storage circuit comprises a third capacitor, the fourth energy storage circuit comprises a fourth capacitor, the fifth switch control circuit comprises a ninth transistor, and the sixth switch control circuit comprises a tenth transistor;

The gate of the seventh transistor is electrically connected to the first reset control terminal, the first electrode of the seventh transistor is electrically connected to the data line, and the second electrode of the seventh transistor is electrically connected to the third switch node;

The first end of the third capacitor is electrically connected to the third switch node, and the second end of the third capacitor is electrically connected to the initial voltage end;

The gate of the eighth transistor is electrically connected to the second reset control terminal, the first electrode of the eighth transistor is electrically connected to the data line, and the second electrode of the eighth transistor is electrically connected to the fourth switch node;

A first end of the fourth capacitor is electrically connected to the fourth switch node, and a second end of the fourth capacitor is electrically connected to the initial voltage end;

The gate of the ninth transistor is electrically connected to the third switch node, the first electrode of the ninth transistor is electrically connected to the second light emitting time control terminal, and the second electrode of the ninth transistor is electrically connected to the first control node;

A gate of the tenth transistor is electrically connected to the fourth switch node, a first electrode of the tenth transistor is electrically connected to the first light emitting time control terminal, and a second electrode of the tenth transistor is electrically connected to the first control node.

10. The pixel circuit according to claim 5, wherein the fifth writing circuit comprises an eleventh transistor, the sixth writing circuit comprises a twelfth transistor, the seventh switch control circuit comprises a thirteenth transistor, the eighth switch control circuit comprises a fourteenth transistor, the fifth energy storage circuit comprises a fifth capacitor, and the sixth energy storage circuit comprises a sixth capacitor;

The gate of the eleventh transistor is electrically connected to the third reset control terminal, the first electrode of the eleventh transistor is electrically connected to the data line, and the second electrode of the eleventh transistor is electrically connected to the fifth switch node;

A first end of the fifth capacitor is electrically connected to the fifth switch node, and a second end of the fifth capacitor is electrically connected to the initial voltage end;

The gate of the twelfth transistor is electrically connected to the fourth reset control terminal, the first electrode of the twelfth transistor is electrically connected to the data line, and the second electrode of the twelfth transistor is electrically connected to the sixth switch node;

The first end of the sixth capacitor is electrically connected to the sixth switch node, and the second end of the sixth capacitor is electrically connected to the initial voltage end;

The gate of the thirteenth transistor is electrically connected to the fifth switch node, the first electrode of the thirteenth transistor is electrically connected to the second light emitting time control terminal, and the second electrode of the thirteenth transistor is electrically connected to the second control node;

A gate of the fourteenth transistor is electrically connected to the sixth switch node, a first electrode of the fourteenth transistor is electrically connected to the third light emitting time control terminal, and a second electrode of the fourteenth transistor is electrically connected to the second control node.

11. The pixel circuit according to any one of claims 1 to 10, further comprising a data writing circuit, a compensation control circuit and a seventh energy storage circuit;

The data writing circuit is electrically connected to the scan line, the data line and the first node respectively, and is used to write the current-controlled data voltage provided by the data line into the first node under the control of the scan signal provided by the scan line;

The compensation control circuit is electrically connected to the scan line, the control end of the drive circuit and the second node respectively, and is used to control the connection or disconnection between the control end of the drive circuit and the second node under the control of the scan signal;

The seventh energy storage circuit is electrically connected to the control end of the driving circuit and is used for storing electric energy.

12. The pixel circuit according to any one of claims 1 to 3, further comprising a first initialization circuit and a second initialization circuit;

The first initialization circuit is electrically connected to the first control terminal, the initial voltage terminal and the control terminal of the driving circuit respectively, and is used to write the initial voltage provided by the initial voltage terminal into the control terminal of the driving circuit under the control of the first control signal provided by the first control terminal;

The second initialization circuit is electrically connected to the first control terminal, the initial voltage terminal and the first electrode of the light-emitting element respectively, and is used to write the initial voltage into the first electrode of the light-emitting element under the control of the first control signal.

13. The pixel circuit according to claim 11, further comprising a light emitting control circuit;

The light-emitting control circuit is electrically connected to the second light-emitting time control terminal, the power supply voltage terminal and the first node respectively, and is used to control the connection between the power supply voltage terminal and the first node under the control of a second light-emitting time control signal provided by the second light-emitting time control terminal.

14. The pixel circuit according to claim 4 or 5, characterized in that the first control terminal comprises a first reset control terminal and a second reset control terminal;

The pixel circuit further includes a first initialization circuit and a second initialization circuit;

The first initialization circuit is electrically connected to the first reset control terminal, the initial voltage terminal and the control terminal of the driving circuit respectively, and is used to write the initial voltage provided by the initial voltage terminal into the control terminal of the driving circuit under the control of the first reset control signal provided by the first reset control terminal;

The second initialization circuit is electrically connected to the first reset control terminal, the initial voltage terminal and the first electrode of the light-emitting element respectively, and is used to write the initial voltage into the first electrode of the light-emitting element under the control of the first reset control signal.

15. The pixel circuit according to any one of claims 1 to 3, further comprising a compensation control circuit, a data writing circuit and an eighth energy storage circuit; the first node is electrically connected to a power supply voltage terminal;

The first end of the eighth energy storage circuit is electrically connected to the control end of the driving circuit; the eighth energy storage circuit is used to store electrical energy;

The compensation control circuit is electrically connected to the scan line, the control end of the drive circuit and the second node respectively, and is used to control the connection or disconnection between the control end of the drive circuit and the second node under the control of the scan signal provided by the scan line;

The data writing circuit is electrically connected to the scan line, the data line and the second end of the eighth energy storage circuit respectively, and is used to write the current-controlled data voltage provided by the data line into the second end of the eighth energy storage circuit under the control of the scan signal.

16. The pixel circuit according to claim 15, further comprising a reference voltage writing circuit;

The reference voltage writing circuit is electrically connected to the first control terminal, the second luminous time control terminal, the reference voltage terminal and the second terminal of the eighth energy storage circuit, respectively, and is used to write the reference voltage provided by the reference voltage terminal into the second terminal of the eighth energy storage circuit under the control of the first control signal provided by the first control terminal, and to write the reference voltage into the second terminal of the eighth energy storage circuit under the control of the second luminous time control signal provided by the second luminous time control terminal.

17. The pixel circuit according to claim 11, wherein the data writing circuit comprises a fifteenth transistor, the compensation control circuit comprises a sixteenth transistor, and the seventh energy storage circuit comprises a first storage capacitor;

The gate of the sixteenth transistor is electrically connected to the scan line, the first electrode of the sixteenth transistor is electrically connected to the control terminal of the driving circuit, and the second electrode of the sixteenth transistor is electrically connected to the second node;

A first end of the first storage capacitor is electrically connected to a control end of the driving circuit, and a second end of the first storage capacitor is electrically connected to a power supply voltage end.

18. The pixel circuit according to claim 12, wherein the first initialization circuit comprises a seventeenth transistor, and the second initialization circuit comprises an eighteenth transistor;

The gate of the seventeenth transistor is electrically connected to the first control terminal, the first electrode of the seventeenth transistor is electrically connected to the initial voltage terminal, and the second electrode of the seventeenth transistor is electrically connected to the control terminal of the driving circuit;

The gate of the eighteenth transistor is electrically connected to the first control terminal, the first electrode of the eighteenth transistor is electrically connected to the initial voltage terminal, and the second electrode of the eighteenth transistor is electrically connected to the first electrode of the light emitting element.

19. The pixel circuit according to claim 13, wherein the light emitting control circuit comprises a nineteenth transistor;

The gate of the nineteenth transistor is electrically connected to the second light emitting time control terminal, the first electrode of the nineteenth transistor is electrically connected to the power supply voltage terminal, and the second electrode of the nineteenth transistor is electrically connected to the first node.

20. The pixel circuit according to claim 14, wherein the first initialization circuit comprises a seventeenth transistor, and the second initialization circuit comprises an eighteenth transistor;

The gate of the seventeenth transistor is electrically connected to the first reset control terminal, the first electrode of the seventeenth transistor is electrically connected to the initial voltage terminal, and the second electrode of the seventeenth transistor is electrically connected to the control terminal of the driving circuit;

21. The pixel circuit according to claim 15, wherein the compensation control circuit comprises a sixteenth transistor, the data writing circuit comprises a fifteenth transistor, and the eighth energy storage circuit comprises a second storage capacitor;

A first end of the second storage capacitor is electrically connected to a control end of the drive circuit;

A gate of the fifteenth transistor is electrically connected to the scan line, a first electrode of the fifteenth transistor is electrically connected to the data line, and a second electrode of the fifteenth transistor is electrically connected to the second end of the second storage capacitor.

22. The pixel circuit according to claim 16, wherein the reference voltage writing circuit comprises a nineteenth transistor and a twentieth transistor;

The gate of the nineteenth transistor is electrically connected to the first control terminal, the first electrode of the nineteenth transistor is electrically connected to the reference voltage terminal, and the second electrode of the nineteenth transistor is electrically connected to the second terminal of the eighth energy storage circuit;

The gate of the twentieth transistor is electrically connected to the second light emitting time control terminal, the first electrode of the twentieth transistor is electrically connected to the reference voltage terminal, and the second electrode of the twentieth transistor is electrically connected to the second terminal of the eighth energy storage circuit.

23. A driving method, applied to the pixel circuit according to any one of claims 1 to 22, characterized in that the driving method comprises:

The driving circuit generates a driving current for driving the light emitting element under the control of the potential of the control terminal;

The second on-off control circuit controls the connection or disconnection between the second electrode of the light-emitting element and the first voltage terminal under the control of the potential of the second control node;

The first control circuit, under the control of the first control signal, controls the connection between the first light emitting time control terminal or the second light emitting time control terminal and the first control node according to the first time control data voltage provided by the data line;

Under the control of the second control signal, the second control circuit controls the connection between the second light emitting time control terminal or the third light emitting time control terminal and the second control node according to the second time control data voltage provided by the data line.

24. A display device, comprising the pixel circuit according to any one of claims 1 to 22.