CN119025169A

CN119025169A - System on chip and startup method thereof, processor, electronic device and storage medium

Info

Publication number: CN119025169A
Application number: CN202411111763.3A
Authority: CN
Inventors: 杨维韬; 张璐; 李信德
Original assignee: Phytium Technology Co Ltd
Current assignee: Phytium Technology Co Ltd
Priority date: 2024-08-13
Filing date: 2024-08-13
Publication date: 2024-11-26

Abstract

The present disclosure provides a system on chip and a startup method thereof, an electronic device and a storage medium. The system on chip startup method of the embodiment of the present disclosure comprises: after power-on, the first processor loads the first instruction segment to the first predetermined space of the first memory for use by the second processor, and loads the second instruction segment to the second memory for use by the second processor; wherein the first instruction segment and the second instruction segment are from the firmware of the second processor. The embodiment of the present disclosure can realize the space expansion of a specific processor in the system on chip without increasing the circuit board area and hardware cost.

Description

System on chip, starting method thereof, processor, electronic device and storage medium

Technical Field

The present disclosure relates to the field of chip technologies, and in particular, to a system on a chip, a method for starting the system on a chip, a processor, an electronic device, and a storage medium.

Background

A multiprocessor architecture of a System on a Chip (SoC) is to integrate multiple processor cores on one Chip to achieve higher performance, lower power consumption, and a more compact System design. Such architectures are typically used for applications that require processing of a large number of parallel tasks or require higher computing power. In a multiprocessor architecture of a system-on-chip, each processor core may run programs independently, perform tasks, and communicate and cooperate via a shared memory or other communication mechanism.

In a system on a chip of a multiprocessor architecture, the instruction space and the data space of a part of the processor are set to be fixed in size, and then the instruction and the data of the processor are continuously increased due to the continuous increase of requirements such as function debugging, client application expansion and the like, and the instruction space and the data space of the processor face the problem of insufficient capacity.

Disclosure of Invention

In view of this, the present disclosure provides a system on a chip, and a method, an apparatus, a processor, an electronic device, and a storage medium for starting the same, which can implement spatial expansion of a specific processor in the system on a chip without increasing a circuit board area and a hardware cost.

According to a first aspect of the present disclosure, there is provided a method of booting a system on a chip, the system on a chip including a first processor, a second processor, a first memory and a second memory, the first processor and the second processor having access to the first memory, the second processor having access to the second memory; the starting method of the system on chip comprises the following steps: after power-on, the first processor loads the first instruction segment to a first preset space of a first memory for the second processor to use, and loads the second instruction segment to the second memory for the second processor to use; wherein the first instruction segment and the second instruction segment are from firmware of the second processor.

In some implementations of the first aspect of the disclosure, the first instruction segment performs the operation of a first peripheral controller when executed by the second processor, and the second instruction segment performs the operation of a second peripheral controller when executed by the second processor.

In some embodiments of the first aspect of the present disclosure, the first peripheral controller includes one or more of: CODEC, I2S; the second external controller includes one or more of the following: UART, I2C, SPI, HDA, GMAC, NPU.

In some implementations of the first aspect of the present disclosure, the first instruction segment, when executed by a second processor, performs a first operation of a third peripheral controller, and the second instruction segment, when executed by the second processor, performs a second operation of the third peripheral controller.

In some implementations of the first aspect of the present disclosure, the firmware of the second processor further includes: a first data segment corresponding to the first instruction segment and a second data segment corresponding to the second instruction segment; the system on a chip further includes a third memory, the third memory being accessible by the second processor; the method further comprises the steps of: the second processor performs an initialization operation, the initialization operation comprising: copying the first data segment to a second predetermined space of the first memory and copying the second data segment to the third memory.

In some embodiments of the first aspect of the present disclosure, the method further comprises: a second processor applies for stack space from a second predetermined space of the first memory to store data generated when the second processor runs the first instruction segment; the second processor applies for stack space from the third memory to store data generated when the second processor runs the second instruction segment.

In some embodiments of the first aspect of the present disclosure, further comprising: before loading the first instruction segment and the second instruction segment, the first memory is spatially partitioned to configure a first predetermined space for storing the first instruction segment and a second predetermined space for storing a first data segment.

In some implementations of the first aspect of the present disclosure, the first processor runs basic firmware pre-loaded in a system-on-chip to perform a method of booting the system-on-chip.

In some implementations of the first aspect of the present disclosure, the method of booting the system-on-chip is performed by the first processor while in the EL3 secure environment.

In some embodiments of the first aspect of the present disclosure, the method further comprises: after the first instruction segment and the second instruction segment are loaded, the first processor rewrites the reset value in the first register to trigger the second processor to start.

According to a second aspect of the present disclosure, there is provided a peripheral management method of a system on chip, including:

Responding to a request initiated by a first processor for a first peripheral controller, and initiating an instruction fetching request for a first preset space of a first memory by a second processor;

the second processor receives a first instruction returned by the first memory in response to the instruction fetching request;

a second processor executes the first instruction to obtain first data corresponding to the first instruction from the first memory;

The second processor sends a data access request to the first memory by using the first instruction and the corresponding first data, so that the first processor can acquire the data of the first peripheral controller requested by the first processor.

In some embodiments of the second aspect of the present disclosure, further comprising: a second processor receives second data returned by the first memory in response to the data access request; the second processor parses the second data to obtain third data, and writes the third data back to the first memory so that the first processor can acquire the third data.

In some embodiments of the second aspect of the present disclosure, further comprising: after the second processor initiates an instruction fetching request for a first preset space of the first memory, the instruction fetching request is subjected to address conversion by a bus network to which the second processor belongs based on an address mapping relation in a second register and then is forwarded to the first memory.

In some implementations of the second aspect of the disclosure, the second processor sending a data access request to the first memory using the first instruction and its corresponding first data, including: the second processor core initiates a data access request aiming at the first memory by utilizing the first instruction and the corresponding first data; and forwarding the data access request to the first memory through a bus network to which the second processor belongs after performing address conversion based on the address mapping relation in the second register.

According to a third aspect of the present disclosure, there is provided a system on a chip, comprising: a first processor, a second processor, a first memory, and a second memory, each of the first processor and the second processor having access to the first memory, the second processor having access to the second memory, the first processor being communicable with the second processor; the first processor is configured to load the first instruction segment into a first predetermined space of a first memory for use by the second processor after power-up, and load the second instruction segment into the second memory for use by the second processor; wherein the first instruction segment and the second instruction segment are from firmware of the second processor.

In some embodiments of the third aspect of the present disclosure, the system on a chip includes a first bus and a second bus; the first memory and the first processor are connected to a first bus, the second memory and the second processor are connected to a second bus, and the second bus is hung on the first bus.

In some embodiments of the third aspect of the present disclosure, the first memory is provided with: a first instruction interface and a first data read-write interface for a core of the first processor; and a second instruction interface and a second data read-write interface for a core of the second processor.

According to a fourth aspect of the present disclosure, there is provided an electronic device comprising the above-described system-on-chip.

According to a fifth aspect of the present disclosure, there is provided a computer readable storage medium storing a program comprising instructions which, when executed by a processor, cause the processor to perform the method of the first aspect or the method of the second aspect.

As can be seen from the above technical solutions, in the embodiments of the present disclosure, a part of instruction segments in firmware of a second processor are stored in a first memory, instead of storing all instruction segments in firmware of the second processor in the second memory, so that functions and instruction codes of the firmware of the second memory can be continuously extended by using a memory of a system on a chip or a memory space shared by each processor, without further adding a memory dedicated to the second processor in the system on a chip, it can be seen that the embodiments of the present disclosure can realize the instruction space extension of a specific processor in the system on a chip without increasing the circuit board area and hardware cost, and can also extend the data space of the specific processor.

Drawings

In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.

FIG. 1 is a schematic diagram of a system-on-chip architecture provided by an embodiment of the present disclosure;

FIG. 2 is a flowchart illustrating a method for system on a chip start-up according to an embodiment of the present disclosure;

FIG. 3 is a diagram illustrating a first processor space division example in accordance with an embodiment of the present disclosure;

FIG. 4 is a diagram of an example distribution of binary files according to an embodiment of the present disclosure;

FIG. 5 is a diagram illustrating an example of a boot method according to an embodiment of the present disclosure;

fig. 6 is a flowchart illustrating a peripheral management method of a system on a chip according to an embodiment of the disclosure;

FIG. 7 is a schematic diagram of a connection structure of a system-on-chip processor and a memory according to an embodiment of the present disclosure;

fig. 8 is a schematic block diagram of an electronic device provided by an embodiment of the present disclosure.

Detailed Description

The following description of the technical solutions in the embodiments of the present disclosure will be made clearly and completely with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments in this disclosure, all other embodiments that a person of ordinary skill in the art would obtain without making any inventive effort are within the scope of protection of this disclosure.

The terminology used in the embodiments of the disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used in this disclosure and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be understood that the term "and/or" as used herein is merely one relationship describing the association of the associated objects, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.

Depending on the context, the word "if" as used herein may be interpreted as "at … …" or "at … …" or "in response to a determination" or "in response to a detection". Similarly, the phrase "if determined" or "if detected (stated condition or event)" may be interpreted as "when determined" or "in response to determination" or "when detected (stated condition or event)" or "in response to detection (stated condition or event), depending on the context.

Term interpretation:

RV kernel: i.e. a processor core based on a RISC-V instruction set architecture, RISC-V is an open Instruction Set Architecture (ISA) based on the principle of a Reduced Instruction Set Computer (RISC), and the RISC-V ISA has simple and modularized design, expandability and can support different application requirements. It defines a basic set of instructions and also provides standard extensions such as floating point, vector, encryption, etc., so that the user can choose the appropriate instruction set extension according to his own needs. The second processor of the disclosed embodiments employs RV core construction.

And (3) peripheral equipment: external hardware devices connected on the SoC, including but not limited to serial devices, audio devices, storage devices, and the like.

SUMMARY

In the related art, the instruction space and the data space of the second processor are set to have a fixed size, and if the instruction space and the data space of the second processor need to be expanded, a relatively high-cost memory such as SRAM needs to be added to the system on chip, which results in an increase in the area of the system on chip and an excessive cost. In view of this, the embodiments of the present disclosure provide the following system on chip and a method for starting the same, an electronic device, and a storage medium.

System architecture

Embodiments of the present disclosure provide a system-on-chip, which may include: the system comprises a first processor, a second processor, a first memory and a second memory, wherein the first memory can be accessed by the first processor and the second processor, the second memory can be accessed by the second processor, and the first processor and the second processor can communicate; the firmware of the second processor comprises a first instruction segment and a second instruction segment, wherein the first processor is used for loading the first instruction segment into a first preset space of the first memory for the second processor to use after power-on, and loading the second instruction segment into the second memory for the second processor to use.

The system-on-chip may include a first bus on which the first memory is coupled with the first processor and a second bus on which the second memory is coupled with the second processor, the second bus being suspended from the first bus. The first bus is a system bus of the system on chip, and the second bus is a bus of the second processor. Illustratively, the first bus may be implemented as the NOC below and the second bus may be implemented as the NCC below.

The first memory may be provided with: a first instruction interface and a first data read-write interface for a core of a first processor; and a second instruction interface and a second data read-write interface for the core of the second processor. By adding the instruction interface and the data access interface of the second processor and checking the first memory, the instruction segment, the data segment and the like can be loaded to the first memory to realize the expansion of the instruction space and the data space.

Specific implementations of the system-on-chip provided by embodiments of the present disclosure are described in detail below.

Fig. 1 shows an exemplary architecture diagram of a system on a chip provided by an embodiment of the present application. Referring to fig. 1, a system on a chip 100 may include: the system comprises a first processor, a second processor, a first memory (not shown), a second memory (not shown), a third memory (not shown), and an inter-core communication component, wherein the first processor and the second processor are in communication through the inter-core communication component, the first memory is accessible by the first processor and the second processor, the second memory is used for storing program files of the second process, and the third memory is used for storing data required by the second processor.

The first memory may be a memory of the system on chip, or may be another memory built in the system on chip. Illustratively, the first memory of the disclosed embodiments is preferably a double rate synchronous dynamic random access memory (DDR, double Data Rate Synchronous Dynamic Random Access Memory) or the like because DDR has a higher data transfer rate and efficiency, and is capable of transferring data twice per clock cycle, providing a higher bandwidth. It is understood that the first memory may also be any other type of Random Access Memory (RAM), such as static random access memory (SRAM, static Random Access Memory), synchronous dynamic random access memory (SDRAM, synchronous Dynamic Random Access Memory), dynamic random access memory (DRAM, dynamic Random Access Memory), etc. The embodiments of the present disclosure are not limited in this regard.

The second memory and the third memory are both dedicated memories of the second processor and may be disposed on the second processor side. Illustratively, the second memory may be, but is not limited to, a static random access memory (SRAM, static Random Access Memory) or other similar memory. The third memory may be, but is not limited to, DCCM or other similar memories.

The first processor may be a single-core processor or a multi-core processor, and the cores of the first processor may be, but are not limited to, ARM, RV cores, or other various types of processor cores.

The second processor may be a single-core processor, which may employ a processor core based on a RISC-V instruction set architecture (herein simply referred to as RV core), an ARM core, or the same processor core as the first processor.

Communication between the first processor and the second processor may be achieved by, for example, an inter-core communication component, a low speed serial bus, a high speed serial bus, or any other feasible manner. Inter-core communication components may include, but are not limited to, register sets (regfile), shared memory sets (shared memory), and the like.

A conflict often occurs with multiple peripherals using one register set at a time. To avoid such a conflict, in one example, multiple register sets may be provided in the inter-core communication component, with different register sets corresponding to different peripherals. The register set in the inter-core communication assembly and the peripheral equipment can be in one-to-one correspondence, one-to-many correspondence or one-to-many correspondence. For example, the inter-core communication component is provided with a plurality of register sets, each register set corresponds to one peripheral, and the peripherals corresponding to different register sets are different.

Each register set contains various registers such as interrupt registers, and the embodiments of the present disclosure are not limited with respect to the number of registers in the register set and their functions.

In one example, the inter-core communication component may further include a plurality of shared memory groups, each shared memory group corresponds to a peripheral, and the peripherals corresponding to different shared memory groups are different.

Referring to fig. 1, peripherals of the soc may include, but are not limited to, serial devices, audio devices, storage devices, and the like. The embodiments of the present disclosure are not limited with respect to the type of peripheral for the SoC and the number thereof.

Illustratively, the first processor may employ a large core, the second processor may employ a small core, the first processor may serve as a master processor of the system-on-chip, the second processor may serve as a slave processor of the system-on-chip, various tasks of the application layer of the system-on-chip may be responsible for the first processor, and the second processor may be used to perform related processing of specific components in the system-on-chip, such as peripherals, input-output interfaces, and the like.

Referring to FIG. 1, a first processor may be used to perform application layer tasks, preferably a multi-core processor including, but not limited to, core 1, cores 2, … …, core n, where n is an integer greater than 2, and each core in the first processor may be the same or different.

Referring to fig. 2, the second Processor may be a Processor (IOP) that processes input output (I/O) operations, and may be an external hardware device (referred to herein simply as a peripheral) that manages the SoC. The second processor is capable of directly accessing the peripheral, and the first processor can complete access operations to the peripheral by communicating with the second processor.

Referring to fig. 1, the second processor may integrate, embed or externally connect with a plurality of types of peripheral controllers (which may also be referred to as peripheral controller interfaces), and the processor core of the second processor may be connected with the peripheral controllers through an internal bus of the second processor, and the peripheral controllers may communicate with corresponding external hardware devices through different standard bus protocols, so that the processor core of the second processor may interact with the peripheral devices through the peripheral controllers.

Referring to fig. 1, the peripheral controller may include, but is not limited to: universal serial communication interface (UART, universal Asynchronous Receiver-Transmitter), serial communication bus interface (I2C, inter-INTEGRATED CIRCUIT), synchronous serial data interface (SPI, serial Peripheral Interface), high definition audio interface (HAD, high Definition Audio), memory Card interface (SD/MMC, secure Digital/Multimedia Card), gigabit ethernet controller interface (GMAC, gigabit MEDIA ACCESS Control), neural processing unit (NPU, neural Processing Unit), digital audio interface standard (I2S, inter-IC Sound), CODEC (Coder-Decoder), enhanced serial peripheral interface (eSPI, enhanced Serial Peripheral Interface), and the like. In a specific application, the peripheral controller integrated, built-in or connected with the second processor can be flexibly expanded according to the actual application requirement, and the embodiment of the disclosure is not limited in this regard.

UARTs may be used for serial data transfer between a computer system and an external device for connecting to peripherals such as modems, serial printers, etc.

I2C may be used to connect communications between integrated circuits, to connect peripherals such as sensors, memory, displays, etc.

The SPI can be used for high-speed data transmission between a computer system and an external device, and is used for connecting with peripheral devices such as a flash memory, a sensor, a display and the like.

HAD may be used to connect audio devices (e.g., speakers, microphones, sound cards, etc.) as peripherals for high definition audio transmission and processing.

The SD/MMC can be used to connect with external storage devices (i.e., peripherals) such as flash memory cards, multimedia cards, etc., and is used in devices such as digital cameras, cell phones, etc. The GMAC is used for connecting a computer system and a gigabit Ethernet network to realize high-speed network communication.

The NPU may be used to perform artificial neural network calculations for deep learning and artificial intelligence applications.

The I2S can be used for connecting with peripheral equipment such as an audio codec, a digital signal processor and the like, and realizing high-quality audio transmission. CODECs are used for encoding and decoding digital signals for use in audio and video processing.

ESPI is used to connect computer systems and peripherals, supporting high-speed data transfer and functional expansion.

It should be noted that, although the external controller is disposed in the second processor in fig. 1, those skilled in the art should understand that the external controller may be disposed outside the second processor in specific applications as required.

The system-on-chip 100 of the disclosed embodiments may include other processors in addition to the first and second processors described above. Referring to fig. 1, the system on chip 100 may further include a third processor that may also be used as a slave processor that may be used to perform processes such as system control, security tasks, which may include, but are not limited to, encryption and decryption, security authentication, etc., system control, including, but not limited to, system power up and down, system configuration, etc. The third processor may communicate with the first processor through an inter-core communication component between itself and the first processor, which may include, but is not limited to, shared memory, etc.

It should be noted that the system 100 is merely illustrative, and the system architecture to which the embodiments of the present disclosure are applicable is not limited thereto. Those skilled in the art will appreciate that other configurations of the system-on-chip of the disclosed embodiments may also be employed, so long as two processors are included in the system-on-chip.

Exemplary method

Fig. 2 shows a flowchart of a system on chip start-up method 200 provided by an embodiment of the present disclosure. Referring to fig. 2, a system on chip start-up method 200 provided by an embodiment of the present disclosure may include:

Step 201, after powering up, the first processor loads the first instruction segment into a first predetermined space of the first memory for the second processor to use, and loads the second instruction segment into the second memory for the second processor to use, wherein the first instruction segment and the second instruction segment are derived from firmware of the second processor.

The first instruction segment and the second instruction segment may correspond to the same peripheral controller, or may correspond to different peripheral controllers. The instruction segment with low requirements on the factors such as safety, real-time performance and importance can be used as a first instruction segment to be placed in the first memory, and the instruction segment with high requirements on the factors such as safety, real-time performance and importance can be used as a second instruction segment to be placed in the second memory.

In some embodiments, the first instruction segment performs the operation of the first peripheral controller when executed by the second processor, and the second instruction segment performs the operation of the second peripheral controller when executed by the second processor. Therefore, the instruction segments of different peripheral controllers can be loaded to different memories according to the types, functions and characteristics of the peripheral controllers, so that the instruction space expansion is realized on the premise of not increasing the hardware cost, and meanwhile, the convenience of related operation of the peripheral controllers is further improved.

The first peripheral controller and the second peripheral controller refer to different types of peripheral controllers respectively. In particular applications, one or more of the following of the first peripheral controller may be preferred over the second peripheral controller: security, real-time, importance. Therefore, the instruction sections of different types of peripheral controllers can be stored in different memories by means of the characteristics of the peripheral controllers so as to meet the processing requirements of specific peripheral devices in specific applications.

In some examples, the first peripheral controller may include, but is not limited to, one or more of the following: CODEC, HDA, I2S. The second external controller may include, but is not limited to, one or more of the following: UART, I2C, SPI, GMAC, NPU.

In some embodiments, the first instruction segment performs a first operation of the third peripheral controller when executed by the second processor, and the second instruction segment performs a second operation of the third peripheral controller when executed by the second processor.

Thus, different instruction segments of the same peripheral controller can be partially loaded to the first memory, thereby achieving the purpose of expanding instruction space while realizing related operations of the peripheral controller.

The third peripheral controller refers to any peripheral controller, wherein the first operation is related to the first instruction segment, and the second operation is related to the second instruction segment. The first operation is different from the second operation, and the first operation and the second operation may be performed sequentially. For example, the first operation is before, the second operation is after, or the second operation is before, the first operation is after.

For example, the initialization code GAMC belongs to a code with low real-time performance, and the instruction segment in the GAMC initialization code may be loaded into the first memory as the first instruction segment. The other code GAMC belongs to the code with higher real-time performance, and the instruction segment in the other code GAMC can be loaded into the second memory as a second instruction segment.

For example, control codes of peripheral controllers such as NPU and QSPI also belong to codes with low real-time performance, and instruction segments in the control codes can be loaded into the first memory as first instruction segments. The real-time requirements of other codes of the peripheral controllers such as NPU, QSPI and the like are high, and instruction segments in the other codes can be used as second instruction segments to be loaded into the second memory.

In some implementations, the firmware of the second processor may further include: a first data segment corresponding to the first instruction segment and a second data segment corresponding to the second instruction segment. For example, the first data segment may be used to perform an initialization operation of the first peripheral controller and the second data segment may be used to perform an initialization operation of the second peripheral controller. For another example, the first data segment may be used to perform a first operation of a third peripheral controller and the second data segment may be used to perform a second operation of the third peripheral controller.

In some implementations, the system-on-chip may further include a third memory, the third memory being accessible by the second processor. For example, a third memory may be used to store data required by the second processor, see the example of fig. 5 below, which may be, but is not limited to, DCCM. In this embodiment, the method 200 may further include: the second processor performs an initialization operation, which may include: the first data segment is copied to a second predetermined space of the first memory and the second data segment is copied to the third memory. Therefore, the data space expansion of the second processor can be further realized, and the problem that the system on chip cannot perform function expansion due to the space limitation of the third memory is avoided.

In some embodiments, the method 200 may further comprise: the second processor applies for stack space from a second preset space of the first memory to store data generated when the second processor runs the first instruction segment; the second processor applies for stack space from the third memory to store data generated when the second processor runs the second instruction segment. Therefore, after the system on chip is started, the second processor can realize the operation for the first external controller by running the first instruction segment, and can realize the operation for the second external controller by running the second instruction segment.

In some embodiments, prior to step 201, the method 200 may further comprise: the first memory is spatially partitioned to configure a first predetermined space for storing the first instruction segment and a second predetermined space for storing the first data segment.

Specifically, the spatial division of the first predetermined space and the second predetermined space in the first memory may be specified by the base firmware. Specifically, the first predetermined space and the second predetermined space may be configured when the program start-up process is run into the configuration map space. FIG. 3 shows an exemplary diagram of the address space division of DDR. Referring to fig. 3, 1MB is reserved in an 8GB DDR as a memory space of the second processor, which is divided into three sections, i.e., a debug space of 512KB, a data space section of 384KB, and a code space section of 128 KB.

In addition, in the embodiment of the present disclosure, after the boot-up to, for example, general-purpose firmware, the code space, the data space, and the debug space in the foregoing 1MB space may be divided secondarily, so as to ensure that the code space and the data space reserved for the second processor are not accessed after entering the operating system of the first processor.

The instruction segment, the data segment and the like can be loaded into the first memory in a compiling and linking mode so as to realize the expansion of the instruction space and the data space. Specifically, the position of the first instruction segment in the bin file, the position of the second instruction segment in the bin file, the position of the first data segment in the bin file and the position of the second data segment in the bin file can be compiled in the link script, so that each code segment can be accurately copied according to the link script when the system on chip is started.

In order to use multiple segments of instruction space (i.e., instruction space in the second memory and first predetermined space in the first memory), the link script may be tightly controlled at the time of compilation of the second processor code. Initialization code, real-time system, critical driver code, etc. of the second processor may be compiled onto the second memory. Other code may be linked to the specified space of the first memory when the link is compiled.

When compiling the link, offset limitation can be performed on the generated binary file (bin file), 0-128 KB is the second memory space code corresponding to the second processor, and 128-256 KB is the first memory space code corresponding to the second processor, so that the base firmware can distinguish when copying codes from storage media such as FLASH.

Fig. 4 shows a comparative schematic diagram of a conventional binary file (bin) distribution and a binary file (bin) distribution modified by an embodiment of the present disclosure. Referring to fig. 4, the conventional bin distribution is only 128KB, the modified bin file in the embodiment of the present disclosure has 256KB, text, text_sram, init sections in the bin file are all code sections, and the code also includes data, data_ddr sections, which are respectively labeled, so as to distinguish the code sections in different storage media to implement loading for different code sections in the embodiment of the present disclosure.

To avoid conflicts with the first processor's use of the first memory, in some implementations, the system-on-chip startup method 200 of embodiments of the present disclosure may be performed by the first processor in an EL3 secure environment. Among them, EL3 is a security level of security extension of a security zone (trust zone), also called security Monitor. EL3 is the highest privilege level for performing secure boot, secure monitoring, and critical system-level tasks, ensuring the security and stability of the system.

In some embodiments, the method 200 may further comprise: after the first instruction segment and the second instruction segment are loaded, the first processor rewrites the reset value in the first register to trigger the second processor to start. Specifically, the first register refers to a register of the whole second processor, the second processor cannot access the first register, and only the first processor can access the first register under the condition that the security authority meets the requirement. The first register is provided with a reset value, wherein a reset value of 0 represents release, and a reset value of 1 represents reset. When the first processor rewrites the reset value in the first register from "1" to "0", the second processor will be triggered to self-start. Thus, the second processor may be controlled to self-start by a reset value in the register after the instruction segment is loaded.

In embodiments of the present disclosure, the first processor may perform the aforementioned system-on-chip booting method by running the base firmware preloaded on the system-on-chip. Wherein the base firmware is operable to implement a boot operation for the first processor, the second processor. Specifically, after the SOC is powered up, the first processor runs to the base firmware to perform the following processing: different portions of the firmware of the second processor are copied from the FLASH storage medium to predetermined spaces of the second memory and the first memory. After the second processor is started, the second processor core moves the data indicated by the data segment to the third memory, and applies for a stack space in the third memory space. If expansion of the data space is desired, the second processor core may move the data segment to a predetermined data space (i.e., a second predetermined space) of the first memory and apply for a stack space in the predetermined data space of the first memory to store the data.

After the method 200, when the operation of the first peripheral controller needs to be performed, the second processor may read and execute the first instruction segment and the first data segment from the first predetermined space of the first memory. When the operation of the second external controller needs to be performed, the second instruction segment and the second data segment can be read from the second memory by the second processor and run. Or the second processor may read and execute the first instruction segment and the first data segment from the first predetermined space of the first memory when the first operation of the third peripheral controller needs to be performed. When the second operation of the third peripheral controller needs to be performed, the second processor may read and execute the first instruction segment and the first data segment from the first predetermined space of the first memory.

Fig. 5 illustrates a schematic implementation process of a system-on-chip start-up method according to an embodiment of the present disclosure. In the example of fig. 5, codes of UART, I2C, SPI are stored in 0-128 KB of FLASH, i.e., base+0 KB-base+128 KB in fig. 5, and codes of codec, I S, iop _control are stored in 128-256 KB of FLASH, i.e., base+128 KB-base+256 KB in fig. 5. Each code comprises a text segment and a data segment, wherein the text segment is the previous instruction segment, the data segment is the data segment, the text_ddr segment is the previous first instruction segment, the data_ddr segment is the previous first data segment, the data_sram segment is the previous second instruction segment, and the text_sram segment is the previous second data segment. The starting method of the embodiment of the disclosure comprises the following steps:

First, a first processor initializes copy firmware, including: namely ① UART, code (data_sram segment and text_sram segment) of I2C, SPI are loaded into SRAM code space 0-128 KB of SRAM, and the SRAM also has a Shared Memory (SHMEM) data space for storing SHMEM data; ② The codes (text_ddr segment and data_ddr segment) of the CODEC and the I S, iop _Console are loaded into DDR code space in 1M space reserved in the DDR, namely data space, data special space and the like are reserved in the DDR.

Second, the second processor operates to copy and apply for the stack, including: ③ Copying the data segment (data_ddr segment) in the code of the CODEC and the I S, iop _Console in the DDR reserved space to the data space 0-64 KB of the DCCM; and copying the data segment (data_sram segment) in the codes of UART and I2C, SPI in the SRMA code space to the data space 0-64 KB of the DCCM, and applying for stack from the reserved data space of DDR. And, the data segment in the SRAM code space in ④ SRAM and the data segment in the DDR code space can also be copied to the reserved data space of DDR, and the stack can also be applied from the reserved data space of DDR.

From the foregoing, it can be seen that, in the method 200 of the embodiment of the present disclosure, after the system is powered on, a part of codes in the firmware of the second processor is loaded into the second memory, after the initialization of the first memory is completed, another part of codes in the firmware of the second processor is continuously loaded into the corresponding space of the first memory, and space expansion of the firmware functions and instruction codes of the second processor is realized by using the space of the first memory, so that the firmware functions and instruction codes of the second processor in the system on chip can be continuously expanded without increasing the area and cost of the system on chip, and the performance, functions and the like of the second processor can better meet the requirements of practical applications.

Fig. 6 shows a flowchart of a peripheral management method of a system on chip according to an embodiment of the present disclosure. Referring to fig. 6, a peripheral management method 600 of a system on chip may include the steps of:

Step 601, in response to a request initiated by a first processor for a first peripheral controller, a second processor initiates an instruction fetch request for a first predetermined space of a first memory;

Step 602, the second processor receives a first instruction returned by the first memory in response to the instruction fetching request;

Step 603, the second processor executes the first instruction to obtain first data corresponding to the first instruction from the first memory;

in step 604, the second processor sends a data access request to the first memory using the first instruction and the first data corresponding thereto, so that the first processor can obtain the data of the first peripheral controller requested by the first processor.

The method 600 of the embodiment of the present disclosure may further include: the second processor receives second data returned by the first memory in response to the data access request; and the second processor analyzes the second data to obtain third data, and writes the third data back to the first memory so that the first processor can acquire the third data.

If the core of the second processor is designed for a 32bit instruction and data address request, address translation is required to access a 40bit DDR. Wherein 20 bits represent 1MB address space, 20 bits higher complements 20 bits pre-configured in registers on the bus network, resulting in 40 bits. Thus, after the mapping relationship is configured, the DDR space accessed by the second processor can only be 1MB of space of the mapping.

The method 600 of the embodiment of the present disclosure may further include: after the second processor initiates the instruction fetching request to the first predetermined space of the first memory, the instruction fetching request is address-converted by a bus network (for example, NCC in fig. 7 below) to which the second processor belongs based on the address mapping relationship in the second register, and then forwarded to the first memory.

The second processor sends a data access request to the first memory by using the first instruction and the corresponding first data, and the second processor comprises: the second processor initiates a data access request aiming at the first memory by utilizing the first instruction and the corresponding first data; and converting the address of the data access request based on the address mapping relation in the second register, and forwarding the data access request to the first memory after passing through a bus network to which the second processor belongs.

Fig. 7 shows a network architecture schematic of a system on chip. In fig. 7, DDR is an example of the first memory, SRAM is an example of the second memory, and DCCM is an example of the third memory. The FLASH storage medium is stored with firmware of a second processor, the first processor, the FLASH storage medium and the DDR are connected to the NOC network in a hanging mode, the second processor, the SRAM and the DCCM are connected to the NCC network in a hanging mode, the NOC network and the NCC network are communicated, interaction between the second processor and the DDR is required to pass through the NCC network and the NOC network, interaction between the second processor and the FLASH storage medium is required to pass through the NCC network and the NOC network, interaction between the second processor and the SRAM and the DCCM is required to pass through the NCC network, and interaction between the first processor and the DDR is required to pass through the NOC network.

That is, the second processor accesses the DDR through the NOC network, and the address space of the NOC network is 40 bits (bits), so registers can be configured in the EL3 environment in advance to confirm that the mapping space DDR is 20 bits higher, and 20 bits lower represents 1MB space.

A Network on Chip (NoC) is an architecture based on-Chip Network interconnection, and is used for connecting each functional module inside an integrated circuit Chip (such as a multi-core processor, an FPGA, etc.) so as to realize efficient communication and data transmission. NoC is used as an advanced on-chip network interconnection technology, provides an efficient communication architecture for integrated circuit systems, and is applied to systems such as multi-core processors.

Lightweight network communication (NCC, LIGHTWEIGHT NETWORK COMMUNICATION) refers to a network communication scheme designed for resource-constrained devices (e.g., internet of things devices, embedded systems, etc.), and is intended to enable efficient and compact communication in a resource-constrained environment. Lightweight network communication is a network communication scheme specially designed for resource-constrained devices, and aims to provide an efficient, concise and low-power consumption communication solution, and is suitable for various scenes such as the Internet of things and embedded systems.

The NCC is used to pass internal data of the second processor across the NOC network. The second processor accesses the SRAM only through the NCC network, so the second processor accesses the SRAM without performing a bit-filling operation. The second processor accesses the DDR and needs to go through the NOC network, because the address of the NOC network is 40 bits, the address of the NCC network is 22 bits, and the address specifications of the two networks are different, the second processor needs to perform address conversion, namely bit filling operation when accessing the DDR.

The second processor accesses the DCCM without going through a network, and the interface of the second processor core can directly reach the DCCM to directly return data.

When the first processor accesses the SRAM, only data read-write requests are needed, and no instruction requests are needed.

The following exemplarily describes a specific implementation of the embodiment of the present disclosure with DDR as a first memory, SRAM as a second memory, and DCCM as a third memory.

An exemplary implementation flow of the system on chip starting method and the peripheral management method thereof provided by the embodiments of the present disclosure may include the following steps 1 to 21:

Step 1, a first processor runs basic firmware, and DDR initialization is completed;

Step 2, the first processor configures the accessed page table mapping space under the EL3 security environment to determine the DDR space division.

Step 3, the first processor configures "the second processor maps to the high 20bit address of DDR" in the EL3 secure environment.

Step 4, the first processor copies a second code in the FLASH to the SRAM under the EL3 security environment, wherein the second code comprises the second instruction segment and the second data segment;

And 5, the first processor copies the first code in the second processor firmware in the FLASH to the reserved code space of the DDR under the EL3 safety environment.

And 6, the first processor confirms that the firmware copy of the second processor is completed.

Step 7, the first processor writes the first register under the EL3 security environment to release the reset of the second processor, and the second processor is triggered to be started.

And 8, the second processor runs initialization codes, copies the first data segment to the reserved data space of the DDR, and copies the second data segment to the DCCM.

Step 9, the second processor applies for stack space from the reserved data space of DCCM and/or DDR.

Step 10, the second processor writes back the start success flag to the second register.

And step 11, after the first processor receives the start completion mark, continuing to run the subsequent codes.

In step 12, the first processor runs to general purpose firmware (e.g., UEFI/UBOOT/…, etc.), configures memory attributes of 1MB, with the first 512KB being reserved space and the second 512KB being readable and writable data space. The first processor will not have access to the first 512KB.

Step 13, the first processor initiates a driving request to trigger the second processor to use the code of the DDR space, wherein the DDR is the first memory;

Step 14, the second processor receives the drive request of the first processor, and the second processor core initiates an instruction fetching request of the DDR address space;

Step 15, the NCC network converts the DDR address in the instruction fetch request initiated by the second processor, adds the high 20 bits of the address in the register to enable the DDR address to meet the address specification of the NOC network, and forwards the instruction fetch request to the DDR through the NOC;

in step 16, the DDR returns an 8 byte aligned instruction according to the instruction fetch request of the second processor core.

Step 17, the second processor executes the fetch instruction from the DDR.

Step 18, the second processor core analyzes the 8-byte alignment instruction returned by the DDR, determines that the data stored in the DDR needs to be retrieved, and initiates a data access request to the DDR;

in step 19, the ncc network translates the address in the data access request, adds the high 20 bits of the address in the register, and forwards the data access request to the DDR.

In step 20, the DDR returns 8-byte aligned data in response to the data access request from the second processor core.

In step 21, the second processor parses the 8-byte aligned data returned by the DDR and writes back to the DDR.

After the silicon, the code amount is continuously increased in the scenes of function debugging, client application and the like. The prior art can only perform functional expansion on a limited space, and when the limit is reached, the expansion of the second processor application is limited. The above method of the embodiment of the disclosure solves the above problem in the post-silicon application of the second processor, and expands the instruction space and the data space of the second processor based on the space of the first memory in the system on chip, so that the firmware function and the instruction code of the second processor can be continuously expanded without increasing the area and the cost, and the whole function expansion can be realized for a small-sized system.

The foregoing describes specific embodiments of the present disclosure. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

Additionally, the disclosed embodiments also provide a computer-readable storage medium having stored thereon a computer program comprising instructions which, when executed by one or more processors of a computing device, perform the steps of the method described in the method embodiments previously described.

Embodiments of the present disclosure also provide an electronic device including the aforementioned system-on-chip 100.

An electronic device according to an embodiment of the present disclosure is further provided, as shown in fig. 8, where the electronic device 800 includes one or more processors 801, and further includes a memory 802 storing one or more programs, and the program units corresponding to each unit in the method flows and/or the apparatus shown in the foregoing embodiments of the present disclosure are implemented by the one or more processors 801.

The various components are interconnected using different buses and may be mounted on a common motherboard or in other manners as desired. The processor 801 may process instructions executing within the electronic device, including instructions stored in or on memory to display graphical information of a user interface on an external input/output device, such as a display device coupled to the interface. In other embodiments, multiple processors and/or multiple buses may be used, if desired, along with multiple memories and multiple memories.

Processor 801 may include one or more single-core processors or multi-core processors. Processor 801 may include any combination of general-purpose processors or special-purpose processors (e.g., image processors, application processor baseband processors, etc.).

Memory 802 is a computer-readable storage medium provided by the present disclosure and may be used to store non-transitory software programs, non-transitory computer-executable programs, and units, such as program instructions/units corresponding to the method shown in fig. 2 in the embodiments of the present disclosure. The processor 801 executes programs, instructions and units corresponding to the method such as shown in fig. 2 in the above-described method embodiment by running non-transitory software programs, instructions and units stored in the memory 802.

The electronic device 800 may further include: an input device 803 and an output device 804. The processor 801, memory 802, input devices 803, and output devices 804 may be connected by a bus or other means, for example in fig. 8.

The input device 803 may receive input digital or character information and generate signal inputs related to user settings and function control associated with the frequency modulation device, such as a touch screen, keypad, mouse, track pad, touch pad, pointer stick, one or more mouse buttons, track ball, joystick, etc. The output device 804 may include a display apparatus, auxiliary lighting devices (e.g., LEDs), and haptic feedback devices (e.g., vibration motors), among others. The display device may include, but is not limited to, a Liquid Crystal Display (LCD), a Light Emitting Diode (LED) display, and a plasma display. In some implementations, the display device may be a touch screen.

The above-described programs (also referred to as software, software applications, or code) include machine instructions of a programmable processor, and these computing programs may be implemented in an object-oriented programming language, assembly, or machine language.

With the development of time and technology, the media has a wider meaning, and the propagation path of the computer program is not limited to a tangible medium any more, and can be directly downloaded from a network, etc. Any combination of one or more computer readable storage media may be employed. The computer readable storage medium can be, for example, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium would include the following: portable computer diskette, hard disk, random Access Memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disc read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination of the foregoing. In this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

The foregoing has outlined rather broadly the more detailed description of the present disclosure, and the detailed description of the principles and embodiments of the present disclosure that follows may be had by applying specific examples, which are presented herein to facilitate the understanding of the methods of the present disclosure and their core concepts; also, changes in the specific embodiments and in the application scope will occur to those skilled in the art in light of the teaching of this disclosure. In view of the foregoing, this description should not be construed as limiting the disclosure.

The foregoing description of the preferred embodiments of the present disclosure is not intended to limit the disclosure, but rather to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the present disclosure.

Claims

1. A method for starting a system on a chip, wherein the system on a chip comprises a first processor, a second processor, a first memory and a second memory, the first processor and the second processor can access the first memory, and the second processor can access the second memory;

The starting method of the system on chip comprises the following steps: after power-on, the first processor loads the first instruction segment to a first preset space of a first memory for the second processor to use, and loads the second instruction segment to the second memory for the second processor to use;

wherein the first instruction segment and the second instruction segment are from firmware of the second processor.

2. The method of claim 1, wherein the first instruction segment, when executed by the second processor, performs an operation of a first peripheral controller, and the second instruction segment, when executed by the second processor, performs an operation of a second peripheral controller.

3. The method of claim 1, wherein the step of determining the position of the substrate comprises,

The first peripheral controller includes one or more of: CODEC, I2S;

The second external controller includes one or more of the following: UART, I2C, SPI, HDA, GMAC, NPU.

4. The method of claim 1, wherein the first instruction segment, when executed by a second processor, performs a first operation of a third peripheral controller, and wherein the second instruction segment, when executed by the second processor, performs a second operation of the third peripheral controller.

5. The method of claim 1, wherein the step of determining the position of the substrate comprises,

The firmware of the second processor further includes: a first data segment corresponding to the first instruction segment and a second data segment corresponding to the second instruction segment;

The system on a chip further includes a third memory, the third memory being accessible by the second processor;

The method further comprises the steps of: the second processor performs an initialization operation, the initialization operation comprising: copying the first data segment to a second predetermined space of the first memory and copying the second data segment to the third memory.

6. The method of claim 5, wherein the method further comprises:

a second processor applies for stack space from a second predetermined space of the first memory to store data generated when the second processor runs the first instruction segment;

The second processor applies for stack space from the third memory to store data generated when the second processor runs the second instruction segment.

7. The method as recited in claim 4, further comprising:

Before loading the first instruction segment and the second instruction segment, the first memory is spatially partitioned to configure a first predetermined space for storing the first instruction segment and a second predetermined space for storing a first data segment.

8. The method of claim 1, wherein the first processor runs base firmware pre-loaded in a system-on-chip to perform a boot method of the system-on-chip.

9. The method of claim 1, wherein the method of booting the system on a chip is performed by the first processor in an EL3 secure environment.

10. The method according to claim 1, wherein the method further comprises:

after the first instruction segment and the second instruction segment are loaded, the first processor rewrites the reset value in the first register to trigger the second processor to start.

11. A peripheral management method for a system on a chip, comprising:

12. The method as recited in claim 11, further comprising:

a second processor receives second data returned by the first memory in response to the data access request;

the second processor parses the second data to obtain third data, and writes the third data back to the first memory so that the first processor can acquire the third data.

13. The method as recited in claim 11, further comprising:

After the second processor initiates an instruction fetching request for a first preset space of the first memory, the instruction fetching request is subjected to address conversion by a bus network to which the second processor belongs based on an address mapping relation in a second register and then is forwarded to the first memory.

14. The method of claim 11, wherein the second processor sending a data access request to the first memory using the first instruction and its corresponding first data, comprising:

The second processor core initiates a data access request aiming at the first memory by utilizing the first instruction and the corresponding first data; and

And after address conversion is carried out on the data access request based on the address mapping relation in the second register, the data access request is forwarded to the first memory through a bus network to which the second processor belongs.

15. A system on a chip, comprising: a first processor, a second processor, a first memory, and a second memory, each of the first processor and the second processor having access to the first memory, the second processor having access to the second memory, the first processor being communicable with the second processor;

the first processor is configured to load the first instruction segment into a first predetermined space of a first memory for use by the second processor after power-up, and load the second instruction segment into the second memory for use by the second processor;

16. The system on a chip of claim 15, wherein the system on a chip comprises a first bus and a second bus; the first memory and the first processor are connected to a first bus, the second memory and the second processor are connected to a second bus, and the second bus is hung on the first bus.

17. The system on a chip of claim 15, wherein the first memory is provided with: a first instruction interface and a first data read-write interface for a core of the first processor; and a second instruction interface and a second data read-write interface for a core of the second processor.

18. An electronic device, comprising: the system on a chip of any one of claims 15-17.

19. A computer readable storage medium storing a program comprising instructions which, when executed by a processor, cause the processor to perform the method of any one of claims 1 to 10 or the method of any one of claims 11 to 14.