CN119003252A

CN119003252A - Hardware system detection method, device, equipment and storage medium

Info

Publication number: CN119003252A
Application number: CN202410875900.4A
Authority: CN
Inventors: 翟昌英; 吴正中; 唐才荣; 张辉; 刘宝东; 邓能文; 王晓东
Original assignee: Beijing Urban Construction Intelligent Control Technology Co ltd
Current assignee: Beijing Urban Construction Intelligent Control Technology Co ltd
Priority date: 2024-07-02
Filing date: 2024-07-02
Publication date: 2024-11-22

Abstract

The present invention relates to the technical field of system testing, and provides a hardware system detection method, device, equipment and storage medium. The method is applied to a field programmable logic gate array in a hardware system detection system, and the hardware system detection system includes a field programmable logic gate array and a processor. The method includes: receiving an original input signal; determining an optional value of a self-test signal based on the original input signal; determining at least one target signal combination according to the optional values of the original input signal and the self-test signal, and determining a target operation result of the field programmable logic gate array according to each target signal combination; sending the target operation result to the processor, wherein the target operation result is used for the processor to determine whether there is an abnormality in the function of the hardware system according to the target operation result. The present invention improves the accuracy of hardware system detection.

Description

Hardware system detection method, device, equipment and storage medium

Technical Field

The present invention relates to the field of system testing technologies, and in particular, to a method, an apparatus, a device, and a storage medium for detecting a hardware system.

Background

The field programmable gate array (Field Programmable GATE ARRAY, FPGA) is an integrated circuit with programmable characteristics, has the characteristics of high performance, reconfigurability, concurrent execution, short development period and the like, can realize the iteration of an algorithm with lower cost due to the characteristics of high flexibility and expandability, can better realize the operation, control and upgrading functions of a new scene, is called a universal chip in the chip field, and is widely applied to the fields of industrial control, aerospace, network communication, consumer electronics, data centers, automotive electronics and artificial intelligence.

The requirements on the system reliability, especially the hardware system reliability, are higher and higher in various fields nowadays, however, the reliability of the hardware system based on the FPGA is greatly influenced by factors such as temperature, humidity, electromagnetism, vibration and the like. Therefore, how to detect the reliability of FPGA hardware systems in different environments is a critical issue.

In the prior art, a self-checking method for detecting an FPGA hardware system mainly detects and displays a state through a light emitting diode (LIGHT EMITTING diode) running light, however, a detection result of the detection method of the led running light only can indicate whether the hardware system is working, but whether the internal function operation is normal or not is not judged, so that the accuracy of detecting the hardware system is poor.

Disclosure of Invention

Aiming at the problems in the prior art, the invention provides a hardware system detection method, a device, equipment and a storage medium, which improves the accuracy of hardware system detection.

In a first aspect, the present invention provides a method for detecting a hardware system, where the method is applied to a field programmable gate array in a hardware system detection system, and the hardware system detection system includes the field programmable gate array and a processor, and the method includes:

receiving an original input signal;

determining an optional value of a self-test signal based on the original input signal;

Determining at least one target signal combination according to the selectable values of the original input signal and the self-checking signal, and determining a target operation result of the field programmable gate array according to each target signal combination;

Sending the target operation result to the processor; and the target operation result is used for the processor to determine whether the function of the hardware system is abnormal according to the target operation result.

Optionally, the field programmable gate array includes a state machine, a first functional unit, and a second functional unit; the first functional unit and the second functional unit are parallel functional units, and the same target operation is executed in the first functional unit and the second functional unit; the number of the selectable values of the self-checking signal is a preset number; each target signal combination comprises a first input signal input into the first functional unit and a second input signal input into the second functional unit; said determining at least one target signal combination from selectable values of said original input signal and said self-test signal, comprising:

determining the original input signal as the first input signal;

determining the second input signal according to a preset number of selectable values of the self-checking signals;

Combining the first input signal and the second input signal by using the state machine to obtain the at least one target signal combination; and/or the number of the groups of groups,

Determining the first input signal according to a preset number of selectable values of the self-checking signals;

determining the original input signal as the second input signal;

And combining the first input signal and the second input signal by using the state machine to obtain the at least one target signal combination.

Optionally, the determining the target operation result of the field programmable gate array according to each target signal combination includes:

For each target signal combination, executing the target operation on the first input signals in each target signal combination by using the first functional unit to obtain a first operation result of the first functional unit corresponding to each target signal combination;

Executing the target operation on the second input signals in each target signal combination by using the second functional unit to obtain a second operation result of the second functional unit corresponding to each target signal combination;

And combining the first operation result of the first functional unit and the second operation result of the second functional unit corresponding to each target signal to determine the target operation result of the field programmable gate array.

Optionally, the sending the target operation result to the processor includes:

And sending the target operation result, each target signal combination, a signal type mark of the first input signal in each target signal combination and a signal type mark of the second input signal in each target signal combination to the processor.

In a second aspect, the present invention also provides a hardware system detection system, where the hardware system detection system includes a field programmable gate array and a processor;

The field programmable gate array is used for receiving an original input signal; determining an optional value of a self-test signal based on the original input signal; determining at least one target signal combination according to the selectable values of the original input signal and the self-checking signal, and determining a target operation result of the field programmable gate array according to each target signal combination; sending the target operation result to the processor;

and the processor is used for determining whether the function of the hardware system is abnormal according to the target operation result.

Optionally, the field programmable gate array includes a state machine, a first functional unit, and a second functional unit; the first functional unit and the second functional unit are parallel functional units, and the same target operation is executed in the first functional unit and the second functional unit; the target signal combinations are determined by the state machine, and each target signal combination comprises a first input signal input into the first functional unit and a second input signal input into the second functional unit; each target operation result is determined based on a first operation result of the first functional unit and a second operation result of the second functional unit corresponding to each target signal combination;

optionally, the processor is specifically configured to:

For any one of the target signal combinations, comparing a first operation result of the first functional unit with a preset operation result to obtain a first comparison result when the first input signal in the target signal combination is determined according to the preset number of selectable values of the self-checking signals; the preset operation result is determined by a target operation tool according to the preset number of selectable values of the self-checking signals;

determining whether the function of the hardware system is abnormal or not according to a first comparison result;

comparing a second operation result of the second functional unit with a preset operation result to obtain a second comparison result under the condition that the second input signal in the target signal combination is determined according to the preset number of selectable values of the self-checking signals;

And determining whether the function of the hardware system is abnormal according to the second comparison result.

In a third aspect, the present invention also provides a hardware system detection apparatus, which is applied to a field programmable gate array in a hardware system detection system, where the hardware system detection system includes the field programmable gate array and a processor, and the apparatus includes:

The receiving module is used for receiving an original input signal; determining an optional value of a self-test signal based on the original input signal;

The determining module is used for determining at least one target signal combination according to the selectable values of the original input signal and the self-checking signal, and determining a target operation result of the field programmable gate array according to each target signal combination;

the sending module is used for sending the target operation result to the processor; and the target operation result is used for the processor to determine whether the function of the hardware system is abnormal according to the target operation result.

In a fourth aspect, the present invention further provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor, where the processor implements any one of the hardware system detection methods described above when executing the program.

In a fifth aspect, the present invention also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements a hardware system detection method as described in any of the above.

In a sixth aspect, the present invention also provides a computer program product comprising a computer program which, when executed by a processor, implements a hardware system detection method as described in any of the above.

The invention provides a hardware system detection method, a device, equipment and a storage medium, wherein the method is applied to a field programmable gate array in a hardware system detection system, the hardware system detection system comprises the field programmable gate array and a processor, and firstly, an original input signal is received, and the selectable value of a self-checking signal is determined based on the original input signal; then, according to the original input signal and the optional value of the self-checking signal, at least one target signal combination is determined, and according to each target signal combination, a target operation result of the field programmable gate array is determined; and further, sending the target operation result to the processor, wherein the target operation result is used for the processor to determine whether the function of the hardware system is abnormal according to the target operation result.

According to the invention, the field programmable gate array determines at least one target signal combination according to the selectable values of the original input signal and the self-checking signal, and determines the target operation result based on the target signal combination, and further, the processor determines whether the function of the hardware system is abnormal or not according to the target operation result after receiving the target operation result, thereby realizing the real-time detection of whether the function of the hardware system is normal or not and improving the detection accuracy of the hardware system.

Drawings

In order to more clearly illustrate the invention or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic flow chart of a hardware system detection method provided by the invention.

Fig. 2 is a schematic diagram of a hardware system detection system according to the present invention.

Fig. 3 is a schematic diagram showing the effect of the target signal combination provided by the present invention.

Fig. 4 is a schematic diagram of a hardware system detection method provided by the present invention.

FIG. 5 is a schematic diagram of a hardware system detection system according to the second embodiment of the present invention.

Fig. 6 is a schematic structural diagram of a hardware system detection device provided by the invention.

Fig. 7 is a schematic structural diagram of an electronic device provided by the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The hardware system detection method, apparatus, device and storage medium of the present invention are described below in conjunction with fig. 1-7.

Fig. 1 is a schematic flow chart of a hardware system detection method provided by the invention, the method is applied to a field programmable gate array in a hardware system detection system, the hardware system detection system comprises the field programmable gate array and a processor, and as shown in fig. 1, the method comprises steps 101-104.

Step 101, receiving an original input signal;

Specifically, the execution body of the present invention is a Field Programmable Gate Array (FPGA) in a hardware system detection system, and fig. 2 is a schematic structural diagram of the hardware system detection system provided by the present invention, where the hardware system detection system 200 includes a field programmable gate array 210 and a processor 220, the programmable gate array 210 receives an original input signal, and the programmable gate array 210 and the processor control and state interactively.

The method comprises the following steps: first, the field programmable gate array receives an original input signal, where the original input signal may be an analog quantity such as a sampled hardware system voltage, current, etc., or may be a signal such as a data stream, etc.

Step 102, determining an optional value of the self-checking signal based on the original input signal;

Specifically, the selectable value of the self-checking signal is determined based on the original input signal, for example, a typical value of the original input signal sig is selected as the selectable value of the self-checking signal, and the present solution details taking two typical values as examples, where the two typical values are a0 and a1 respectively.

Step 103, determining at least one target signal combination according to the selectable values of the original input signal and the self-checking signal, and determining a target operation result of the field programmable gate array according to each target signal combination;

specifically, after receiving the original input signal and determining the selectable values of the self-test signal, the field programmable gate array FPGA determines at least one target signal combination based on the original input signal, it being understood that the target signal combination is used to characterize how the selectable values of the original input signal and the self-test signal are input into the functional unit, which is used to perform specific processing on the input signal, such as algorithmic processing, data parsing, etc. to perform target operations. For example, the target signal combination comprises a first input signal and a second input signal, the first input signal being determined based on the original input signal, the second input signal being determined based on a selectable value of the self-test signal, or the first input signal being determined based on a selectable value of the self-test signal, the second input signal being determined based on the original input signal.

After at least one target signal combination is determined, a target operation is performed on each target signal combination to obtain a target operation result of each target signal combination. Further, the target operation result of each target signal combination is determined as the target operation result of the field programmable gate array FPGA.

104, Sending a target operation result to a processor; the target operation result is used for the processor to determine whether the function of the hardware system is abnormal according to the target operation result.

Specifically, the field programmable gate array FPGA transmits the target operation result to the processor after determining the target operation result.

And after the processor receives the target operation result, the target operation result is used for the processor to judge whether the function of the hardware system is abnormal or not based on the target operation result. The method includes comparing a target operation result with a preset comparison result, determining whether the function of the hardware system is abnormal, determining that the function of the hardware system is normal when the target operation result is consistent with the preset comparison result, and determining that the function of the hardware system is abnormal when the target operation result is inconsistent with the preset comparison result.

In the method provided by the embodiment, the method is applied to a field programmable gate array in a hardware system detection system, the hardware system detection system comprises the field programmable gate array and a processor, firstly, an original input signal is received, and an optional value of a self-checking signal is determined based on the original input signal; then, according to the original input signal and the optional value of the self-checking signal, at least one target signal combination is determined, and according to each target signal combination, a target operation result of the field programmable gate array is determined; and further, sending the target operation result to the processor, wherein the target operation result is used for the processor to determine whether the function of the hardware system is abnormal according to the target operation result.

Optionally, the field programmable gate array comprises a state machine, a first functional unit and a second functional unit; the first functional unit and the second functional unit are parallel functional units, and the same target operation is executed in the first functional unit and the second functional unit; the number of the selectable values of the self-checking signals is a preset number; each target signal combination comprises a first input signal input into a first functional unit and a second input signal input into a second functional unit; determining at least one target signal combination from the raw input signal and the selectable values of the self-test signal, comprising:

determining an original input signal as a first input signal;

determining a second input signal according to the selectable values of the preset number of self-checking signals;

Combining the first input signal and the second input signal by using a state machine to obtain at least one target signal combination; and/or the number of the groups of groups,

Determining a first input signal according to the selectable values of the preset number of self-checking signals;

determining the original input signal as a second input signal;

and combining the first input signal and the second input signal by using a state machine to obtain at least one target signal combination.

Specifically, in some embodiments, a field programmable gate array FPGA includes a state machine, a first functional unit, and a second functional unit. The state machine is used for switching the original input signal and the self-checking signal so as to output different target signals to the functional unit.

Further, it can be understood that the functional unit is a module that performs a specific process on an original input signal when the field programmable gate array FPGA is operating normally, where, for example, the functional unit of the field programmable gate array FPGA is instantiated twice as a first functional unit and a second functional unit, respectively, the first functional unit and the second functional unit are parallel functional units, and the first functional unit and the second functional unit perform the same target operation, or perform the same data processing. That is, based on the operational parallelism of the FPGA, the two functional units are running simultaneously and are functionally identical, except that the input signals are different.

Further, the number of selectable values of the self-test signal input to the state machine is a preset number, for example, two typical values a0, a1 of the original input signal are taken, and for example, two typical values a0, a1, a2, a3 of the original input signal are taken. After the state machine receives the self-checking signal and the original input signal, the self-checking signal and the original input signal are switched to obtain different target signal combinations, namely, different states of the state machine are obtained through switching. Each target signal combination includes a first input signal input to the first functional unit and a second input signal input to the second functional unit.

The following describes a process of determining each target signal combination according to the original input signal and the optional values of the self-test signal, taking the self-test signal as two typical values a0, a1 of the original input signal as an example:

Firstly, determining an original input signal sig as a first input signal; then, according to the preset number of selectable values of the self-checking signals, the second input signal is determined, for example, the selectable values of the self-checking signals are two, and are respectively two typical values a0 and a1 of the original input signal, and then the second input signal is a0 and a1. And combining the first input signal and the second input signal by using a state machine to obtain at least one target signal combination.

Illustratively, target signal combination 1: "first input signal: an original input signal sig; a second input signal: a0"; target signal combination 2: "first input signal: an original input signal sig; a second input signal: a1% >.

And/or, determining the target signal combination as follows:

First, a first input signal is determined according to a preset number of selectable values of the self-test signals. For example, the selectable values of the self-test signal are two, respectively two typical values a0, a1 of the original input signal, and the second input signal is a0, a1. Then, the original input signal sig is determined as the second input signal. Further, the first input signal and the second input signal are combined by a state machine to obtain at least one target signal combination.

Illustratively, target signal combination 3: "first input signal: a0; a second input signal: an original input signal sig "; target signal combination 4: "first input signal: a1; a second input signal: the original input signal sig. "

Further, after the first input signal and the second input signal in the target signal combination are determined, the first input signal is input to the first functional unit, the second input signal is input to the second functional unit, and specific target operations are respectively executed.

Fig. 3 is a schematic diagram illustrating the effect of the combination of the target signals provided by the present invention, and as shown in fig. 3, the combination includes four target signal combinations s0, s1, s2, s3, that is, four states of the state machine are s0, s1, s2, s3, respectively. Wherein, the four target signals are combined as follows:

s0：in1=sig，in2=a0；

s1：in1=a0，in2=sig；

s2：in1=a1，in2=sig；

s3：in1=sig，in2=a1。

Wherein in1 represents a first input signal, and is subsequently input to the first functional unit to perform target operation, so as to obtain a first operation result, in2 represents a second input signal, and is subsequently input to the second functional unit to perform target operation, so as to obtain a second operation result.

Note that, the state machine switching conditions 0 to 3 may be periodically and automatically switched, or may be switched by receiving an external command, which is not limited in this embodiment.

In the method provided by the embodiment, the field programmable gate array includes a state machine, a first functional unit and a second functional unit, where the state machine is used to switch states, i.e., target signal combinations, so that the functional units are used to perform target operations on input signals, and the first functional unit and the second functional unit are parallel functional units, and each target signal combination includes a first input signal input into the first functional unit and a second input signal input into the second functional unit. According to the optional values of the original input signal and the self-checking signal, at least one target signal combination can be determined, so that different target signal combinations are input to the functional unit to execute specific target operation, and then a target operation result is sent to the processor, so that the processor judges whether the function of the hardware system based on the field programmable gate array is abnormal or not based on the target operation result, and the accuracy of hardware system detection is improved.

Optionally, determining the target operation result of the field programmable gate array according to each target signal combination includes:

For each target signal combination, performing target operation on a first input signal in each target signal combination by using a first functional unit to obtain a first operation result of the first functional unit corresponding to each target signal combination;

Performing target operation on a second input signal in each target signal combination by using a second functional unit to obtain a second operation result of the second functional unit corresponding to each target signal combination;

and combining the first operation result of the corresponding first functional unit and the second operation result of the corresponding second functional unit by each target signal to determine the target operation result of the field programmable gate array.

Specifically, after each target signal combination is obtained, a first input signal in each target signal combination is input to a first functional unit, a second input signal is input to a second functional unit, the first functional unit and the second functional unit are used to process the respective input signals, and in some embodiments, a process of determining a target operation result of the field programmable gate array in step 102 is as follows:

Firstly, aiming at each target signal combination, a first functional unit is utilized to execute target operation on a first input signal in each target signal combination, and a first operation result of the first functional unit corresponding to each target signal combination is obtained; and simultaneously, executing target operation on the second input signals in each target signal combination by using the second functional units to obtain a second operation result of the second functional units corresponding to each target signal combination. It will be appreciated that, since the selectable value of the self-test signal is a predetermined typical value of the original input signal, the result of the self-test signal passing through the functional unit is known and determined under the condition that the hardware system is normal in function, the comparison result of the self-test signal passing through the functional unit is calculated, for example, by a calculation tool matlab, and the comparison result of the self-test signal passing through the functional unit and the actual calculation result of the self-test signal are used as a comparison group to determine whether the hardware system is abnormal in function.

Further, the first operation result of the corresponding first functional unit and the second operation result of the corresponding second functional unit are combined by each target signal, and the target operation result of the field programmable gate array is determined.

In an exemplary embodiment, when the first input signal is a self-checking signal, the first operation result of the first functional unit is compared with the comparison result of the self-checking signal passing through the functional unit, whether the first operation result and the comparison result are consistent is determined, if the first operation result and the comparison result are consistent, the hardware system is determined to be normal in function, and if the first operation result and the comparison result are inconsistent, the hardware system is determined to be abnormal in function.

And under the condition that the second input signal is a self-checking signal, comparing a second operation result of the second functional unit with a comparison result of the self-checking signal passing through the functional unit, judging whether the second operation result is consistent with the comparison result of the self-checking signal, if so, judging that the function of the hardware system is normal, and if not, judging that the function of the hardware system is abnormal.

Fig. 4 is a schematic diagram of a hardware system detection method provided by the present invention, which shows a process of determining a target operation result by a field programmable gate array, and as shown in fig. 4, the method includes:

Firstly, inputting a selectable value a of a self-checking signal and an original input signal sig into a state machine of a programmable gate array (FPGA);

Then, the state machine switches the original input signal sig and the optional value a of the self-checking signal, outputs different target signal combinations to the functional units, wherein the target signal combinations comprise a first input signal in1 and a second input signal in2, inputs the first input signal into the first functional unit, and inputs the second input signal into the second functional unit;

furthermore, the operation results of the first functional unit and the second functional unit, namely the FPGA state, are output to the processor, and the input is controlled according to the feedback result of the processor.

In the method provided by the embodiment, for each target signal combination, a first functional unit is used for executing target operation on a first input signal in each target signal combination to obtain a first operation result of the first functional unit corresponding to each target signal combination, a second functional unit is used for executing target operation on a second input signal in each target signal combination to obtain a second operation result of the second functional unit corresponding to each target signal combination, then the first operation result of the first functional unit and the second operation result of the second functional unit corresponding to each target signal combination are determined to be the target operation result of the field programmable logic gate array, and the target operation result is sent to the processor, so that the processor judges whether the function of a hardware system based on the field programmable logic gate array is abnormal or not based on the comparison result of the target operation result and the self-checking signal passing through the functional unit, and the accuracy of hardware system detection is improved.

Optionally, sending the target operation result to the processor includes:

and sending the target operation result, each target signal combination, the signal type mark of the first input signal in each target signal combination and the signal type mark of the second input signal in each target signal combination to the processor.

Specifically, in some embodiments, the process of sending the target operation result to the processor may be implemented by:

And sending the target operation result, each target signal combination, the signal type mark of the first input signal in each target signal combination and the signal type mark of the second input signal in each target signal combination to the processor. The target operation result is obtained by performing target operation on each target signal combination (a first input signal and a second input signal), the target operation result comprises a first operation result and a second operation result, the first operation result is obtained by performing target operation on the first input signal by the first functional unit, and the second operation result is obtained by performing target operation on the second input signal by the second functional unit. The first input signal and the second input signal each correspond to a signal type flag, e.g., the signal type flag of the first input signal is the original input signal, the signal type flag of the second input signal is an optional value of the self-test signal (e.g., a typical value of the original input signal), and, further, e.g., the signal type flag of the first input signal is an optional value of the self-test signal (e.g., a typical value of the original input signal), the signal type flag of the second input signal is the original input signal.

It can be understood that, because the optional value of the self-checking signal (for example, the typical value of the original input signal) is a predetermined typical value, the result of the passing through the functional units is known and determined, the processor can determine whether the function of the corresponding functional unit is abnormal through the operation result of the optional value of the self-checking signal after passing through the corresponding functional unit, further, because the first functional unit and the second functional unit are parallel functional units, the processor can determine whether the function of the parallel functional units is normal, further, whether the function of the hardware system based on the FPGA is normal, and the accuracy of the hardware system detection is realized.

In the method provided by the embodiment, the FPGA sends the target operation result, each target signal combination, the signal type mark of the first input signal in each target signal combination and the signal type mark of the second input signal in each target signal combination to the processor, so that the processor can conveniently judge whether the function of the hardware system based on the FPGA is abnormal according to the target operation result and the signal type mark in each target signal combination, and the reliability and the safety of the system are improved.

FIG. 5 is a second schematic diagram of a hardware system detection system according to the present invention, as shown in FIG. 5, the hardware system detection system 500 includes a field programmable gate array 510 and a processor 520;

The field programmable gate array 510 is configured to receive an original input signal; determining an optional value of a self-test signal based on the original input signal; determining at least one target signal combination according to the selectable values of the original input signal and the self-checking signal, and determining a target operation result of the field programmable gate array according to each target signal combination; sending the target operation result to the processor;

the processor 520 is configured to determine whether an abnormality exists in a function of the hardware system according to the target operation result.

Specifically, it should be noted that the hardware system detection system is used for detecting a hardware system, so as to improve the accuracy of hardware system detection. Hardware system detection system 500 includes field programmable gate array 510 and processor 520, wherein the individual modules function as follows:

The field programmable gate array 510 is configured to receive an original input signal; determining an optional value of a self-test signal based on the original input signal; the original input signal may be analog values such as sampled hardware system voltage and current, or may be signals such as data stream, and the selectable value of the self-checking signal is determined based on the original input signal, for example, a typical value of the original input signal sig is selected as the selectable value of the self-checking signal.

And then, determining at least one target signal combination according to the selectable values of the original input signal and the self-checking signal, and determining a target operation result of the field programmable gate array according to each target signal combination. Specifically, upon receiving the raw input signal and the selectable values of the self-test signal, the field programmable gate array FPGA determines at least one target signal combination based on the input signal, it being understood that the target signal combination is used to characterize how the selectable values of the raw input signal and the self-test signal are input into the functional unit, which is used to perform specific processing on the input signal, such as algorithmic processing, data parsing, etc. to perform target operations. For example, the target signal combination comprises a first input signal and a second input signal, the first input signal being determined based on the original input signal, the second input signal being determined based on a selectable value of the self-test signal, or the first input signal being determined based on a selectable value of the self-test signal, the second input signal being determined based on the original input signal. After at least one target signal combination is determined, a target operation is performed on each target signal combination to obtain a target operation result of each target signal combination. Further, the target operation result of each target signal combination is determined as the target operation result of the field programmable gate array FPGA.

Further, the field programmable gate array FPGA transmits the target operation result to the processor after determining the target operation result.

The processor 520 is configured to determine whether an abnormality exists in a function of the hardware system according to the target operation result. Specifically, after receiving the target operation result, the processor determines whether the function of the hardware system is abnormal or not based on the target operation result by the processor. The method includes comparing a target operation result with a preset comparison result, determining whether the function of the hardware system is abnormal, determining that the function of the hardware system is normal when the target operation result is consistent with the preset comparison result, and determining that the function of the hardware system is abnormal when the target operation result is inconsistent with the preset comparison result.

The hardware system detection system provided in this embodiment includes a field programmable gate array 510 and a processor 520, where the field programmable gate array 510 is firstly configured to receive an original input signal, and determine an optional value of a self-checking signal based on the original input signal; then, according to the selectable values of the original input signal and the self-checking signal, at least one target signal combination is determined, and a target operation result of the field programmable gate array is determined according to each target signal combination; and then, the target operation result is sent to the processor. The processor 520 is configured to determine whether an abnormality exists in a function of the hardware system according to the target operation result.

Optionally, the field programmable gate array comprises a state machine, a first functional unit and a second functional unit; the first functional unit and the second functional unit are parallel functional units, and the same target operation is executed in the first functional unit and the second functional unit; the target signal combinations are determined by using a state machine, and each target signal combination comprises a first input signal input into a first functional unit and a second input signal input into a second functional unit; each target operation result is determined based on the first operation result of the first functional unit and the second operation result of the second functional unit corresponding to each target signal combination;

Specifically, in some embodiments, a field programmable gate array FPGA includes a state machine, a first functional unit, and a second functional unit. The state machine is used for switching the original input signal and the self-checking signal so as to output different target signals to the functional unit. The first functional unit and the second functional unit are parallel functional units, and the first functional unit and the second functional unit execute the same target operation or execute the same data processing, that is, based on the working parallelism of the FPGA, the two functional units operate simultaneously and have the same function, and only the input signals are different.

The target signal combinations are determined by using a state machine, and each target signal combination, namely, represents different states of the state machine, wherein each target signal combination comprises a first input signal input into a first functional unit and a second input signal input into a second functional unit, and each target operation result is determined based on the first operation result of the first functional unit and the second operation result of the second functional unit corresponding to each target signal combination.

In the system provided by this embodiment, the field programmable gate array includes a state machine, a first functional unit and a second functional unit, where the first functional unit and the second functional unit are parallel functional units, the first functional unit and the second functional unit execute the same target operation, the target signal combinations are determined by using the state machine, each target signal combination includes a first input signal input into the first functional unit and a second input signal input into the second functional unit, and each target operation result is determined based on the first operation result of the first functional unit and the second operation result of the second functional unit corresponding to each target signal combination. The processor judges whether the hardware system is abnormal or not based on the target operation result corresponding to the target signal combination, thereby realizing the real-time detection of whether the function of the hardware system is normal or not and improving the detection accuracy of the hardware system.

Optionally, the processor 520 is specifically configured to:

For any target signal combination, under the condition that a first input signal in the target signal combination is determined according to selectable values of a preset number of self-checking signals, comparing a first operation result of the first functional unit with a preset operation result to obtain a first comparison result; the preset operation result is determined by utilizing a target operation tool according to selectable values of a preset number of self-checking signals;

determining whether the function of the hardware system is abnormal according to the first comparison result;

Comparing a second operation result of the second functional unit with a preset operation result to obtain a second comparison result under the condition that a second input signal in the target signal combination is determined according to selectable values of a preset number of self-checking signals;

Specifically, in some embodiments, the process of the processor 520 determining whether the function of the hardware system is abnormal based on the target operation result is exemplified as follows:

For any target signal combination, under the condition that a first input signal in the target signal combination is determined according to selectable values of a preset number of self-checking signals, comparing a first operation result of the first functional unit with a preset operation result to obtain a first comparison result; the selectable value of the self-test signal is, for example, a typical value of the original input signal, and the operation result of the selectable value of the self-test signal after specific processing is known and determined, that is, the comparison result of the self-test signal passing through the functional unit is a preset budget result, and the preset operation result is determined by using the target operation tool according to the selectable values of the preset number of self-test signals.

It can be understood that comparing the first operation result of the first functional unit with a preset operation result to obtain a first comparison result, where the first comparison result includes two cases: and according to the first comparison result, whether the functions of the hardware system are abnormal or not can be determined. For example, if the two are consistent, determining that there is no abnormality in the function of the hardware system; and under the condition that the two are inconsistent, determining that the function of the hardware system is abnormal.

Correspondingly, under the condition that the second input signals in the target signal combination are determined according to the selectable values of the preset number of self-checking signals, comparing the second operation result of the second functional unit with the preset operation result to obtain a second comparison result, and determining whether the function of the hardware system is abnormal according to the second comparison result. The second comparison result includes two cases: and (4) according to the consistency or the inconsistency, determining whether the function of the hardware system is abnormal or not according to the second comparison result. For example, if the two are consistent, determining that there is no abnormality in the function of the hardware system; and under the condition that the two are inconsistent, determining that the function of the hardware system is abnormal.

The hardware system detection device provided by the invention is described below, and the hardware system detection device described below and the hardware system detection method described above can be referred to correspondingly.

Fig. 6 is a schematic structural diagram of a hardware system detection device provided by the present invention, where the hardware system detection device 600 is applied to a field programmable gate array in a hardware system detection system, the hardware system detection system includes the field programmable gate array and a processor, and the hardware system detection device 600 includes a receiving module 610, a determining module 620 and a sending module 630.

A receiving module 610, configured to receive an original input signal;

A determination module 620 for determining an optional value of a self-test signal based on the original input signal; determining at least one target signal combination according to the selectable values of the original input signal and the self-checking signal, and determining a target operation result of the field programmable gate array according to each target signal combination;

a sending module 630, configured to send the target operation result to the processor; and the target operation result is used for the processor to determine whether the function of the hardware system is abnormal according to the target operation result.

In the device provided in this embodiment, the device is applied to a field programmable gate array in a hardware system detection system, where the hardware system detection system includes a field programmable gate array and a processor, first, a receiving module 610 is configured to receive an original input signal; then, the determining module 620 determines an optional value of the self-test signal based on the original input signal, determines at least one target signal combination according to the original input signal and the optional value of the self-test signal, and determines a target operation result of the field programmable gate array according to each target signal combination; further, the sending module 630 is configured to send a target operation result to the processor, where the target operation result is used for the processor to determine whether the function of the hardware system is abnormal according to the target operation result.

Optionally, the field programmable gate array includes a state machine, a first functional unit, and a second functional unit; the first functional unit and the second functional unit are parallel functional units, and the same target operation is executed in the first functional unit and the second functional unit; the number of the selectable values of the self-checking signal is a preset number; each target signal combination comprises a first input signal input into the first functional unit and a second input signal input into the second functional unit; the determining module 620 is specifically configured to:

determining the original input signal as the first input signal;

determining the original input signal as the second input signal;

Optionally, the determining module 620 is further configured to:

Optionally, the sending module 630 is specifically configured to:

Fig. 7 illustrates a physical schematic diagram of an electronic device, as shown in fig. 7, which may include: processor 710, communication interface (Communications Interface) 720, memory 730, and communication bus 740, wherein processor 710, communication interface 720, memory 730 communicate with each other via communication bus 740. Processor 710 may invoke logic instructions in memory 730 to perform a hardware system detection method for use with a field programmable gate array in a hardware system detection system comprising the field programmable gate array and the processor, the method comprising:

receiving an original input signal;

Further, the logic instructions in the memory 730 described above may be implemented in the form of software functional units and may be stored in a computer readable storage medium when sold or used as a stand alone product. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

In another aspect, the present invention also provides a computer program product, where the computer program product includes a computer program, where the computer program can be stored on a non-transitory computer readable storage medium, where the computer program when executed by a processor can perform a hardware system detection method provided by the methods above, where the method is applied to a field programmable gate array in a hardware system detection system, where the hardware system detection system includes the field programmable gate array and the processor, and where the method includes:

receiving an original input signal;

In yet another aspect, the present invention also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, is implemented to perform the hardware system detection method provided by the above methods, the method being applied to a field programmable gate array in a hardware system detection system, the hardware system detection system including the field programmable gate array and the processor, the method comprising:

receiving an original input signal;

The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.

From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A hardware system detection method, characterized in that it is applied to a field programmable logic gate array in a hardware system detection system, the hardware system detection system includes the field programmable logic gate array and a processor, and the method includes:

receiving an original input signal;

Determining a selectable value of a self-test signal based on the original input signal;

Determine at least one target signal combination according to the optional values of the original input signal and the self-test signal, and determine a target operation result of the field programmable logic gate array according to each of the target signal combinations;

The target operation result is sent to the processor; the target operation result is used by the processor to determine whether there is an abnormality in the function of the hardware system according to the target operation result.

2. The hardware system detection method according to claim 1 is characterized in that the field programmable logic gate array includes a state machine, a first functional unit and a second functional unit; the first functional unit and the second functional unit are parallel functional units, and the same target operation is performed in the first functional unit and the second functional unit; the number of optional values of the self-test signal is a preset number; each of the target signal combinations includes a first input signal input into the first functional unit and a second input signal input into the second functional unit; the determining of at least one target signal combination according to the optional values of the original input signal and the self-test signal comprises:

Determine the original input signal as the first input signal;

Determining the second input signal according to a preset number of optional values of the self-test signals;

Using the state machine, combining the first input signal and the second input signal to obtain the at least one target signal combination; and/or,

Determining the first input signal according to a preset number of optional values of the self-test signals;

Determine the original input signal as the second input signal;

The first input signal and the second input signal are combined by using the state machine to obtain the at least one target signal combination.

3. The hardware system detection method according to claim 2, wherein determining the target operation result of the field programmable logic gate array according to each target signal combination comprises:

For each of the target signal combinations, using the first functional unit to perform the target operation on the first input signal in each of the target signal combinations, to obtain a first operation result of the first functional unit corresponding to each of the target signal combinations;

Using the second functional unit to perform the target operation on the second input signal in each of the target signal combinations, to obtain a second operation result of the second functional unit corresponding to each of the target signal combinations;

The first operation result of the first functional unit and the second operation result of the second functional unit corresponding to each target signal combination are determined as the target operation result of the field programmable logic gate array.

4. The hardware system detection method according to claim 2, wherein sending the target operation result to the processor comprises:

The target operation result, each of the target signal combinations, the signal type flag of the first input signal in each of the target signal combinations, and the signal type flag of the second input signal in each of the target signal combinations are sent to the processor.

5. A hardware system detection system, characterized in that the hardware system detection system includes a field programmable logic gate array and a processor;

The field programmable logic gate array is used to receive an original input signal; determine an optional value of a self-test signal based on the original input signal; determine at least one target signal combination according to the original input signal and the optional value of the self-test signal, and determine a target operation result of the field programmable logic gate array according to each target signal combination; and send the target operation result to the processor;

The processor is used to determine whether there is an abnormality in the function of the hardware system according to the target operation result.

6. The hardware system detection system according to claim 5 is characterized in that the field programmable logic gate array includes a state machine, a first functional unit and a second functional unit; the first functional unit and the second functional unit are parallel functional units, and the same target operation is performed in the first functional unit and the second functional unit; the target signal combination is determined by using the state machine, and each target signal combination includes a first input signal input into the first functional unit and a second input signal input into the second functional unit; each target operation result is determined based on the first operation result of the first functional unit and the second operation result of the second functional unit corresponding to each target signal combination.

7. The hardware system detection system according to claim 6, wherein the processor is specifically used for:

For any of the target signal combinations, when the first input signal in the target signal combination is determined according to a preset number of optional values of the self-test signals, a first operation result of the first functional unit is compared with a preset operation result to obtain a first comparison result; the preset operation result is determined by using a target operation tool according to the preset number of optional values of the self-test signals;

Determining whether there is an abnormality in the function of the hardware system according to the first comparison result;

In the case where the second input signal in the target signal combination is determined according to the selectable values of a preset number of the self-test signals, comparing the second operation result of the second functional unit with the preset operation result to obtain a second comparison result;

According to the second comparison result, it is determined whether there is any abnormality in the function of the hardware system.

8. A hardware system detection device, characterized by being applied to a field programmable logic gate array in a hardware system detection system, the hardware system detection system comprising the field programmable logic gate array and a processor, the device comprising:

A receiving module, used for receiving an original input signal;

a determination module, configured to determine an optional value of a self-test signal based on the original input signal; determine at least one target signal combination according to the original input signal and the optional value of the self-test signal, and determine a target operation result of the field programmable logic gate array according to each of the target signal combinations;

The sending module is used to send the target operation result to the processor; the target operation result is used by the processor to determine whether there is an abnormality in the function of the hardware system according to the target operation result.

9. An electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the hardware system detection method according to any one of claims 1 to 4 when executing the program.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the hardware system detection method according to any one of claims 1 to 4 is implemented.

11. A computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the hardware system detection method according to any one of claims 1 to 4 is implemented.