CN118984155A - Adaptive temperature compensation charge pump phase-locked loop circuit and module based on MTJ - Google Patents
Adaptive temperature compensation charge pump phase-locked loop circuit and module based on MTJ Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
本发明涉及电荷泵锁相环设计技术领域，具体涉及基于MTJ的自适应温度补偿电荷泵锁相环电路、模块。本发明提供了基于MTJ的自适应温度补偿电荷泵锁相环电路，包括：鉴频鉴相部、电荷泵部、低通滤波部、压控振荡部、分频部。本发明在传统电荷泵锁相环的基础上，一方面在电荷泵部的上、下充放电路串联了磁隧道结MTJ，另一方面在双端输入、双端输出的压控振荡部的输出端也串联了磁隧道结MTJ；利用磁隧道结MTJ来进行温度补偿，有效得减少了电荷泵的电流失配，并使压控振荡器的频率稳定性得到大幅度的提升，保证并提升了CPPLL的使用效果。本发明解决了CPPLL易受到片上系统温度变化影响的问题。
The present invention relates to the technical field of charge pump phase-locked loop design, and in particular to an adaptive temperature compensated charge pump phase-locked loop circuit and module based on MTJ. The present invention provides an adaptive temperature compensated charge pump phase-locked loop circuit based on MTJ, comprising: a frequency and phase detection unit, a charge pump unit, a low-pass filter unit, a voltage-controlled oscillation unit, and a frequency division unit. On the basis of a traditional charge pump phase-locked loop, the present invention connects a magnetic tunnel junction MTJ in series to the upper and lower charge and discharge circuits of the charge pump unit, and also connects a magnetic tunnel junction MTJ in series to the output end of the voltage-controlled oscillation unit with double-end input and double-end output on the other hand; the magnetic tunnel junction MTJ is used for temperature compensation, which effectively reduces the current mismatch of the charge pump, and greatly improves the frequency stability of the voltage-controlled oscillator, thereby ensuring and improving the use effect of the CPPLL. The present invention solves the problem that the CPPLL is easily affected by the temperature change of the on-chip system.
Description
Technical Field
The invention relates to the technical field of charge pump phase-locked loop design, and more particularly, to: 1. an adaptive temperature compensation charge pump phase-locked loop circuit based on an MTJ; 2. an adaptive temperature compensated charge pump phase locked loop module based on an MTJ.
Background
A phase-locked loop circuit (PLL) is a closed-loop automatic control system that is capable of tracking the phase of an input signal. A Charge-Pump PLL (CPPLL) is one of the most widely used types of PLL circuits.
Charge pumps are commonly used with Phase Frequency Detectors (PFD), low Pass Filters (LPF), voltage Controlled Oscillators (VCO). The charge pump in CPPLL is an electronic switch that distributes charge to LPFs under PFD control. The charge pump has the advantage of being used with any PFD that outputs a two-level waveform with phase error information contained in the duty cycle of the waveform. This determines a significant improvement in the performance of the CPPLL, including efficiency of output phase lock, jitter, noise. The CPPLL adopts a passive low-pass filter, but can complete the work which can only be completed by an active filter, thereby effectively reducing noise and greatly reducing manufacturing cost.
However, commercial and high energy physical applications of CPPLL need to be able to run continuously over a wide temperature range, ideally without additional calibration. However, the system on a chip has high sensitivity fluctuation to temperature, and current mismatch of a charge pump and oscillation frequency drift of a VCO may occur: referring to fig. 1, the mismatch rate of the charge pump increases with decreasing temperature; referring to fig. 2, the oscillation frequency of the vco decreases with an increase in temperature. Both of these problems can affect the VCO and ultimately lead to phase loss in the phase locked loop. This is because: the main function of the charge pump is to convert the output pulse-converting the signal from the PFD into a corresponding current signal; the current signal is then converted into a voltage signal after passing through an LPF that adjusts the output frequency; any fluctuations in this voltage signal may interfere with the VCO output, resulting in jitter and reference spurs in the phase locked loop.
To sum up, it is extremely important to solve the temperature problem of the CPPLL system-on-chip, which is helpful to ensure and improve the use effect of CPPLL.
Disclosure of Invention
Based on this, it is necessary to provide MTJ-based adaptive temperature compensated charge pump phase locked loop circuits, modules, for the problem that CPPLLs are susceptible to system-on-chip temperature variations.
The invention is realized by adopting the following technical scheme:
In a first aspect, the present invention provides an MTJ-based adaptive temperature compensated charge pump phase locked loop circuit comprising: the device comprises a frequency and phase discrimination part, a charge pump part, a low-pass filtering part, a voltage-controlled oscillation part and a frequency division part.
The frequency and phase discrimination part is used for comparing phases of the reference signal FREF and the frequency division signal FVCODIV, and converting the compared phase difference into a signal UP and a signal DOWN. The charge pump unit charges and discharges the low-pass filter unit according to the UP and DOWN signals. The low-pass filter is used for adjusting the control voltage VTCAL of the voltage-controlled oscillation part. The voltage-controlled oscillation unit is configured to generate an oscillation signal FVCO under the control voltage VTCAL. The frequency dividing section is configured to divide the oscillation signal FVCO and output a divided signal FVCODIV.
The upper charge-discharge circuit of the charge pump part is connected with 1 magnetic tunnel junction MTJ1 in series, and the lower charge-discharge circuit is connected with 1 magnetic tunnel junction MTJ2 in series, which are all used for temperature compensation. The charge and discharge current of the upper charge and discharge circuit and the lower charge and discharge circuit of the charge pump part are the same.
The voltage-controlled oscillation section includes: a current mirror part and 3 differential amplifiers S 1~S3 which are arranged in cascade. The current mirror part is used as a current source of the differential amplifier S n; n is E [1,3]. The differential amplifier S n has an input terminal VIN n1, an input terminal VIN n2, an output terminal OUT n1, and an output terminal OUT n2. The output terminal OUT n1 is connected in series with 1 magnetic tunnel junction MTJ n1, and the output terminal OUT n2 is connected in series with 1 magnetic tunnel junction MTJ n2, which are all used for temperature compensation.
Implementation of such MTJ-based adaptive temperature-compensated charge pump phase-locked loop circuits is in accordance with methods or processes of embodiments of the present disclosure.
In a second aspect, the present invention discloses an MTJ-based adaptive temperature compensated charge pump phase locked loop module employing the layout of the MTJ-based adaptive temperature compensated charge pump phase locked loop circuit as disclosed in the first aspect.
Implementation of such MTJ-based adaptive temperature-compensated charge pump phase-locked loop modules is in accordance with methods or processes of embodiments of the present disclosure.
Compared with the prior art, the invention has the following beneficial effects:
On the basis of a traditional charge pump phase-locked loop, on one hand, the invention connects the Magnetic Tunnel Junction (MTJ) in series with the upper and lower charge-discharge circuits of the charge pump part, and on the other hand, the invention connects the Magnetic Tunnel Junction (MTJ) in series with the output end of the voltage-controlled oscillating part with double-end input and double-end output; temperature compensation is performed by using the Magnetic Tunnel Junction (MTJ), so that current mismatch of a charge pump is effectively reduced, frequency stability of a voltage-controlled oscillator is greatly improved, and the use effect of CPPLL is guaranteed and improved.
2, By adding the magnetic tunnel junction MTJ to the charge pump part, the invention reduces the current mismatch to below 0.3% in the range of-80-150 ℃ at a wide temperature, thereby improving the current matching stability at the wide temperature.
And 3, the Magnetic Tunnel Junction (MTJ) is added to the voltage-controlled oscillation part, so that the maximum frequency offset is only 8MHz within the range of wide temperature ranging from-80 ℃ to 150 ℃, and the stability of the frequency is improved.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the invention, and that other drawings can be obtained from these drawings without inventive faculty for a person skilled in the art.
FIG. 1 is a schematic diagram of the current mismatch mentioned in the background art;
FIG. 2 is a diagram of oscillation frequency drift mentioned in the background art;
FIG. 3 is a block diagram of an adaptive temperature compensated charge pump phase locked loop circuit based on an MTJ according to the present invention;
FIG. 4 is a circuit diagram of the first phase and frequency detector of FIG. 3;
FIG. 5 is a circuit diagram of a second phase and frequency detector of FIG. 3;
FIG. 6 is a circuit diagram of the charge pump section and the low pass filter section of FIG. 3;
FIG. 7 is a circuit diagram of the voltage controlled oscillator of FIG. 3;
FIG. 8 is a circuit diagram of the divider of FIG. 3;
FIG. 9 is a graph of simulation results provided in embodiment 1 of the present invention;
FIG. 10 is a second simulation result chart of the embodiment 1 of the present invention;
FIG. 11 is a third simulation result chart of the embodiment 1 of the present invention;
FIG. 12 is a diagram showing simulation results provided in embodiment 1 of the present invention;
FIG. 13 is a diagram showing simulation results provided in embodiment 1 of the present invention;
Fig. 14 is a block diagram of an MTJ-based adaptive temperature compensated charge pump phase locked loop module according to embodiment 2 of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It is noted that when an element is referred to as being "mounted to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "disposed on" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "secured to" another element, it can be directly secured to the other element or intervening elements may also be present.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or/and" as used herein includes any and all combinations of one or more of the associated listed items.
Example 1
Referring to fig. 3, fig. 3 shows an overall structure diagram of an MTJ-based adaptive temperature compensation charge pump phase locked loop circuit according to embodiment 1.
It should be noted that the MTJ-based adaptive temperature compensation charge pump phase locked loop circuit provided in embodiment 1 is a second type of phase locked loop.
As shown in fig. 3, according to the functional area division, the MTJ-based adaptive temperature compensation charge pump phase locked loop circuit provided in this embodiment 1 includes: the device comprises a frequency and phase discrimination part, a charge pump part, a low-pass filtering part, a voltage-controlled oscillation part and a frequency division part.
The following description will be made on each part:
1. The frequency and phase discrimination part is used for comparing phases of the reference signal FREF and the frequency division signal FVCODIV, and converting the compared phase difference into a signal UP and a signal DOWN.
The frequency and phase discrimination part can adopt the design as shown in fig. 4 or the design as shown in fig. 5:
I, referring to FIG. 4, the frequency and phase discrimination section includes: 2 flip-flops (i.e., flip-flop D1, flip-flop D2), 1 NAND gate (i.e., NAND gate NAND), 1 inverter (i.e., inverter INV).
Specifically, the input terminal D of the flip-flop D1 is connected to VDD, the clock signal terminal CLK is connected to the reference signal FREF, and the output terminal Q is connected to the signal UP. The input terminal D of the flip-flop D2 is connected to VDD, the clock signal terminal CLK is connected to the divided signal FVCODIV, and the output terminal Q is connected to the signal DOWN. The NAND gate NAND has an input connected to the UP signal and an input connected to the DOWN signal. The input end of the inverter INV is connected with the output end of the NAND gate NAND, and the output end is connected with the reset end RET of the trigger D1 and the reset end RET of the trigger D2.
II referring to FIG. 5, the frequency and phase discrimination section includes: 2 flip-flops (i.e., flip-flop D1, flip-flop D2), 1 AND gate (i.e., AND gate AND), 1 Delay unit (i.e., delay unit Delay).
Specifically, the input terminal D of the flip-flop D1 is connected to VDD, the clock signal terminal CLK is connected to the reference signal FREF, and the output terminal Q is connected to the signal UP. The input terminal D of the flip-flop D2 is connected to VDD, the clock signal terminal CLK is connected to the divided signal FVCODIV, and the output terminal Q is connected to the signal DOWN. AND the input end of the AND gate is connected with a signal UP AND the input end of the AND gate is connected with a signal DOWN. The input end of the Delay unit Delay is connected with the output end of the AND gate AND the output end is connected with the reset end RET of the trigger D1 AND the reset end RET of the trigger D2.
2. The charge pump unit charges and discharges the low-pass filter unit according to the UP and DOWN signals.
The charge pump section may adopt the design as shown in fig. 6:
Referring to fig. 6, the charge pump section includes: the device comprises 5 PMOS tubes (namely a PMOS tube P38, a PMOS tube P11, a PMOS tube P10, a PMOS tube P9 and a PMOS tube PM 5), 5 NMOS tubes (namely an NMOS tube N33, an NMOS tube N32, an NMOS tube N30, an NMOS tube N31 and an NMOS tube N4) and 2 magnetic tunnel junctions (namely a magnetic tunnel junction MTJ1 and a magnetic tunnel junction MTJ 2).
Specifically, the gate of the PMOS transistor P38 is connected to the source thereof, and the drain is connected to VDD. The gate of the NMOS transistor N33 is connected to the drain thereof, and the source is connected to the ground GND. The gate of the NMOS transistor N32 is connected with the gate of the NMOS transistor N33, and the source is connected with the ground GND. The grid electrode of the PMOS tube P11 is connected with the drain electrode thereof, and the source electrode is connected with the VDD. The grid electrode of the PMOS tube P10 is connected with the grid electrode of the PMOS tube P11, and the source electrode is connected with the VDD. The T1 end of the magnetic tunnel junction MTJ1 is connected with the drain electrode of the PMOS tube P10. The gate of the PMOS tube P9 is connected with a signal UP, the drain is connected with a control voltage VTCAL, and the source is connected with the T2 end of the magnetic tunnel junction MTJ 1. The gate of the NMOS transistor N30 is connected to the signal DOWN, and the drain is connected to the control voltage VTCAL. The T1 end of the magnetic tunnel junction MTJ2 is connected with the source of the NMOS transistor N30. The gate of the NMOS transistor N31 is connected with the gate of the NMOS transistor N33, the drain is connected with the T2 end of the magnetic tunnel junction MTJ2, and the source is connected with the ground GND. The gate of the NMOS tube N4 is connected with VDD, and the source is connected with the drain of the NMOS tube N32. The gate of the PMOS tube PM5 is connected with VSS, the drain is connected with the drain of the NMOS tube N4, and the source is connected with the drain of the PMOS tube P11.
The PMOS tube P10, the magnetic tunnel junction MTJ1 and the PMOS tube P9 form an upper charge-discharge circuit: when the upper charge/discharge circuit is turned on, VDD is charged by the upper charge/discharge circuit, thereby increasing the control voltage VTCAL.
The NMOS tube N31, the magnetic tunnel junction MTJ2 and the NMOS tube N30 form a lower charge-discharge circuit: when the lower charge-discharge circuit is turned on, the control voltage VTCAL is discharged to VSS through the lower charge-discharge circuit, thereby reducing the control voltage VTCAL.
It should be noted that:
Referring to what is described in the background, conventional charge pumps can exhibit current mismatch and can result in more pronounced current mismatch as temperature decreases.
In embodiment 1, the PMOS transistor P38, the PMOS transistor P11, the NMOS transistor N33, and the NMOS transistor N32 form a current mirror, so that the charge and discharge currents of the upper charge and discharge circuit and the lower charge and discharge circuit can be the same, which can avoid current difference and ensure the current matching performance of the charge pump unit.
The upper charge-discharge circuit of the charge pump section is connected in series with 1 magnetic tunnel junction MTJ1, and the lower charge-discharge circuit is connected in series with 1 magnetic tunnel junction MTJ2, both for temperature compensation. This is based on the following principle: the on-resistance of the MOS tube of the charge pump part increases with the temperature rise, namely has positive temperature coefficient; that is, when the magnetic tunnel junction is not added, the charge pump section has a large current at a low temperature; therefore, elements capable of providing a negative temperature coefficient of resistance are employed to counteract the temperature drift to reflect the constant temperature characteristics. The inventor discovers that the anti-parallel resistance of the magnetic tunnel junction becomes larger along with the reduction of the temperature through researching the magnetic tunnel junction, and the parallel resistance basically does not change along with the temperature; that is, the high resistance of the magnetic tunnel junction has a negative temperature coefficient, and the charge pump section can be temperature-compensated. In addition, the magnetic tunnel junction has the advantage of low power consumption, and the magnetic tunnel junction is added to the charge pump part, so that the overall power consumption can be reduced.
Referring to FIG. 6, magnetic tunnel junctions MTJ1, MTJ2 may be considered to have a negative temperature coefficient of resistance R AP. The PMOS transistor P10 and the NMOS transistor N31 may be regarded as resistors R 0 having positive temperature coefficients, so that the two types of resistors having positive temperature coefficients are used to compensate each other's temperature, which not only can further suppress current mismatch, but also can greatly reduce the power of the charge pump portion.
3. The low-pass filter is used for adjusting the control voltage VTCAL of the voltage-controlled oscillation part.
The low-pass filter section may be designed as shown in fig. 6:
Referring to fig. 6, the low-pass filtering part includes: 2 capacitors (i.e., capacitor C1, capacitor C2), 1 resistor (i.e., resistor R2).
Specifically, one end of the capacitor C1 is connected to the control voltage VTCAL, and the other end is connected to the ground GND. One end of the resistor R2 is connected with the control voltage VTCAL. One end of the capacitor C2 is connected with the other end of the resistor R2, and the other end is connected with the ground GND.
In particular, the method comprises the steps of,
When the signal UP is at a high level and the signal DOWN is at a low level, the upper charge-discharge circuit is turned on, the lower charge-discharge circuit is turned off, and the charge pump unit charges the low-pass filter unit with a charge current I1.
When the signal UP is at low level and the signal DOWN is at high level, the upper charge-discharge circuit is turned off, the lower charge-discharge circuit is turned on, and the charge pump section discharges the low-pass filter section with a discharge current I2.
Wherein, the sizes of I1 and I2 are the same.
And III, when the signal UP and the signal DOWN are both in low level, the upper charge-discharge circuit is disconnected, the lower charge-discharge circuit is disconnected, and the low-pass filter part does not charge and discharge, wherein the output of the charge pump part is in a high-resistance state.
And IV, when the signal UP and the signal DOWN are both high, the upper charge-discharge circuit is conducted, the lower charge-discharge circuit is conducted, and the low-pass filter part does not conduct charge and discharge, namely a path from VDD to GND is formed at the moment, and no current passes through the low-pass filter part.
4. The voltage-controlled oscillation unit is configured to generate an oscillation signal FVCO under the control voltage VTCAL.
The voltage-controlled oscillation section includes: a current mirror part and 3 differential amplifiers S 1~S3 which are arranged in cascade. The current mirror part is used as a current source of the differential amplifier S n; n is E [1,3]. The differential amplifier S n is a double-ended input and a double-ended output, that is, has an input terminal VIN n1, an input terminal VIN n2, an output terminal OUT n1, and an output terminal OUT n2.
The voltage-controlled oscillation section may employ a design as shown in fig. 7:
referring to fig. 7, the current mirror part includes: 1 PMOS tube (namely PMOS tube PM 10), 1 NMOS tube (NMOS tube NM 10).
Specifically, the gate of the PMOS transistor PM10 is connected to the drain thereof, and the source is connected to VDD. The gate of the NMOS transistor NM10 is connected with the drain thereof, the source is connected with VSS, and the drain is connected with the drain of the PMOS transistor PM 10.
The differential amplifier S n includes: 3 NMOS tubes (i.e., NMOS tube N n, NMOS tube N n1, NMOS tube N n2), 2 magnetic tunnel junctions (i.e., magnetic tunnel junction MTJ n1, magnetic tunnel junction MTJ n2), 2 capacitors (i.e., capacitor C n1, capacitor C n2).
Specifically, the source of the NMOS transistor N n is connected to VSS, and the gate is connected to the gate of the NMOS transistor NM 10. The source of the NMOS transistor N n1 is connected with the drain of the NMOS transistor N n, the gate is connected with the input end VIN n1, and the drain is connected with the output end OUT n1. The source of the NMOS transistor N n2 is connected with the drain of the NMOS transistor N n, the gate is connected with the input end VIN n2, and the drain is connected with the output end OUT n2. The T2 terminal of the magnetic tunnel junction MTJ n1 is connected to the output OUT n1 and the T1 terminal is connected to VDD. The T2 terminal of the magnetic tunnel junction MTJ n2 is connected to the output OUT n2 and the T1 terminal is connected to VDD. One end of the capacitor C n1 is connected to the output terminal OUT n1, and the other end is connected to the control voltage VTCAL. One end of the capacitor C n2 is connected to the output terminal OUT n2, and the other end is connected to the control voltage VTCAL.
Wherein the oscillating signal FVCO is positively correlated with the control voltage VTCAL —both are almost linear: the voltage of the control voltage VTCAL becomes large, and the frequency of the oscillation signal FVCO increases; the voltage of the control voltage VTCAL becomes small and the frequency of the oscillation signal FVCO decreases.
It should be noted that:
Referring to the background art, a conventional VCO may experience oscillation frequency drift, and the oscillation frequency decreases with an increase in temperature.
In the present embodiment 1,1 magnetic tunnel junction MTJ n1 is connected in series to the output terminal OUT n1, and 1 magnetic tunnel junction MTJ n2 is connected in series to the output terminal OUT n2. Similar to the charge pump section, the magnetic tunnel junction MTJ n1, the magnetic tunnel junction MTJ n2 are used for temperature compensation. This is also based on a similar principle: the on-resistance of the MOS tube of the VCO increases with increasing temperature-i.e. has a positive temperature coefficient; the magnetic tunnel junction can be regarded as a resistor R AP with a negative temperature coefficient, so that the two temperature coefficient types of resistors are utilized to compensate the temperature of each other, thereby not only suppressing the oscillation frequency drift, but also greatly reducing the power of the voltage-controlled oscillation part.
5. The frequency dividing section is configured to divide the oscillation signal FVCO and output a divided signal FVCODIV.
As shown in fig. 3, the divided signal FVCODIV returns to the phase and frequency discrimination section, thus forming a closed loop feedback.
The frequency dividing section may adopt the design as shown in fig. 8:
Referring to fig. 8, the frequency dividing section includes: 4 flip-flops (i.e., flip-flop D3, flip-flop D4, flip-flop D5, flip-flop D6).
Specifically, the input terminal D of the flip-flop D3 is connected to the output terminal QB thereof, the clock signal terminal CLK is connected to the oscillation signal FVCO, and the reset terminal RET is connected to VSS. The input terminal D of the flip-flop D4 is connected to the output terminal QB thereof, the clock signal terminal CLK is connected to the input terminal D of the flip-flop D3, and the reset terminal RET is connected to VSS. The input terminal D of the flip-flop D5 is connected to the output terminal QB thereof, the clock signal terminal CLK is connected to the input terminal D of the flip-flop D4, and the reset terminal RET is connected to VSS. The input terminal D of the flip-flop D6 is connected to the output terminal QB thereof, the output terminal QB is connected to the divided signal FVCODIV, the clock signal terminal CLK is connected to the input terminal D of the flip-flop D5, and the reset terminal RET is connected to VSS.
That is, the frequency dividing section is composed of 4 flip-flops cascade-connected to each other, and is a 16-bit frequency division.
The self-adaptive temperature compensation charge pump phase-locked loop circuit based on the MTJ with the structure can compensate the temperature, weaken the influence of system-on-chip temperature change, and ensure and improve the using effect of CPPLL.
Simulation verification
The present embodiment 1 also simulates the MTJ-based adaptive temperature compensation charge pump phase locked loop circuit with the above structure to verify the effect:
1. the charge pump section to which the MTJ was added was simulated, and the results are shown in fig. 9 and 10.
Fig. 9 shows current mismatch curves for the charge pump section with MTJ added at different temperatures. Unlike fig. 1, the curves of different temperatures in fig. 9 have high overlapping degree, and it is known that the current matching performance of the charge pump section to which the MTJ is added is very good—the current mismatch is less than 0.3%, and it is explained that the temperature does not have a significant influence on the current mismatch of the charge pump section to which the MTJ is added.
Fig. 10 shows the compensation effect curves of the MOS transistor and the MTJ resistor. It is known that the on-resistance of the MOS tube increases with increasing temperature, i.e. has a positive temperature coefficient; the corresponding R AP of the MTJ is decreasing with increasing temperature-i.e., has a negative temperature coefficient. Then the total resistance of the two resistors is stacked together in the temperature range-80 ℃ to 125 ℃ with the total resistance being hardly affected by the temperature and remaining constant. In addition, most of slopes are found to be 0 after the total resistance is derived with respect to temperature, which indicates that the total resistance can neglect the influence of temperature, and also indicates that the charge pump part added with the MTJ can well perform temperature compensation.
2. The voltage-controlled oscillation section to which the MTJ was added was simulated, and the voltage-controlled oscillation section to which the MTJ was not added was introduced for comparison, and the results were shown in fig. 11, 12, and 13.
Fig. 11 shows the change of the control voltage VTCAL and the oscillation signal FVCO without adding the MTJ. It can be seen that when no MTJ is added, there is a change in control voltage VTCAL ranging from 0.32V to 0.6v—280 mv; the frequency of the oscillating signal FVCO fluctuates from 2.54GHz to 2.638ghz—there is a fluctuation of 98 MHz. Fig. 12 shows the change of the control voltage VTCAL and the oscillation signal FVCO after the MTJ is added. It can be seen that with the addition of the MTJ, the control voltage VTCAL ranges from 0.42V to 0.47v—there is a 50mv change; the frequency fluctuation of the oscillation signal FVCO is also reduced to only 8MHz. The voltage-controlled oscillation part added with the MTJ can well perform temperature compensation and restrain oscillation frequency drift.
In addition, the output noise gain of the voltage controlled oscillation section is an important factor affecting the entire CPPLL, and should be considered. Fig. 13 shows comparison of output noise of the voltage controlled oscillation section to which the MTJ is added and the voltage controlled oscillation section to which the MTJ is not added, and it is clear that the output noise curves of the two are not greatly different, and the influence of the addition of the MTJ on the output noise of the voltage controlled oscillation section is negligible.
Example 2
This embodiment 2 discloses an MTJ-based adaptive temperature compensated charge pump phase locked loop module employing the layout of the MTJ-based adaptive temperature compensated charge pump phase locked loop circuit as disclosed in embodiment 1. The packaging mode is a module mode, so that the popularization and the application of the circuit are easier.
Referring to fig. 14, the MTJ-based adaptive temperature compensated charge pump phase locked loop module includes, in functional division: the device comprises a phase frequency detector, a charge pump, a low-pass filter, a voltage-controlled oscillator and a frequency divider.
The phase frequency detector corresponds to the phase frequency detector; the charge pump corresponds to the charge pump part; the low-pass filter corresponds to the low-pass filtering part; the voltage-controlled oscillator corresponds to the voltage-controlled oscillating part; the frequency divider corresponds to the frequency dividing part; specific circuit distributions are referred to in example 1 and are not repeated here.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (10)
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