CN118971886A - A preamplifier circuit for low supply voltage SAR ADC - Google Patents

Abstract

The invention provides a pre-amplifier circuit for a low supply voltage SAR ADC, comprising: the improved sampling circuit is used for sampling the input differential signal to obtain a first differential signal; the input end of the preamplifier is connected with the output end of the improved sampling circuit and is used for amplifying the first differential signal to obtain a second differential signal; and the input end of the common mode feedback circuit is connected with the output end of the pre-amplifier, outputs a feedback signal to the pre-amplifier, is used for detecting the common mode signal of the second differential signal, and carries out feedback processing on the second differential signal based on a reference voltage so as to adjust the second differential signal to enable the transistor in the pre-amplifier to be in a normal working state. The pre-amplifier circuit has a simple structure, solves the problem that the common mode gain of the pre-amplifier is difficult to reduce in a transistor-level circuit under low power supply voltage, and improves the stability of input signals of a later-stage dynamic comparator.

Description

Pre-amplifier circuit for low supply voltage SAR ADC

Technical Field

The invention belongs to the technical field of integrated circuits, and relates to a preamplifier circuit for a low supply voltage SAR ADC.

Background

With the continuous development of microelectronic technology, requirements of modern electronic devices on energy efficiency, performance and integration level are continuously improved. The advent of System on Chip (SoC) technology has enabled the integration of processors, memory, and other functional modules onto a single Chip, thereby enabling smaller size and lower power consumption. However, as process nodes shrink, the operating voltage of the SoC also decreases, which presents challenges to the design of analog circuits.

Analog-to-Digital Converter (ADC) converts Analog signals to digital signals, an important component in SoC Analog circuits. The signal swing is reduced at low supply voltages and the effects of noise and nonlinearity on analog-to-digital conversion are increased, so there is a need for an ADC architecture that can maintain high performance at lower supply voltages. The successive approximation analog-to-digital converter (Successive Approximation Register Analog-to-Digital Converter, SAR ADC) is widely used in SoC applications because of its simple structure and few analog modules. The SAR ADC consists of a digital-to-analog converter, a comparator, an SAR logic module and the like, wherein the comparator is a key module for determining the speed, the precision and the power consumption of the SAR ADC. The dynamic comparator is difficult to realize high speed and low power consumption and simultaneously has low noise and low offset, and the pre-amplifier module is added in front of the dynamic comparator to effectively inhibit noise and offset voltage of a system introduced by the comparator.

Compared with other traditional structures, the pre-amplifier structure based on the phase inverter has the advantages of simple structure, high current energy efficiency and the like, and the problem of output common mode offset caused by process deviation can be solved through dynamic common mode feedback. However, the inverter type preamplifier structure requires at least two transistor stacks, which is not suitable for the application scenario of low power supply voltage. In addition, the low power supply voltage limits the stacking number of transistors, and the inverter type pre-amplifier adopts a pseudo-differential structure and cannot add a tail current tube; although dynamic common mode feedback can suppress the common mode gain of low frequencies, it still has the disadvantage of too high a high frequency common mode gain; the high-frequency input common-mode signal is amplified by the pre-amplifier and then transmitted to the later-stage dynamic comparator, so that the work of the high-frequency input common-mode signal is influenced, and the system performance is further influenced.

Therefore, how to adjust the structure of the inverter type pre-amplifier to be suitable for low power supply voltage application and reduce the influence of the high-frequency output common mode signal on the post-stage dynamic comparator is a technical problem to be solved at present.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a preamplifier circuit for a low supply voltage SAR ADC, which is used to solve the drawbacks of the existing preamplifier that it is not suitable for low supply voltage and that the high frequency common mode gain causes unstable output common mode voltage.

To achieve the above object, the present invention provides a preamplifier circuit for a low supply voltage SAR ADC, comprising:

The improved sampling circuit is used for sampling the input differential signal to obtain a first differential signal;

The pre-amplifier is used for amplifying the first differential signal to obtain a second differential signal; and

And the common mode feedback circuit is coupled with the pre-amplifier and is used for detecting a common mode signal of a second differential signal and carrying out feedback processing on the second differential signal based on a reference voltage so as to adjust the second differential signal, so that a transistor in the pre-amplifier is in a normal working state.

In one embodiment of the present invention, the improved sampling circuit comprises: the improved sampling circuit comprises: a first capacitor C1, a second capacitor C2, first to fifth bootstrap switches K1 to K5, a sixth switch K6, and a seventh switch K7; a first end of the first bootstrap switch K1 is connected with the second input end Vin, a first end of the second bootstrap switch K2 is connected with the first input end Vip, and first ends of the third bootstrap switch K3, the fourth bootstrap switch K4, the sixth switch K6 and the seventh switch K7 are connected with the reference voltage Vcm; the second end of the first bootstrap switch K1 and the second end of the sixth switch K6 are connected to the first end of the first capacitor C1; the second end of the second bootstrap switch K2 and the second end of the seventh switch K7 are connected to the first end of the second capacitor C2; the second end of the first capacitor C1 and the second end of the third bootstrap switch K3 are connected with the first end of the fifth bootstrap switch K5 and are connected with the second output end Vxn of the improved sampling circuit; the second end of the second capacitor C2 and the second end of the fourth bootstrap switch K4 are connected to the second end of the fifth bootstrap switch K5, and are connected to the first output end Vxp of the improved sampling circuit; the control ends of the first bootstrap switch K1 and the second bootstrap switch K2 are connected to a first clock signal clk1; the control ends of the third bootstrap switch K3 and the fourth bootstrap switch K4 are connected to a second clock signal clk2; the control end of the fifth bootstrap switch K5 is connected to a third clock signal clk3; the control ends of the sixth switch K6 and the seventh switch K6 are connected to a fourth clock signal clk4.

In an embodiment of the present invention, the capacitance values of the first capacitor C1 and the second capacitor C2 are equal; the first bootstrap switch K1 and the second bootstrap switch K2 are equal in size; the third bootstrap switch K3 and the fourth bootstrap switch K4 are equal in size; the sixth switch K6 and the seventh switch K7 are equal in size.

In an embodiment of the present invention, the first clock signal clk1 to the fourth clock signal clk4 have equal frequencies, wherein the first rising edges of the second clock signal clk2, the third clock signal clk3 and the fourth clock signal clk4 coincide, the falling edges of the second clock signal clk2, the fourth clock signal clk4 coincide with the rising edges of the first clock signal clk1, and the falling edges of the first clock signal clk1 follow the falling edges of the third clock signal clk3 and precede the second rising edges of the fourth clock signal clk 4.

In one embodiment of the present invention, the pre-amplifier has four input terminals and two output terminals, wherein a first input terminal and a second input terminal of the pre-amplifier are used for switching in the first differential signal; the third input end of the pre-amplifier is used for accessing the feedback signal; the fourth input end of the pre-amplifier is used for being connected with a bias voltage signal; the first output end and the second output end of the pre-amplifier are used for outputting the second differential signal.

In one embodiment of the present invention, the pre-amplifier includes: the first to fourth resistors R1 to R4, the third to sixth capacitors C3 to C6, the first to third PMOS tubes Mp1 to Mp3, and the first to fourth NMOS tubes Mn1 to Mn4; the first end of the third capacitor C3 is connected to the first end of the fourth capacitor C4, and is connected to the first output end Vxp of the improved sampling circuit; a first end of the fifth capacitor C5 is connected to a first end of the sixth capacitor C6, and is connected to the second output end Vxn of the improved sampling circuit; the first end of the first resistor R1, the first end of the third resistor R3 and the drain electrode of the fourth NMOS tube Mn4 are connected with the grid electrode and the drain electrode of the third PMOS tube MP 3; the first end of the second resistor R2 is connected with the first end of the fourth resistor R4 and is connected with the third input end Vbn of the pre-amplifier, namely the feedback signal; the second end of the third capacitor C3 and the second end of the first resistor R1 are connected with the grid electrode of the first PMOS tube MP 1; the second end of the fourth capacitor C4 and the second end of the second resistor R2 are connected with the grid electrode of the first NMOS tube Mn 1; the second end of the fifth capacitor C5 and the second end of the third resistor R3 are connected with the grid electrode of the second PMOS tube MP 2; the second end of the sixth capacitor C6 and the second end of the fourth resistor R4 are connected with the grid electrode of the second NMOS tube Mn 2; the drain electrode of the first PMOS tube MP1 is connected with the drain electrode of the first NMOS tube Mn1 and is connected with the first output end Von of the pre-amplifier; the drain electrode of the second PMOS tube MP2 is connected with the drain electrode of the second NMOS tube Mn2 and is connected with the second output end Vop of the pre-amplifier; the grid electrode and the drain electrode of the third NMOS tube Mn3 are connected with the grid electrode of the fourth NMOS tube Mn4 and are connected with the fourth input end Vb of the pre-amplifier, the sources of the first PMOS tube MP1 to the third PMOS tube MP3 are all connected with a power supply, and the sources of the first NMOS tube Mn1 to the fourth NMOS tube Mn4 are all grounded.

In an embodiment of the present invention, the resistance values of the first resistor R1 to the fourth resistor R4 are equal; the capacitance values of the third capacitor C3 to the sixth capacitor C6 are equal.

In one embodiment of the present invention, the common mode feedback circuit includes: the first input end and the second input end of the common mode detection module are correspondingly connected with the first output end and the second output end of the pre-amplifier respectively; the third input end of the common mode detection module is connected with a reference voltage signal, and the clock signal control end of the common mode detection module is connected with a common mode detection clock signal and is used for comparing the first differential signal with the reference voltage signal based on the common mode detection clock signal to obtain a comparison result signal; the input end of the charge sharing module is connected with the output end of the common mode detection module, and is used for receiving the comparison result signal output by the common mode detection module, and carrying out charge sharing with the last feedback signal according to the comparison result signal to obtain the feedback signal; and the buffer module is connected between the charge sharing module and the input end of the pre-amplifier, and is used for receiving the feedback signal output by the charge sharing module and outputting the feedback signal to the input end of the pre-amplifier.

In one embodiment of the present invention, the charge sharing module includes: seventh to ninth capacitances C7 to C9, tenth PMOS transistor Mp10, eleventh PMOS transistor Mp11, sixteenth NMOS transistor Mn16, seventeenth NMOS transistor Mn17, and inverter inv; the gate of the tenth PMOS Mp10 is connected to the gate of the sixteenth NMOS Mn16, and is connected to the first output terminal of the common mode detection module 31; a second output end of the common mode detection module 31 is connected with an input end of the inverter inv; the output end of the inverter inv is connected with the grid electrode of the eleventh PMOS tube MP11 and the grid electrode of the seventeenth NMOS tube Mn 17; the drain electrode of the tenth PMOS tube Mp10 and the drain electrode of the sixteenth NMOS tube Mn16 are connected with the first end of the seventh capacitor C7; the drain electrode of the eleventh PMOS tube Mp11 and the drain electrode of the seventeenth NMOS tube Mn17 are connected with the first end of the eighth capacitor C8; the source of the sixteenth PMOS transistor Mp16 and the source of the eleventh NMOS transistor Mn11 are connected to the first end of the ninth capacitor C9, and are connected to the output end Vcmfb of the charge sharing module 32; the source electrode of the tenth PMOS tube MP10 is connected with the power supply voltage, the source electrode of the seventeenth NMOS tube Mn17 is grounded, and the second ends of the seventh to ninth capacitors C7 to C9 are grounded.

As described above, the pre-amplifier circuit for the low supply voltage SAR ADC provided by the present invention can be adapted to an application scenario of a low supply voltage by improving the structure of the pre-amplifier; by arranging the common mode feedback unit at the output end of the amplifier, the risk that the transistor enters a linear region due to excessively high or excessively low output common mode caused by process deviation is reduced, and meanwhile, the low-frequency common mode gain is reduced; by improving the sampling circuit in front of the pre-amplifier, the high-frequency common-mode gain from the input signal to the output signal of the pre-amplifier is reduced, and the stability of the input common-mode signal of the later-stage dynamic comparator is improved.

Drawings

FIG. 1 is a block diagram of a preamplifier circuit for a low supply voltage SAR ADC according to an embodiment of the present invention;

FIG. 2 is a circuit diagram of an improved sampling circuit according to an embodiment of the present invention;

FIG. 3 is a circuit diagram of a pre-amplifier according to an embodiment of the invention;

FIG. 4 is a schematic diagram of a common mode feedback circuit according to an embodiment of the invention;

FIG. 5 is a circuit diagram of a common mode detection module of a common mode feedback circuit according to an embodiment of the present invention;

FIG. 6 is a circuit diagram of a charge sharing module and a buffer module of a common mode feedback circuit according to an embodiment of the present invention;

Fig. 7 is an eye diagram waveform diagram of a common mode voltage signal of the first differential signal according to an embodiment of the present invention.

Detailed Description

Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.

It should be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.

The invention provides a pre-amplifier circuit for a low supply voltage SAR ADC, which can work under the low supply voltage by improving the structure of a traditional inverter type pre-amplifier; by arranging the common mode feedback unit at the output end of the amplifier, the risk that the transistor enters a linear region due to excessively high or excessively low output common mode caused by process deviation is reduced, and meanwhile, the low-frequency common mode gain is reduced; by improving the sampling circuit, the common mode gain of the preamplifier in the high frequency band is restrained, and the stability of the input common mode signal of the post-stage dynamic comparator is improved. The following will be described in connection with specific embodiments.

Referring to fig. 1, a schematic diagram of a preamplifier circuit for a low supply voltage SAR ADC according to an embodiment of the invention is shown. As shown in fig. 1, the pre-amplifier circuit for a low supply voltage SAR ADC includes: a modified sampling circuit 1, a pre-amplifier 2, and a common mode feedback circuit 3 coupled to the pre-amplifier 2.

Wherein the modified sampling circuit 1 has a first input Vip, a second input Vin, and a third input Vcm, a first output Vxp, and a second output Vxn; the first input end Vip and the second input end Vin of the improved sampling circuit 1 are connected with input signals, and the third input end of the improved sampling circuit 1 is connected with a reference voltage signal; the improved sampling circuit 1 is used for sampling a differential mode signal of an input signal and suppressing a common mode signal of the input signal to obtain a first differential signal.

Referring to fig. 2, fig. 2 shows a circuit diagram of a modified sampling circuit 1. As shown in fig. 2, the improved sampling circuit 1 has a differential structure of a double-ended input and a double-ended output, and includes: a first capacitor C1, a second capacitor C2, first to fifth bootstrap switches K1 to K5, a sixth switch K6, and a seventh switch K7; a first end of the first bootstrap switch K1 is connected to the second input end Vin, a first end of the second bootstrap switch K2 is connected to the first input end Vip, and first ends of the third bootstrap switch K3, the fourth bootstrap switch K4, the sixth switch K6 and the seventh switch K7 are connected to the third input end (i.e., reference voltage) Vcm; the second end of the first bootstrap switch K1 and the second end of the sixth switch K6 are connected with the first end of the first capacitor C1; the second end of the second bootstrap switch K2 and the second end of the seventh switch K7 are connected with the first end of the second capacitor C2; the second end of the first capacitor C1 and the second end of the third bootstrap switch K3 are connected with the first end of the fifth bootstrap switch K5 and are connected with the second output end Vxn of the improved sampling circuit 1; the second end of the second capacitor C2, the second end of the fourth bootstrap switch K4 and the second end of the fifth bootstrap switch K5 are connected, and are connected to the first output end Vxp of the improved sampling circuit; the control ends of the first bootstrap switch K1 and the second bootstrap switch K2 are connected with a first clock signal clk1; the control ends of the third bootstrap switch K3 and the fourth bootstrap switch K4 are connected to a second clock signal clk2; the control end of the fifth bootstrap switch K5 is connected to a third clock signal clk3; the control ends of the sixth switch K6 and the seventh switch K7 are connected to the fourth clock signal clk4.

In this embodiment, the capacitance values of the first capacitor C1 and the second capacitor C2 are equal, and are used as a sampling capacitor and a digital-to-analog conversion capacitor in successive approximation, where the capacitance value depends on the specific application; the first bootstrap switch K1 and the second bootstrap switch K2 are equal in size and serve as a bottom plate sampling switch; the third bootstrap switch K3 and the fourth bootstrap switch K4 are equal in size and serve as top plate sampling switches; the sixth switch K6 and the seventh switch K7 are equal in size and serve as a top plate common mode voltage initialization switch.

In this embodiment, the improved sampling circuit has one more additional phase than the conventional backplane sampling circuit, specifically, as shown in fig. 2, the first rising edges of the second clock signal clk2, the third clock signal clk3 and the fourth clock signal clk4 coincide, the falling edges of the second clock signal clk2 and the fourth clock signal clk4 coincide with the rising edges of the first clock signal clk1, and the falling edges of the first clock signal clk1 are after the falling edges of the third clock signal clk3 and before the second rising edges of the fourth clock signal clk 4. Before the first clock signal clk1 rises, the second clock signal clk2, the third clock signal clk3 and the fourth clock signal clk4 are at high level at the same time, and the top plate voltage and the bottom plate voltage of the sampling capacitor are reset to preset common mode signals; after the second clock signal clk2 decreases to a low level, the first clock signal clk1 increases to sample the differential input signal, and at this time, the fifth switch K5 is still closed, and the top plate is in a floating state; after a period of sampling time, the third clock signal clk3 is reduced from high level to low level, so as to complete sampling, and then the first clock signal clk1 is reduced from high level to low level; finally, the fourth clock signal clk4 rises again, and the sampled differential input signal is transferred from the bottom plate to the top plate, so that sampling is completed. The research shows that the improved sampling circuit can inhibit common-mode voltage signal components in differential input signals, and further reduce common-mode gain of input differential signals to output signals of the pre-amplifier.

In addition, the pre-amplifier 2 has a first input terminal, a second input terminal, a third input terminal and a fourth input terminal, the first input terminal of the pre-amplifier 2 is connected to a first voltage signal, the second input terminal of the pre-amplifier 2 is connected to a second voltage signal, and the difference between the first voltage signal and the second voltage signal is calculated and amplified to obtain a second differential signal.

Referring to fig. 3, fig. 3 shows a circuit diagram of the preamplifier 2. As shown in fig. 3, the pre-amplifier 2 has a pseudo-differential structure of a double-ended input and a double-ended output, and includes: the first resistor R1 to the fourth resistor R4, the third capacitor C3 to the sixth capacitor C6, the first PMOS tube Mp1 to the third PMOS tube Mp3, the first NMOS tube Mn1 to the fourth NMOS tube Mn4; wherein the first end of the third capacitor C3 is connected to the first end of the fourth capacitor C4, and is connected to the first input end of the pre-amplifier 2 (i.e., the first output end Vxp of the sampling circuit 1); a first end of the fifth capacitor C5 is connected to a first end of the sixth capacitor C6, and is connected to a second input end of the preamplifier 2 (i.e., the second output end Vxn of the sampling circuit 1); the first end of the first resistor R1, the first end of the third resistor R3 and the drain electrode of the fourth NMOS tube Mn4 are connected with the grid electrode and the drain electrode of the third PMOS tube MP 3; the first end of the second resistor R2 is connected with the first end of the fourth resistor R4 and is connected with the third input end Vbn of the pre-amplifier 2; the second end of the third capacitor C3 and the second end of the first resistor R1 are connected with the grid electrode of the first PMOS tube MP 1; the second end of the fourth capacitor C4 and the second end of the second resistor R2 are connected with the grid electrode of the first NMOS tube Mn 1; the second end of the fifth capacitor C5 and the second end of the third resistor R3 are connected with the grid electrode of the second PMOS tube MP 2; the second end of the sixth capacitor C6 and the second end of the fourth resistor R4 are connected with the grid electrode of the second NMOS tube Mn 2; the drain electrode of the first PMOS tube MP1 is connected with the drain electrode of the first NMOS tube Mn1 and is connected with the first output end Von of the pre-amplifier; the drain electrode of the second PMOS tube MP2 is connected with the drain electrode of the second NMOS tube Mn2 and is connected with the second output end Vop of the pre-amplifier 2; the grid electrode and the drain electrode of the third NMOS tube Mn3 are connected with the grid electrode of the fourth NMOS tube Mn4 and are connected with the fourth input end Vb of the pre-amplifier, the source electrodes of the first PMOS tube MP1 to the third PMOS tube MP3 are all connected with a power supply, and the source electrodes of the first NMOS tube Mn1 to the fourth NMOS tube Mn4 are all grounded.

In this embodiment, the resistance values of the first resistor R1 to the fourth resistor R4 are equal in magnitude; the capacitance values of the third capacitor C3 to the sixth capacitor C6 are equal.

In this embodiment, the first input signal Vxp of the preamplifier 2 is connected to the gate of the first PMOS transistor Mp1 through the third capacitor C3 and the first resistor R1, and the fourth capacitor C4 and the second resistor R2 are connected to the gate of the first NMOS transistor Mn 1; because the sum of the threshold voltages of the first PMOS transistor Mp1 and the first NMOS transistor Mn1 is greater than the power supply voltage at the low power supply voltage, the direct connection of the input signal to the input transistor cannot ensure that the first PMOS transistor and the first NMOS transistor are simultaneously in the saturation region. This inverter-based preamplifier architecture can be guaranteed to operate properly even at low supply voltages by amplifying the input signal after "splitting". The dc bias voltage Vbp of the PMOS transistor is generated by a fixed current flowing through the third PMOS transistor Mp3, and the dc bias voltage Vbn of the NMOS transistor is generated by the common mode feedback circuit.

Referring to fig. 4, fig. 4 shows a schematic structure of the common mode feedback circuit 3. As shown in fig. 4, the common mode feedback circuit 3 includes a common mode detection module 31, a charge sharing module 32, and a buffer module 33, which are sequentially connected; wherein an input terminal of the common mode detection module 31 is connected to an output terminal of the pre-amplifier 2, and an output terminal of the buffer module 33 is connected to the third input terminal Vbn of the pre-amplifier 2.

Referring to fig. 5, fig. 5 shows a circuit diagram of the common mode detection module 31. As shown in fig. 5, the common-mode detection module 31 adopts a dynamic comparator structure, wherein a first input end and a second input end of the common-mode detection module are respectively connected with a first output end Vop and a second output end Von of the pre-amplifier 2, and a third input end and a fourth input end of the common-mode detection module 31 are connected with a reference voltage signal Vcm for detecting the relative magnitudes of the common-mode voltage signal output by the pre-amplifier 2 and the reference voltage signal Vcm; the relative magnitude relation between the output common-mode voltage signal of the pre-amplifier 2 and the reference voltage signal can be obtained according to the high-low level relation between the first output terminal din and the second output terminal dip of the common-mode detection module 31. The common mode detection module adopts the existing dynamic comparator circuit structure, and is not described herein again.

Referring to fig. 6, fig. 6 shows a circuit diagram of the charge sharing module 32 and the buffer module 33. As shown in fig. 6, the buffer module adopts a conventional buffer circuit structure, which is not described herein. The charge sharing module 32 includes: seventh to ninth capacitances C7 to C9, tenth PMOS transistor Mp10, eleventh PMOS transistor Mp11, sixteenth NMOS transistor Mn16, seventeenth NMOS transistor Mn17, and inverter inv; the gate of the tenth PMOS transistor Mp10 is connected to the gate of the sixteenth NMOS transistor Mn16 and to the first output terminal of the common mode detection module 31 (i.e., the first input terminal din of the charge sharing module 32); a second output terminal of the common mode detection module 31 (i.e., the second input terminal dip of the charge sharing module 32) is connected to an input terminal of the inverter inv; the output end of the inverter inv is connected with the grid electrode of the eleventh PMOS tube MP11 and the grid electrode of the seventeenth NMOS tube Mn 17; the drain electrode of the tenth PMOS tube Mp10 and the drain electrode of the sixteenth NMOS tube Mn16 are connected with the first end of the seventh capacitor C7; the drain electrode of the eleventh PMOS tube Mp11 and the drain electrode of the seventeenth NMOS tube Mn17 are connected with the first end of the eighth capacitor C8; the source of the sixteenth PMOS transistor Mp16 and the source of the eleventh NMOS transistor Mn11 are connected to the first end of the ninth capacitor C9, and are connected to the output end Vcmfb of the charge sharing module 32; the source electrode of the tenth PMOS tube Mp10 is connected with the power supply voltage, the source electrode of the seventeenth NMOS tube Mn17 is grounded, and the second ends of the seventh capacitor C7, the eighth capacitor C8 and the ninth capacitor C9 are grounded.

In this embodiment, the capacitance values of the seventh capacitor C7 and the eighth capacitor C8 are equal in magnitude.

In this embodiment, the charge sharing module 32 determines the magnitude relation of the output signal Vcmfb of the present period with respect to the previous period through the first input signal din and the second input signal dip; when the common mode detection module 31 is in a reset state, the first input signal din and the second input signal dip of the charge sharing module 32 are at low level, the seventh capacitor C7 is reset to a power supply voltage, and the eighth capacitor C8 is reset to a ground voltage; when the common mode detection module 31 is in a comparison state, the first input signal din of the charge sharing module 32 is at a high level, the second input signal dip is at a low level, the eighth capacitor C8 is reset to a ground voltage, the charges of the seventh capacitor C7 and the ninth capacitor C9 are shared, and the output signal Vcmfb of the charge sharing module 32 is raised relative to the previous period; when the common mode detection module 31 is in another comparison state, the first input signal din of the charge sharing module is low, the second input signal dip is high, the seventh capacitor C7 is reset to the power supply voltage, the charges of the eighth capacitor C8 and the ninth capacitor C9 are shared, and the output signal Vcmfb of the charge sharing module 32 is reduced with respect to the previous period.

To further demonstrate the effectiveness of the pre-amplifier circuit for a low supply voltage SAR ADC of the present invention, the following simulation experiments were performed. The simulation experiment adopts a dynamic circuit simulation technology, and in Cadence simulation software, a 28nm CMOS technology is adopted, and a common mode interference signal with the frequency of 100MHz and the amplitude of 100mV is added into an input voltage. The results of the simulation experiment are shown in fig. 7.

Fig. 7 shows an eye diagram waveform diagram of 200 cycles of a common-mode voltage signal of a first differential signal of a conventional bottom plate sampling circuit, and an eye diagram waveform diagram of 200 cycles of a common-mode voltage signal of a first differential signal of the improved sampling circuit; the comparison result shows that the bottom plate sampling circuit cannot restrain common mode jitter in the input signal, and common mode components in the input differential signal are transmitted to the first differential signal almost without attenuation; the first differential signal of the improved sampling circuit has little common-mode signal jitter except for the kick noise of the rear comparator, and can well inhibit the high-frequency common-mode gain from the differential input signal to the output of the pre-amplifier.

In summary, the pre-amplifier circuit for the low supply voltage SAR ADC provided by the present invention realizes an inverter-based pre-amplifier structure suitable for low supply voltage by performing a "split" input on an input signal and providing a common mode feedback circuit to the output of the pre-amplifier; meanwhile, by improving the sampling circuit, the common mode gain of the input signal to the output signal of the pre-amplifier is restrained from being too high under high frequency, the problem that the common mode gain of the pre-amplifier is difficult to be reduced in a transistor-level circuit under low power supply voltage is solved, and the stability of the input signal of the post-level dynamic comparator is improved. Meanwhile, the implementation mode of the common mode feedback circuit provided by the invention has better feasibility.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (10)

1. A pre-amplifier circuit for a low supply voltage SAR ADC, comprising:

The improved sampling circuit is used for sampling the input differential signal to obtain a first differential signal;

The input end of the preamplifier is connected with the output end of the improved sampling circuit and is used for amplifying the first differential signal to obtain a second differential signal; and

And the input end of the common mode feedback circuit is connected with the output end of the pre-amplifier, outputs a feedback signal to the pre-amplifier, is used for detecting the common mode signal of the second differential signal, and carries out feedback processing on the second differential signal based on a reference voltage so as to adjust the second differential signal to enable the transistor in the pre-amplifier to be in a normal working state.

2. The pre-amplifier circuit for a low supply voltage SAR ADC of claim 1, wherein said modified sampling circuit comprises: a first capacitor C1, a second capacitor C2, first to fifth bootstrap switches K1 to K5, a sixth switch K6, and a seventh switch K7; a first end of the first bootstrap switch K1 is connected with the second input end Vin, a first end of the second bootstrap switch K2 is connected with the first input end Vip, and first ends of the third bootstrap switch K3, the fourth bootstrap switch K4, the sixth switch K6 and the seventh switch K7 are connected with the reference voltage Vcm; the second end of the first bootstrap switch K1 and the second end of the sixth switch K6 are connected to the first end of the first capacitor C1; the second end of the second bootstrap switch K2 and the second end of the seventh switch K7 are connected to the first end of the second capacitor C2; the second end of the first capacitor C1 and the second end of the third bootstrap switch K3 are connected with the first end of the fifth bootstrap switch K5 and are connected with the second output end Vxn of the improved sampling circuit; the second end of the second capacitor C2 and the second end of the fourth bootstrap switch K4 are connected to the second end of the fifth bootstrap switch K5, and are connected to the first output end Vxp of the improved sampling circuit; the control ends of the first bootstrap switch K1 and the second bootstrap switch K2 are connected to a first clock signal clk1; the control ends of the third bootstrap switch K3 and the fourth bootstrap switch K4 are connected to a second clock signal clk2; the control end of the fifth bootstrap switch K5 is connected to a third clock signal clk3; the control ends of the sixth switch K6 and the seventh switch K6 are connected to a fourth clock signal clk4.

3. The pre-amplifier circuit for a low supply voltage SAR ADC according to claim 2, wherein the first capacitor C1 and the second capacitor C2 have equal capacitance values; the first bootstrap switch K1 and the second bootstrap switch K2 are equal in size; the third bootstrap switch K3 and the fourth bootstrap switch K4 are equal in size;

The sixth switch K6 and the seventh switch K7 are equal in size.

4. The pre-amplifier circuit for a low supply voltage SAR ADC according to claim 2, wherein the first clock signal clk1 to the fourth clock signal clk4 are equal in frequency, wherein the first rising edges of the second clock signal clk2, the third clock signal clk3 and the fourth clock signal clk4 coincide, wherein the falling edges of the second clock signal clk2, the fourth clock signal clk4 and the rising edges of the first clock signal clk1 coincide, and wherein the falling edges of the first clock signal clk1 follow the falling edges of the third clock signal clk3 and precede the second rising edges of the fourth clock signal clk 4.

5. The pre-amplifier circuit for a low supply voltage SAR ADC of claim 2, wherein said pre-amplifier has four inputs and two outputs, wherein a first input and a second input of said pre-amplifier are for switching in said first differential signal; the third input end of the pre-amplifier is used for accessing the feedback signal; the fourth input end of the pre-amplifier is used for being connected with a bias voltage signal; the first output end and the second output end of the pre-amplifier are used for outputting the second differential signal.

6. The pre-amplifier circuit for a low supply voltage SAR ADC of claim 5, wherein said pre-amplifier comprises: the first to fourth resistors R1 to R4, the third to sixth capacitors C3 to C6, the first to third PMOS tubes Mp1 to Mp3, and the first to fourth NMOS tubes Mn1 to Mn4; the first end of the third capacitor C3 is connected to the first end of the fourth capacitor C4, and is connected to the first output end Vxp of the improved sampling circuit; a first end of the fifth capacitor C5 is connected to a first end of the sixth capacitor C6, and is connected to the second output end Vxn of the improved sampling circuit; the first end of the first resistor R1, the first end of the third resistor R3 and the drain electrode of the fourth NMOS tube Mn4 are connected with the grid electrode and the drain electrode of the third PMOS tube MP 3; the first end of the second resistor R2 is connected with the first end of the fourth resistor R4 and is connected with the third input end Vbn of the pre-amplifier, namely the feedback signal; the second end of the third capacitor C3 and the second end of the first resistor R1 are connected with the grid electrode of the first PMOS tube MP 1; the second end of the fourth capacitor C4 and the second end of the second resistor R2 are connected with the grid electrode of the first NMOS tube Mn 1; the second end of the fifth capacitor C5 and the second end of the third resistor R3 are connected with the grid electrode of the second PMOS tube MP 2; the second end of the sixth capacitor C6 and the second end of the fourth resistor R4 are connected with the grid electrode of the second NMOS tube Mn 2; the drain electrode of the first PMOS tube MP1 is connected with the drain electrode of the first NMOS tube Mn1 and is connected with the first output end Von of the pre-amplifier; the drain electrode of the second PMOS tube MP2 is connected with the drain electrode of the second NMOS tube Mn2 and is connected with the second output end Vop of the pre-amplifier; the grid electrode and the drain electrode of the third NMOS tube Mn3 are connected with the grid electrode of the fourth NMOS tube Mn4 and are connected with the fourth input end Vb of the pre-amplifier, the sources of the first PMOS tube MP1 to the third PMOS tube MP3 are all connected with a power supply, and the sources of the first NMOS tube Mn1 to the fourth NMOS tube Mn4 are all grounded.

7. The preamplifier circuit for a low supply voltage SAR ADC according to claim 5, wherein the resistances of the first to fourth resistors R1 to R4 are equal in magnitude; the capacitance values of the third to sixth capacitances C3 to C6 are equal in magnitude.

8. The pre-amplifier circuit for a low supply voltage SAR ADC of claim 5, wherein said common mode feedback circuit comprises:

The first input end and the second input end of the common mode detection module are respectively and correspondingly connected with the first output end and the second output end of the pre-amplifier, the third input end is connected with a reference voltage signal, the clock signal control end is connected with a common mode detection clock signal, and the common mode detection module is used for comparing the first differential signal with the reference voltage signal based on the common mode detection clock signal to obtain a comparison result signal;

The input end of the charge sharing module is connected with the output end of the common mode detection module, and the charge sharing module is used for receiving the comparison result signal output by the common mode detection module and carrying out charge sharing with the last feedback signal according to the comparison result signal to obtain the feedback signal; and

And the buffer module is connected between the charge sharing module and the input end of the pre-amplifier, and is used for receiving the feedback signal output by the charge sharing module and outputting the feedback signal to the third input end of the pre-amplifier.

9. The pre-amplifier circuit for a low supply voltage SAR ADC of claim 8, wherein said charge sharing module comprises: seventh to ninth capacitances C7 to C9, tenth PMOS transistor Mp10, eleventh PMOS transistor Mp11, sixteenth NMOS transistor Mn16, seventeenth NMOS transistor Mn17, and inverter inv; the gate of the tenth PMOS Mp10 is connected to the gate of the sixteenth NMOS Mn16, and is connected to the first output terminal of the common mode detection module 31; a second output end of the common mode detection module 31 is connected with an input end of the inverter inv; the output end of the inverter inv is connected with the grid electrode of the eleventh PMOS tube MP11 and the grid electrode of the seventeenth NMOS tube Mn 17; the drain electrode of the tenth PMOS tube Mp10 and the drain electrode of the sixteenth NMOS tube Mn16 are connected with the first end of the seventh capacitor C7; the drain electrode of the eleventh PMOS tube Mp11 and the drain electrode of the seventeenth NMOS tube Mn17 are connected with the first end of the eighth capacitor C8; the source of the sixteenth PMOS transistor Mp16 and the source of the eleventh NMOS transistor Mn11 are connected to the first end of the ninth capacitor C9, and are connected to the output end Vcmfb of the charge sharing module 32; the source electrode of the tenth PMOS tube MP10 is connected with a power supply, the source electrode of the seventeenth NMOS tube Mn17 is grounded, and the second ends of the seventh to ninth capacitors C7 to C9 are grounded.

10. The pre-amplifier circuit for a low supply voltage SAR ADC according to claim 9, wherein said seventh capacitor C7 and said eighth capacitor C8 have equal capacitance values.