CN118971854B - A monolithic integrated overvoltage protection power switch - Google Patents
A monolithic integrated overvoltage protection power switch Download PDFInfo
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- CN118971854B CN118971854B CN202411440958.2A CN202411440958A CN118971854B CN 118971854 B CN118971854 B CN 118971854B CN 202411440958 A CN202411440958 A CN 202411440958A CN 118971854 B CN118971854 B CN 118971854B
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- power switch
- switch tube
- surge
- vdmos
- vdmos1
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- 238000001514 detection method Methods 0.000 claims abstract description 33
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 19
- 239000010703 silicon Substances 0.000 claims abstract description 19
- 239000002184 metal Substances 0.000 claims abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 13
- 238000007599 discharging Methods 0.000 claims description 9
- 238000000407 epitaxy Methods 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 description 11
- 238000010586 diagram Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000000284 extract Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
- H03K17/08104—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a monolithic integrated overvoltage protection power switch, which comprises a main power switch tube, a surge relief power switch tube, a switch grid control circuit, a surge detection circuit, an input end and an output end, wherein the grid of the main power switch tube is controlled by the switch grid control circuit, the drain electrode of the main power switch tube is connected with the drain electrode and the input end of the surge relief power switch tube, the grid of the surge relief power switch tube is controlled by the surge detection circuit, the main power switch tube and the surge relief power switch tube are of a longitudinal DMOS structure, and the drain electrodes of the main power switch tube and the surge relief power switch tube are in metal short circuit through the back surface of a silicon chip. The invention realizes the power switch tube with ultralow on-resistance and the surge protection tube with higher grade.
Description
Technical Field
The invention relates to a power switch, in particular to a monolithic integrated overvoltage protection power switch, and belongs to the technical field of semiconductor integrated circuits.
Background
Electrical overstress is currently the primary cause of device failure in integrated circuit chips. Particularly, the chip pins directly connected with the external ports of the system are very easy to be impacted by various electric overstresses, the generation factors of the electric overstresses include unstable power supply output, various overvoltage, noise of overcurrent, surge current during hot plug application, moisture or mechanical error short circuit phenomenon, static electricity release and the like, and special attention is paid to the electric overstress protection of the chip pins connected with the interface of the system. At present, a main method for protecting the electric overstress of a chip is to add a discrete surge protection device such as a transient voltage suppression diode (TVS) on a system circuit board outside the chip for electric overstress protection, wherein the external discrete protection device is a functional device for realizing electric overstress protection clamping leakage current, and has strong clamping voltage and current leakage capability. However, under the trend of light and thin mobile terminals, the integrated circuit overstress protection function omits an external voltage clamping device, and the realization of the maximum integration is a main research direction of interface chips, and especially in some existing primary protection systems, the requirements can be met only by the residual voltage overstress protection capability of the chip interface after primary protection.
The idea of the prior art is that a high-voltage LDMOS switch tube is adopted as a high-voltage power switch, another high-voltage LDMOS is adopted as a surge relief tube, the drain electrode of the LDMOS of the surge relief tube and the drain electrode of the high-voltage power switch are connected together at an input end, a grid electrode is controlled by a surge detection circuit, and an overshoot detection circuit module is utilized to control the opening of a clamping protection tube, so that voltage clamping is realized, system ESD and surge pulse energy are released, and the protection function of the internal switch tube is further realized. As shown in FIG. 4, the reference 1-a is the Input terminal, the reference 6-a is the Output terminal, the reference 2-a is the LDMOS power switch tube in the plane BCD, the drain electrode is connected with 1-a, the source electrode is connected with 6-a, and the grid electrode is controlled by a switch grid electrode control circuit which is referenced as 4-a. And 3-a is a surge relief power switch tube between the input 1-a and the substrate ground GND, the drain electrode is connected with 1-a, the source electrode is connected with the substrate ground GND, and the grid electrode is controlled by a surge detection circuit 5-a.
A major drawback with this approach is that it is difficult to achieve low on-resistance power switches, such as switches under 10 milliohms, and greater surge protection capability, by pulling the source and drain from the surface. The reason is that for the LDMOS in the horizontal plane, the drain electrode and the source electrode are both on the surface of the silicon wafer, an interdigital layout method is needed, and the parasitic resistance of the metal wiring is increased along with the increase of the interdigital number fn of the NLDMOS and the width W of a single interdigital, so that the occupation ratio is larger and larger, and further the further reduction of the on-resistance is limited.
Disclosure of Invention
The invention aims to solve the technical problem of providing a monolithic integrated overvoltage protection power switch for realizing ultralow on-resistance.
In order to solve the technical problems, the invention adopts the following technical scheme:
The utility model provides a monolithic integrated overvoltage protection power switch, include main power switch tube VDMOS1, surge bleeder power switch tube VDMOS2, switch grid control circuit, surge detection circuit, input and Output, the grid of main power switch tube VDMOS1 is connected by switch grid control circuit with switch grid control circuit's Output, main power switch tube VDMOS 1's source and Output are connected, main power switch tube VDMOS 1's drain electrode and surge bleeder power switch tube VDMOS 2's drain electrode and Input are connected, surge bleeder power switch tube VDMOS 2's grid is connected by surge detection circuit with surge detection circuit's Output, surge bleeder power switch tube VDMOS 2's source ground, main power switch tube VDMOS1, surge bleeder power switch tube VDMOS2 all is vertical DMOS structure and main power switch tube VDMOS1, the drain electrode of surge bleeder power switch tube VDMOS2 is through the back metal short circuit of silicon chip, main power switch tube VDMOS1, surge power switch tube VDMOS2, switch grid control circuit, surge detection circuit is integrated on single chip.
Further, the Input end of the switch grid control circuit and the Input end of the surge detection circuit are connected with the Input end Input.
Further, the grounding terminal of the surge detection circuit is grounded.
Further, the main power switch tube VDMOS1 and the surge relief power switch tube VDMOS2 are arranged on two sides of the switch grid control circuit and the surge detection circuit in layout arrangement.
Further, the main power switch tube VDMOS1 and the surge discharging power switch tube VDMOS2 are annularly arranged around the periphery of the switch grid control circuit and the periphery of the surge detection circuit in layout arrangement.
Further, the main power switch tube VDMOS1 and the surge discharging power switch tube VDMOS2 are respectively formed by connecting a plurality of VDMOS tubes in parallel.
Further, each of the VDMOS tubes includes a heavily doped N-type silicon substrate, a back metal electrode layer, an Input terminal Input pin, a source pin, an N-type epitaxy, a trench of a VDMOS terminal junction, a shield gate lead-out polysilicon, a trench of a VDMOS unit region, a source of the VDMOS, a back gate lead-out polysilicon, and a gate polysilicon of the VDMOS, the back metal electrode layer is disposed on a lower side of the heavily doped N-type silicon substrate, the Input terminal Input pin is disposed on the back metal electrode layer, the N-type epitaxy is disposed on an upper side of the heavily doped N-type silicon substrate, the trench of the VDMOS terminal junction and the trench of the VDMOS unit region are disposed on an upper surface of the N-type epitaxy, the shield gate lead-out polysilicon is disposed in the trench of the VDMOS terminal junction, the source of the VDMOS and the back gate lead-out polysilicon are disposed in the trench of the VDMOS unit region, the source of the VDMOS is disposed on an upper surface of the N-type epitaxy, and the pin is connected to the source and the back gate of the VDMOS tube.
Compared with the prior art, the single-chip integrated overvoltage protection power switch has the advantages that the single-chip integrated overvoltage protection power switch is provided, the main power switch tube and the surge discharging power tube are both longitudinally realized by the high-voltage MOS tube on the silicon wafer, and because the drain electrodes of the main power switch tube and the surge discharging power tube are all arranged on the back surface of the silicon wafer, the influence of metal interconnection between the drain and the source of the LDMOS in the existing planar BCD on the limitation of the overvoltage resistor is eliminated, so that the power switch tube with ultra-low on resistance and the surge protection tube with higher grade can be realized. Meanwhile, as the upper surface and the lower surface of the silicon wafer are covered with metal, the thermal resistance is reduced, and the area efficiency of surge protection is greatly improved.
Drawings
Fig. 1 is a schematic diagram of a monolithically integrated overvoltage protection power switch according to the present invention.
Fig. 2 is a schematic diagram of layout of a monolithically integrated overvoltage protection power switch according to the present invention.
Fig. 3 is a cross-sectional view in the A-A direction of the layout of a monolithically integrated overvoltage protection power switch according to the present invention.
Fig. 4 is a schematic diagram of a prior art single chip integrated overvoltage protection load switch.
Detailed Description
In order to explain in detail the technical solutions adopted by the present invention to achieve the predetermined technical purposes, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, but not all embodiments, and that technical means or technical features in the embodiments of the present invention may be replaced without inventive effort, and the present invention will be described in detail below with reference to the accompanying drawings in combination with the embodiments.
As shown in FIG. 1, the monolithic integrated overvoltage protection power switch of the invention comprises a main power switch tube VDMOS1, a surge discharge power switch tube VDMOS2, a switch grid control circuit, a surge detection circuit, an Input end and an Output end, wherein the grid of the main power switch tube VDMOS1 is connected with the Output end of the switch grid control circuit and controlled by the switch grid control circuit, the source electrode of the main power switch tube VDMOS1 is connected with the Output end, the drain electrode of the main power switch tube VDMOS1 is connected with the drain electrode of the surge discharge power switch tube VDMOS2 and the Input end, the grid of the surge relief power switch tube VDMOS2 is connected with the Output end of the surge detection circuit and controlled by the surge detection circuit, the source electrode of the surge relief power switch tube VDMOS2 is grounded, the main power switch tube VDMOS1 and the surge relief power switch tube VDMOS2 are of a longitudinal DMOS structure, the drain electrodes of the main power switch tube VDMOS1 and the surge relief power switch tube VDMOS2 are in metal short circuit through the back surface of a silicon chip, and the main power switch tube VDMOS1, the surge relief power switch tube VDMOS2, the switch grid control circuit and the surge detection circuit are integrated on a single chip.
The invention can realize ultralow on-resistance, such as an ultralow on-resistance power switch below 10mohm, and can realize surge protection capability of 100V-300V and above according to application requirements.
The Input end of the switch grid control circuit and the Input end of the surge detection circuit are connected with the Input end Input. The ground of the surge detection circuit is grounded.
In one embodiment of the present invention, as shown in fig. 2, the main power switching transistor VDMOS1 and the surge bleed power switching transistor VDMOS2 are located on both sides of the switching gate control circuit and the surge detection circuit in layout arrangement.
In another embodiment of the present invention, the main power switch tube VDMOS1 and the surge bleed power switch tube VDMOS2 are annularly arranged around the periphery of the switch gate control circuit and the surge detection circuit in layout arrangement.
The main power switch tube VDMOS1 and the surge discharging power switch tube VDMOS2 are respectively formed by connecting a plurality of VDMOS tubes in parallel.
As shown in fig. 3, each VDMOS tube includes a heavily doped N-type silicon substrate 1, a back metal electrode layer 2, an Input terminal Input pin 31, a source pin, an N-type epi 3, a trench 4 of a VDMOS terminal junction, a shield gate lead-out polysilicon 5, a trench 22 of a VDMOS unit region, a source 10 of the VDMOS, a back gate lead-out 6, and a gate polysilicon 7 of the VDMOS, the back metal electrode layer 2 is disposed on the lower side of the heavily doped N-type silicon substrate 1, the Input terminal Input pin 31 is disposed on the back metal electrode layer 2, the N-type epi 3 is disposed on the upper side of the heavily doped N-type silicon substrate 1, the trench 4 of the VDMOS terminal junction and the trench 22 of the VDMOS unit region are disposed on the upper surface of the N-type epi 3, the shield gate lead-out polysilicon 5 is disposed in the trench 4 of the VDMOS terminal junction, the source 10 and the back gate lead-out 6 of the VDMOS are disposed on the upper surface of the N-type epi 3, the gate polysilicon 7 and the shield gate 9 of the VDMOS are disposed in the trench 22 of the VDMOS unit region and the gate polysilicon 7 of the VDMOS is disposed on the upper surface of the back gate 3, the back gate 3 is disposed on the back gate polysilicon 3, and the drain terminal of the VDMOS is connected to the drain pin of the power drain of the VDMOS and the drain transistor is connected to the drain of the power drain of the main transistor, the drain is connected to the drain of the source drain transistor, the drain transistor is connected to the drain transistor, the drain of the drain transistor is connected to the drain transistor.
The grids of the main power switch tube VDMOS1 and the surge discharging power switch tube VDMOS2 are driven by a grid control circuit and a surge detection circuit respectively on the front side of the silicon wafer, the front side is isolated from a high-voltage N-type substrate by a deep P well, and the grid control circuit and the surge detection circuit are formed in a deep P well area on the front side of the silicon wafer. The main power switch tube VDMOS1 and the surge discharging power switch tube VDMOS2 are respectively provided with a terminal ring at the front surface of the chip and at the source electrode and the grid electrode area, and the N-type epitaxy outside the terminal rings can lead out drain electrode potential from the front surface for realizing the detection function of the circuit.
The main power switch tube VDMOS1 and the surge discharging power switch tube VDMOS2 can be of a common groove structure, can be MOSFET of SGT (SPLIT GATE split gate) or (SHIELDING GATE) groove structure, and can be groove MOSFET of other structures.
As shown in fig. 3, the switch gate control circuit includes a P-well isolation 11, a cathode 12 of the zener diode, an anode 13 of the zener diode, a P-well 14 of the CMOS, an N-well 16 of the PMOS, a Poly gate 15 of the PMOS, a Poly gate 17 of the NMOS, a P-well 18 of the NMOS, a P-well potential extraction 19, an n+ well region 20 that extracts the backside drain (i.e., at Input pin 31) potential, and an N-well region 21 that extracts the backside drain potential. The cathode 12 of the zener, the anode 13 of the zener can be formed by the n+ and P back gates of the VDMOS. The specific circuit principles of the switch gate control circuit and the surge detection circuit and the chip layout structure are the prior art, so that the description is omitted.
The invention provides a monolithic integrated overvoltage protection power switch, which is realized by adopting a VDMOS BCD process platform based on a longitudinal direction, so that the metal interconnection parasitic resistance limit of LDMOS of a surface structure is eliminated, and the upper and lower metal electrodes of a power switch tube and a thinner substrate of a current path of the longitudinal structure enhance the heat dissipation performance, thereby greatly improving the power processing capacity of a single chip. Further, a high-power switch and a surge protection tube (a surge protection capability of 100V or more with higher area efficiency) with ultra-low on-resistance (10 mohm or less) can be realized.
The self-protection circuit is particularly suitable for chips with larger areas of power switching tubes of the chips, and realizes the self-protection function of electric overstress which does not occupy surface area and provides considerable system ESD and EOS surge. The transient voltage suppression diode outside the chip is saved, the system board area is saved, the area of the chip is not increased, and the integrated protection innovation scheme for solving the problem of electric overstress protection is very high in efficiency and low in cost.
The present invention is not limited to the preferred embodiments, and the present invention is described above in any way, but is not limited to the preferred embodiments, and any person skilled in the art will appreciate that the present invention is not limited to the embodiments described above, while the invention has been described with respect to specific examples including presently preferred modes of carrying out the invention, those skilled in the art will appreciate that there are numerous variations and permutations of the above described embodiments that fall within the spirit and scope of the invention as set forth in the appended claims.
Claims (5)
1. A monolithic integrated overvoltage protection power switch is characterized by comprising a main power switch tube VDMOS1, a surge discharge power switch tube VDMOS2, a switch grid control circuit, a surge detection circuit, an Input end and an Output end, wherein the grid electrode of the main power switch tube VDMOS1 is connected with the Output end of the switch grid control circuit and controlled by the switch grid control circuit, the source electrode of the main power switch tube VDMOS1 is connected with the Output end, the drain electrode of the main power switch tube VDMOS1 is connected with the drain electrode of the surge discharge power switch tube VDMOS2 and the Input end, the grid electrode of the surge discharge power switch tube VDMOS2 is connected with the Output end of the surge detection circuit and controlled by the surge detection circuit, the source electrodes of the surge discharge power switch tube VDMOS2 are grounded, the main power switch tube VDMOS1 and the surge discharge power switch tube VDMOS2 are of a longitudinal DMOS structure, the drain electrodes of the main power switch tube VDMOS1 and the surge discharge power switch tube VDMOS2 are in short circuit through silicon chip back metal, and the main power switch tube VDMOS1, the surge power switch tube VDMOS2 and the surge power switch grid control circuit and the surge detection circuit are arranged on a single chip;
The main power switch tube VDMOS1 and the surge discharging power switch tube VDMOS2 are respectively formed by connecting a plurality of VDMOS tubes in parallel;
Each VDMOS tube comprises a heavily doped N-type silicon substrate, a back metal electrode layer, an Input end Input pin, a source electrode pin, an N-type epitaxy, a groove of a VDMOS terminal junction, shielding grid lead-out polycrystalline silicon, a groove of a VDMOS unit area, a source electrode of the VDMOS, a back grid lead-out polycrystalline silicon and grid polycrystalline silicon of the VDMOS, wherein the back metal electrode layer is arranged on the lower side of the heavily doped N-type silicon substrate, the Input end Input pin is arranged on the back metal electrode layer, the N-type epitaxy is arranged on the upper side of the heavily doped N-type silicon substrate, the groove of the VDMOS terminal junction and the groove of the VDMOS unit area are arranged on the upper surface of the N-type epitaxy, the shielding grid lead-out polycrystalline silicon is arranged in the groove of the VDMOS terminal junction, the source electrode and the back grid lead-out polycrystalline silicon of the VDMOS are arranged in the groove of the VDMOS unit area, the grid polycrystalline silicon of the VDMOS is arranged on the upper surface of the N-type epitaxy, and the source electrode pin is connected with the source electrode and the back polycrystalline silicon of the VDMOS tube.
2. The monolithically integrated overvoltage protection power switch of claim 1 wherein said switch gate control circuit Input and said surge detection circuit Input are connected to an Input.
3. A monolithically integrated overvoltage protection power switch according to claim 1, wherein the ground of said surge detection circuit is grounded.
4. A monolithically integrated overvoltage protection power switch according to claim 1, wherein the main power switch tube VDMOS1 and the surge bleed power switch tube VDMOS2 are located on both sides of the switch gate control circuit and the surge detection circuit in layout arrangement.
5. The monolithically integrated overvoltage protection power switch of claim 1, wherein the main power switch tube VDMOS1 and the surge bleed power switch tube VDMOS2 are arranged in a circular pattern around the periphery of the switch gate control circuit and the surge detection circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411440958.2A CN118971854B (en) | 2024-10-16 | 2024-10-16 | A monolithic integrated overvoltage protection power switch |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411440958.2A CN118971854B (en) | 2024-10-16 | 2024-10-16 | A monolithic integrated overvoltage protection power switch |
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| CN118971854A CN118971854A (en) | 2024-11-15 |
| CN118971854B true CN118971854B (en) | 2024-12-24 |
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| CN202411440958.2A Active CN118971854B (en) | 2024-10-16 | 2024-10-16 | A monolithic integrated overvoltage protection power switch |
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114420759A (en) * | 2022-02-23 | 2022-04-29 | 江苏帝奥微电子股份有限公司 | An NLDMOS device with integrated overvoltage protection diode |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4872141B2 (en) * | 1999-10-28 | 2012-02-08 | 株式会社デンソー | Power MOS transistor |
| CN105141134B (en) * | 2014-05-26 | 2019-06-14 | 中兴通讯股份有限公司 | A kind of Switching Power Supply and the method for controlling the Switching Power Supply |
| CN112993953B (en) * | 2021-02-26 | 2023-06-06 | 西安微电子技术研究所 | High-voltage surge suppression circuit |
| CN214850475U (en) * | 2021-06-25 | 2021-11-23 | 上海音特电子有限公司 | Protection circuit of USB PD |
| CN117526255A (en) * | 2023-11-10 | 2024-02-06 | 珠海市杰理科技股份有限公司 | Protection circuit and electric equipment |
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Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114420759A (en) * | 2022-02-23 | 2022-04-29 | 江苏帝奥微电子股份有限公司 | An NLDMOS device with integrated overvoltage protection diode |
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