CN118969739A

CN118969739A - Semiconductor packaging structure

Info

Publication number: CN118969739A
Application number: CN202411438306.5A
Authority: CN
Inventors: 李文源; 张朋; 李学宝; 金锐; 崔翔; 李哲洋; 赵志斌; 郑超
Original assignee: Beijing Smart Energy Research Institute; Beijing Huairou Laboratory; North China Electric Power University
Current assignee: Beijing Smart Energy Research Institute; Beijing Huairou Laboratory; North China Electric Power University
Priority date: 2024-10-15
Filing date: 2024-10-15
Publication date: 2024-11-15
Anticipated expiration: 2044-10-15

Abstract

The present invention provides a semiconductor packaging structure, wherein the semiconductor packaging structure comprises: a packaging shell, comprising a substrate and a panel connected to the substrate; a semiconductor chip connected to the substrate; a first terminal connected to a first side of the semiconductor chip; a second terminal connected to a second side of the semiconductor chip; an insulating reinforcement portion connected to the panel, the insulating reinforcement portion comprising a first insulating reinforcement rib and a second insulating reinforcement rib, the first insulating reinforcement rib being arranged between the first terminal and the second terminal, the two ends of the second insulating reinforcement rib being respectively connected to two opposite inner surfaces of the panel, the first insulating reinforcement rib and the second insulating reinforcement rib being intersected and connected. The technical solution of the present application can effectively solve the problem that it is difficult to take both the insulation performance and the structural strength of the housing into account in the related art.

Description

Semiconductor packaging structure

Technical Field

The invention relates to the technical field of semiconductors, in particular to a semiconductor packaging structure.

Background

With the continuous development of science and technology, the application range of semiconductor devices is wider and wider, for example, the semiconductor devices can be used as rectifiers, oscillators, light emitters, amplifiers or photometers and the like in the fields of radio frequency, microwave and optical semiconductor products.

In the art, power semiconductor devices generally include a housing, a substrate, and a power semiconductor chip (e.g., a silicon carbide chip); the housing and the substrate form a mounting cavity, the power semiconductor chip is arranged in the mounting cavity, the power semiconductor chip generally comprises a source electrode and a drain electrode, when the power semiconductor device works, a larger voltage difference exists between the source electrode and the drain electrode, and therefore, higher requirements on the insulation performance of the housing and the substrate are required, generally, grooves are formed in the housing to increase the surface distance between the source electrode and the drain electrode or between a source terminal and a drain terminal, so that the insulation performance of the housing is enhanced, but the structural strength of the housing is more or less adversely affected.

Disclosure of Invention

The invention mainly aims to provide a semiconductor packaging structure for solving the problem that the insulating performance and the structural strength of a shell in the related art are difficult to be compatible.

In order to achieve the above object, the present invention provides a semiconductor package structure including: the packaging shell comprises a substrate and a coaming connected with the substrate; a semiconductor chip connected to the substrate; a first terminal connected to a first side of the semiconductor chip; a second terminal connected to a second side of the semiconductor chip; the insulating reinforcing part is connected with the coaming, and the insulating reinforcing part comprises a first insulating reinforcing rib and a second insulating reinforcing rib, wherein the first insulating reinforcing rib is arranged between the first terminal and the second terminal, two ends of the second insulating reinforcing rib are respectively connected with two opposite inner surfaces of the coaming, and the first insulating reinforcing rib and the second insulating reinforcing rib are intersected and connected.

Further, the bounding wall is rectangular frame body structure, and the first end and the bounding wall of first insulating stiffening rib are connected, and the second end and the middle part of second insulating stiffening rib of first insulating stiffening rib are connected.

Further, the semiconductor package structure further comprises an insulating colloid layer, the insulating colloid layer is connected with the substrate, and the semiconductor chip is located in the insulating colloid layer.

Further, be provided with the mount pad between the internal surface of second insulating stiffening rib and bounding wall, the encapsulation shell still includes the apron, is provided with the mounting hole on the apron, and the apron is connected with the mount pad through the fastener that wears to locate mount pad and mounting hole.

Further, the semiconductor package structure further includes a first metal plate connected between the substrate and the semiconductor chip, the first metal plate is electrically connected with the drain electrode of the semiconductor chip, and the first terminal is electrically connected with the first metal plate.

Further, the semiconductor package structure further includes a second metal plate disposed on the substrate and electrically connected to the source of the semiconductor chip, a second terminal electrically connected to the second metal plate, the second metal plate disposed at an interval from the first metal plate, and an insulating bump disposed between the first metal plate and the second metal plate.

Further, the semiconductor package structure further includes a third terminal and a third metal plate disposed on the substrate, the third metal plate being electrically connected to the gate of the semiconductor chip, the third terminal being electrically connected to the third metal plate, the third metal plate and the second metal plate being located on a same side of the insulating bump.

Further, the semiconductor package structure further includes a bonding wire connected between the second metal plate and the source electrode of the semiconductor chip, at least a portion of the bonding wire being located above the insulating bump.

Further, the semiconductor package structure further comprises a conductive plate, wherein the conductive plate is connected between the second metal plate and the source electrode of the semiconductor chip, and the conductive plate penetrates through the insulation bump and is located in the insulation colloid layer.

Further, the width of the insulation bump is more than 0 and less than or equal to 2mm; and/or the height of the insulating bump is greater than 0 and less than or equal to 3mm.

Further, the insulating colloid layer is made of silicone rubber; and/or the package shell and the insulation reinforcement are made of ceramic.

Further, be provided with first through-hole on the bounding wall, first terminal is including being the first board section and the second board section that the contained angle set up, and the first end of first board section is connected with the drain electrode electricity of semiconductor chip, and the second end of first board section is connected with the first end of second board section, and the second end of second board section passes first through-hole, and first board section shelters from the setting in first through-hole department.

Further, a space is formed between the insulating reinforcement part and the semiconductor chip, the surface of the insulating reinforcement part facing the substrate is far away from the substrate relative to the second plate section, and the surface of the insulating reinforcement part facing the substrate is located in the insulating colloid layer.

Further, the semiconductor package structure further comprises a cover plate connected with the coaming, a space is arranged between the insulation reinforcing part and the semiconductor chip, and the surface of the insulation colloid layer, which faces the cover plate, is arranged at a distance from the cover plate.

Further, the semiconductor package structure further includes a first insulating collar disposed on an outer surface of the collar and surrounding the outer periphery of the second board segment.

By applying the technical scheme of the application, the packaging shell provides a mounting foundation for each component of the semiconductor packaging structure, wherein the packaging shell comprises a substrate and a coaming connected with the substrate; the semiconductor chip is provided with a drain electrode and a source electrode and is respectively positioned at two sides of the semiconductor chip, and the first terminal is connected with the first side of the semiconductor chip; the second terminal is connected with the second side of the semiconductor chip, and the first terminal and the second terminal enable the drain electrode and the source electrode of the semiconductor chip to be electrically connected with the outside; the insulating reinforcing part is connected with the coaming, the insulating reinforcing part comprises a first insulating reinforcing rib and a second insulating reinforcing rib, the first insulating reinforcing rib is arranged between the first terminal and the second terminal, specifically, the first insulating reinforcing rib is arranged between the part of the first terminal in the packaging shell and the part of the second terminal in the packaging shell, so that the surface distance between the first terminal and the second terminal comprises the part of the outer surface of the first insulating reinforcing rib besides the inner surface of the packaging shell, the surface distance between the first terminal and the second terminal can be effectively enhanced, the insulating performance of the packaging shell is enhanced, and the structural strength of the packaging shell is not adversely affected; in addition, the both ends of second insulating stiffening rib are connected with two opposite internal surfaces of bounding wall respectively, and the structural strength of encapsulation shell also can be strengthened to the second insulating stiffening rib, and the setting of insulating enhancement portion makes the encapsulation shell not only have good insulating properties have good structural strength, and first insulating stiffening rib and second insulating stiffening rib intersect and link to each other for also have better structural strength between first insulating stiffening rib and the second insulating stiffening rib. Therefore, the technical scheme of the application can effectively solve the problem that the insulating performance and the structural strength of the shell in the related technology are difficult to be compatible.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:

fig. 1 shows a schematic perspective view of an embodiment of a semiconductor package structure according to the present invention;

FIG. 2 illustrates a schematic top view of the semiconductor package of FIG. 1;

FIG. 3 illustrates a side view schematic of the semiconductor package structure of FIG. 1;

fig. 4 shows a schematic front view of the semiconductor package of fig. 1;

Fig. 5 shows a split structure schematic diagram of the semiconductor package structure of fig. 1;

fig. 6 is a schematic perspective view showing a first terminal of the semiconductor package structure of fig. 5;

fig. 7 is a schematic perspective view showing a substrate, a first metal plate, a second metal plate and a third metal plate of the semiconductor package structure of fig. 5;

Fig. 8 is a schematic perspective view showing a part of the structure of the semiconductor package of fig. 1;

FIG. 9 illustrates a schematic top view of the semiconductor package of FIG. 8;

Fig. 10 shows a schematic side view of the semiconductor package structure of fig. 8.

Wherein the above figures include the following reference numerals:

10. packaging the shell; 11. a cover plate; 111. a mounting hole; 12. a substrate; 13. coaming plate; 131. a first plate body; 132. a second plate body; 133. a third plate body; 1331. a first through hole; 1332. a second through hole; 134. a mounting base; 14. a mounting cavity;

20. a semiconductor chip;

30. A first terminal; 31. a first plate segment; 32. a second plate segment;

40. A second terminal;

50. an insulation reinforcement; 51. a first insulating reinforcing rib; 52. second insulating reinforcing ribs;

60. a fastener;

71. a first metal plate; 72. a second metal plate; 73. a third metal plate;

82. A bonding wire; 83. a first insulating shroud; 84. a second insulating shroud;

90. and a third terminal.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. The following description of at least one exemplary embodiment is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the present application. As used herein, the singular is also intended to include the plural unless the context clearly indicates otherwise, and furthermore, it is to be understood that the terms "comprises" and/or "comprising" when used in this specification are taken to specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof.

The relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless it is specifically stated otherwise. Meanwhile, it should be understood that the sizes of the respective parts shown in the drawings are not drawn in actual scale for convenience of description. Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate. In all examples shown and discussed herein, any specific values should be construed as merely illustrative, and not a limitation. Thus, other examples of the exemplary embodiments may have different values. It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further discussion thereof is necessary in subsequent figures.

As shown in fig. 2,3 and 9, the present application provides a semiconductor package structure, and an embodiment of the semiconductor package structure of the present application includes: a package case 10, a semiconductor chip 20, a first terminal 30, a second terminal 40, and an insulation reinforcement 50; the package 10 includes a base plate 12 and a shroud 13 connected to the base plate 12; the semiconductor chip 20 is connected to the substrate 12; the first terminal 30 is connected to a first side of the semiconductor chip 20; the second terminal 40 is connected to the second side of the semiconductor chip 20; the insulating reinforcement 50 is connected to the shroud 13, the insulating reinforcement 50 includes a first insulating reinforcement rib 51 and a second insulating reinforcement rib 52, the first insulating reinforcement rib 51 is provided between the first terminal 30 and the second terminal 40, both ends of the second insulating reinforcement rib 52 are connected to opposite inner surfaces of the shroud 13, respectively, and the first insulating reinforcement rib 51 and the second insulating reinforcement rib 52 intersect and are connected.

By applying the technical scheme of the embodiment, the package shell 10 provides a mounting foundation for each component of the semiconductor package structure, wherein the package shell 10 comprises a substrate 12 and a coaming 13 connected with the substrate 12; the semiconductor chip 20 is arranged to realize the basic function of the semiconductor package structure, the semiconductor chip 20 is connected with the substrate 12, the semiconductor chip 20 is provided with a drain electrode and a source electrode and is respectively positioned at two sides of the semiconductor chip 20, and the first terminal 30 is connected with the first side of the semiconductor chip 20; the second terminal 40 is connected to the second side of the semiconductor chip 20, and the first terminal 30 and the second terminal 40 enable the drain and source of the semiconductor chip 20 to be electrically connected to the outside; the insulation reinforcement 50 is connected to the coaming 13, the insulation reinforcement 50 includes a first insulation reinforcement rib 51 and a second insulation reinforcement rib 52, the first insulation reinforcement rib 51 is disposed between the first terminal 30 and the second terminal 40, specifically, the first insulation reinforcement rib 51 is disposed between a portion of the first terminal 30 within the package case10 and a portion of the second terminal 40 within the package case10, such that a face distance between the first terminal 30 and the second terminal 40 includes a portion of an outer surface of the first insulation reinforcement rib 51 in addition to an inner surface of the package case10, thereby effectively enhancing the face distance between the first terminal 30 and the second terminal 40, thereby enhancing insulation performance of the package case10, and also not adversely affecting structural strength of the package case 10; in addition, the two ends of the second insulating reinforcing rib 52 are respectively connected with the two opposite inner surfaces of the coaming 13, the second insulating reinforcing rib 52 can also enhance the structural strength of the package shell 10, and the insulating reinforcing part 50 is arranged to enable the package shell 10 to have good insulating performance and good structural strength, and the first insulating reinforcing rib 51 and the second insulating reinforcing rib 52 are intersected and connected, so that good structural strength is also achieved between the first insulating reinforcing rib 51 and the second insulating reinforcing rib 52. Therefore, the technical scheme of the embodiment can effectively solve the problem that the insulating performance and the structural strength of the shell in the related technology are difficult to be compatible.

Specifically, in the present embodiment, the package case 10 further includes a cover plate 11, and a mounting cavity 14 is formed between the cover plate 11, the base plate 12, and the coaming 13; the first end of the first terminal 30 is electrically connected with the drain electrode of the semiconductor chip 20, and the second end of the first terminal 30 protrudes outside the mounting cavity 14 through the package case 10; a first end of the second terminal 40 is electrically connected with the source of the semiconductor chip 20, and a second end of the second terminal 40 protrudes outside the mounting cavity 14 through the package case 10; the insulation reinforcement 50 is provided between the semiconductor chip 20 and the cap plate 11, and the first insulation reinforcement rib 51 is provided between a portion of the first terminal 30 within the mounting cavity 14 and a portion of the second terminal 40 within the mounting cavity 14.

Incidentally, "creepage distance" refers to the shortest path between two conductive parts along the surface of an insulating material. The "along-plane distance" is mainly used for evaluating the insulation performance of the electric gap under different voltage levels so as to ensure the safety of the semiconductor packaging structure during normal operation or failure. In the present embodiment, the source of the semiconductor chip 20 is mainly supplied with current, and forms a current path together with the drain. In the present embodiment, the semiconductor chip 20 is a power semiconductor chip.

In addition, in the present embodiment, the semiconductor package structure further includes an insulating gel layer disposed in the mounting cavity 14 and connected to the substrate 12, and the semiconductor chip 20 is disposed in the insulating gel layer. Specifically, the insulating gel layer is further formed by pouring an insulating gel into the mounting cavity 14, and the semiconductor chip 20 is located in the insulating gel layer to ensure the insulating performance of the semiconductor package structure, preferably, the insulating gel layer may be made of silicone rubber, the working temperature of the semiconductor package structure is raised to 250 ℃, and compared with the conventional insulating gel layer (the highest tolerance of 230 ℃) made of silicone gel, the working temperature of 250 ℃ can be easily resisted by the insulating gel layer made of silicone rubber. The silicon rubber is a high polymer material with excellent performance, mainly comprises silicon atoms and oxygen atoms, and has very high-temperature resistance and excellent insulating performance. Its advantages in terms of high temperature resistance and insulation are mainly manifested in the following aspects: 1. high temperature resistance: can be used for a long time in a temperature range of-60 ℃ to +250 ℃ and can withstand higher temperatures even in a short time. The performance ensures that the silicon rubber can keep the original physical and chemical properties thereof in a high-temperature environment, is not easy to age and deform, and can work stably. 2. Insulation properties: the silicon rubber has high resistivity and dielectric constant, can effectively prevent current from flowing, and ensures safe operation of electrical equipment. Meanwhile, the insulating property of the silicone rubber is not affected by temperature change, and good insulating property can be maintained even in a high-temperature environment. 3. Chemical resistance: the silicon rubber has good chemical resistance, can resist corrosion of acid, alkali, salt and other chemical substances, and is not easy to corrode and deteriorate. The performance of the silicone rubber can still keep the stable performance of the silicone rubber under a severe chemical environment, and the service life of the material is prolonged. In general, the advantages of silicone rubber in terms of high temperature resistance and insulation are mainly represented by excellent high temperature resistance, good insulation performance and chemical resistance, so that the silicone rubber is widely applied to the fields of electricity, aerospace and the like.

As shown in fig. 1 to 5 and fig. 8 to 10, the coaming 13 is a rectangular frame structure, the coaming 13 includes a first plate 131, a second plate 132 and a third plate 133, the first plate 131 and the second plate 132 are disposed opposite to each other, the third plate 133 is connected between the first plate 131 and the second plate 132, a first end of the first insulating reinforcing rib 51 is connected with the third plate 133, a second end of the first insulating reinforcing rib 51 is connected with a middle portion of the second insulating reinforcing rib 52, and two ends of the second insulating reinforcing rib 52 are connected with the first plate 131 and the second plate 132, respectively. Specifically, in the present embodiment, the first insulating reinforcing rib 51 and the second insulating reinforcing rib 52 are vertically disposed, the first insulating reinforcing rib 51 extends along the length direction of the enclosure 13 and is connected to the middle portion of the second insulating reinforcing rib 52, and the second insulating reinforcing rib 52 extends along the width direction of the enclosure 13, so that both the first insulating reinforcing rib 51 and the second insulating reinforcing rib 52 can play a role in improving the structural strength of the package case 10.

As shown in fig. 1 to 5 and 8 to 10, a mounting seat 134 is provided between the second insulating reinforcing rib 52 and the inner surface of the shroud 13, a mounting hole 111 is provided in the cover plate 11, and the cover plate 11 is connected to the mounting seat 134 by a fastener 60 penetrating the mounting seat 134 and the mounting hole 111. Specifically, the width of the mounting seat 134 is greater than the width of the second insulating reinforcing rib 52, so that the mounting seat 134 can strengthen the connection strength between the second insulating reinforcing rib 52 and the inner surface of the coaming 13, the mounting seat 134 can also provide a mounting foundation for the fastening piece 60, so that the cover plate 11 is connected with the mounting seat 134 through the fastening piece 60 penetrating through the mounting seat 134 and the mounting hole 111, and further, the cover plate 11 is connected with the coaming 13; compared with the traditional mode of fixing the cover plate and the coaming by using the adhesive, the embodiment not only simplifies the packaging process steps of the semiconductor packaging structure, but also increases the high temperature resistance of the semiconductor packaging structure, and compared with the traditional mode of fixing the cover plate and the coaming by using the buckle, the embodiment enables a user to conveniently open the cover plate 11 so as to be capable of observing the working condition inside the semiconductor packaging structure or the condition after failure.

As shown in fig. 5 to 8, the semiconductor package structure further includes a first metal plate 71, the first metal plate 71 is connected between the substrate 12 and the semiconductor chip 20, the first metal plate 71 is electrically connected with the drain electrode of the semiconductor chip 20, the first end of the first terminal 30 is electrically connected with the first metal plate 71, specifically, the semiconductor chip 20 is directly connected with the substrate 12 through the first metal plate 71, that is, the semiconductor chip 20 is directly connected with the package case 10 through the first metal plate 71, compared with the scheme that the substrate and the semiconductor chip are connected through the lining plate and the connection part between the lining plate and the substrate in the related art, the embodiment simplifies the heat dissipation path between the semiconductor chip 20 and the substrate 12, reduces the thermal resistance on the heat dissipation path, so that the heat generated by the semiconductor chip 20 during operation can be better transferred to the substrate 12 and even the package case 10, thereby being more beneficial to the heat dissipation of the semiconductor chip 20.

As shown in fig. 5 to 8, the semiconductor package structure further includes a second metal plate 72 disposed on the substrate 12, the second metal plate 72 being electrically connected to the source of the semiconductor chip 20, the first end of the second terminal 40 being electrically connected to the second metal plate 72, the second metal plate 72 being disposed apart from the first metal plate 71, and an insulating bump disposed between the first metal plate 71 and the second metal plate 72. Specifically, since the second metal plate 72 is electrically connected to the source of the semiconductor chip 20 and the first metal plate 71 is electrically connected to the drain of the semiconductor chip 20, the voltage difference between the first metal plate 71 and the second metal plate 72 is also large, and the insulation bump effectively enhances the creepage distance between the first metal plate 71 and the second metal plate 72 to thereby improve the insulation performance of the semiconductor package structure.

As shown in fig. 5 to 8, the semiconductor package structure further includes a third terminal 90 and a third metal plate 73 disposed on the substrate 12, the third metal plate 73 being electrically connected to the gate of the semiconductor chip 20, a first end of the third terminal 90 being electrically connected to the third metal plate 73, a second end of the third terminal 90 protruding outside the mounting cavity 14 through the package case 10, the third metal plate 73 and the second metal plate 72 being located on the same side of the insulating bump. Specifically, since the voltage difference between the third metal plate 73 and the first metal plate 71 is small, the insulation requirement of the semiconductor package structure can be satisfied by positioning the third metal plate 73 and the first metal plate 71 on the same side of the insulation bump.

As shown in fig. 5 to 8, the semiconductor package structure further includes a bonding wire 82, the bonding wire 82 is connected between the second metal plate 72 and the source of the semiconductor chip 20, and at least a portion of the bonding wire 82 is located above the insulating bump. Specifically, the bonding wire 82 is located in the insulating paste layer, and the bonding wire 82 can stably electrically connect the second metal plate 72 and the source electrode of the semiconductor chip 20. In addition, the semiconductor chip 20 and the second metal plate 72 are connected using a sintering process. The sintering process may be a nano silver sintering process. The semiconductor chip 20 and the second metal plate 72 are manufactured by the nano silver sintering process so that the semiconductor package structure can withstand an operating temperature of 300 c or higher than an operating temperature (220 c) of the semiconductor chip and the second connection plate manufactured by the conventional soldering process. It should be noted that the nano silver sintering process is an innovative material connection technology, and is particularly suitable for manufacturing electronic packages and high-power devices. The process forms the connecting layer with high electrical conductivity and high thermal conductivity by sintering the nano-scale silver particles at low temperature, and has remarkable technical advantages and wide application potential. The nano silver sintering process is an important technology in electronic packaging and high-power device manufacturing by virtue of the characteristics of low-temperature sintering, high electrical conductivity, high thermal conductivity, structural strength and environmental protection. The nano silver sintering process not only improves the performance and reliability of the semiconductor packaging structure, but also provides a green and environment-friendly solution, and the advantages of adopting the nano silver sintering process are as follows: 1. and (3) sintering at low temperature: one of the main advantages of the nano-silver sintering process is its low temperature sintering characteristics. Conventional metal sintering processes typically require high temperatures (in excess of 800 ℃) to achieve efficient sintering, whereas nano-silver sintering can be accomplished at temperatures between 200 ℃ and 300 ℃. This low temperature sintering characteristic makes the process particularly suitable for temperature sensitive electronic components and materials, such as certain semiconductors and organic materials, thereby avoiding thermal damage and material degradation that may occur at high temperatures. 2. High conductivity: the connecting layer formed by the nano silver particles after sintering has excellent conductive performance. Silver is a metal, and its conductivity is highest among all metals. The nano silver sintering process can realize tight connection between silver particles at a lower temperature, so that a low-resistance connecting layer is formed. This can significantly improve performance and efficiency for electronic devices and circuit boards that require efficient electrical transmission. 3. High thermal conductivity: besides high electrical conductivity, the nano silver sintered layer also has high thermal conductivity. This means that it can effectively dissipate heat, avoiding failure or performance degradation of the electronic device due to overheating. In high power devices such as power semiconductors, LEDs, and high frequency communication equipment, good thermal management is a key factor to ensure stability and long life. 4. Structural strength and stability: the nano silver sintering process can realize the close combination of silver particles at a lower temperature, and form a connecting layer with high structural strength and stability. Compared with the traditional welding method, the nano silver sintered layer has higher reliability and durability, and can better resist fatigue and damage caused by stress and thermal cycle. 5. Environmental protection characteristics: the nano silver sintering process does not contain lead, and meets the environmental protection requirement. Conventional soldering processes often use lead-containing solders, which, although superior in performance, are harmful to the environment and health. The nano silver sintering provides a green alternative scheme, and accords with the environmental protection development trend in the future electronic packaging and manufacturing field. 6. Process flexibility: the nano silver sintered material usually exists in a paste form, and can be coated and printed by various methods such as screen printing, spraying or dispensing. This flexibility allows the process to accommodate different manufacturing requirements and design requirements, providing greater design freedom and manufacturing efficiency.

Further, the first metal plate 71 may be made of copper, and the substrate 12 may be made of ceramic, that is, the first metal plate 71 and the substrate 12 may be made of copper on a ceramic substrate.

The copper-clad ceramic structure can be manufactured by the following modes:

DBC (Direct Bonded Copper, direct copper coating): the copper foil is directly sintered to the surfaces of Al ₂O₃ and AlN ceramics at high temperature by a hot melt bonding method to prepare the composite substrate. The copper thickness of the DBC substrate can be generally 100-600 mu m due to higher eutectic bonding strength between copper foil and ceramic, and meanwhile, the ceramic and copper have good heat conductivity, and the DBC substrate is better in heat stability. Benefits of DBC technology include: high thermal conductivity: the DBC substrate has excellent heat conduction properties, which are critical to heat dissipation of high power electronics. For example, aluminum nitride has a much higher thermal conductivity than aluminum oxide, making DBC substrates more efficient in high power applications. High insulation: the ceramic material itself has a high insulation property, making the DBC substrate very reliable in high voltage applications. High structural strength: the DBC substrate combines the high strength of ceramics with the high conductivity of copper, providing good structural stability. Low coefficient of thermal expansion: the thermal expansion coefficient of the DBC substrate is similar to that of a silicon chip, so that the thermal stress is reduced and the packaging reliability is improved. Simplified manufacturing process: the DBC technology simplifies the conventional multilayer ceramic substrate manufacturing process because it does not require an additional metallization step. High current carrying capacity: the thickness of the copper layer can be made thicker, so that the DBC substrate has higher current carrying capacity and is suitable for high-current application. Excellent solder resistance: the DBC substrate can withstand multiple soldering processes without damage. Customizable layout: the DBC substrate may customize the circuit layout as desired, similar to a conventional PCB. Economy: in some applications, DBC substrates may be more economical than using other high performance materials (e.g., AIN and Si3N 4). Environmental suitability: DBC substrates are capable of stable operation under harsh environmental conditions, such as high temperature, high pressure, and chemically aggressive environments.

DPC (DIRECT PLATING coppers, direct Copper plating): is a ceramic circuit processing technology developed on the basis of ceramic film processing technology. The circuit is formed by using ceramic as the substrate of the circuit, adopting sputtering technology to compound a metal layer on the surface of the substrate, and adopting electroplating and photoetching technology. Benefits of DPC technology include: high thermal conductivity: the DPC substrate uses ceramic as a base material, has excellent heat conduction performance, can effectively conduct and emit heat generated by high-power electronic equipment, and improves the reliability and performance of the equipment. The high frequency characteristics are excellent: the DPC substrate has low dielectric constant and dielectric loss, can realize low signal transmission loss in high frequency and microwave frequency bands, and is suitable for high frequency and radio frequency applications. High density packaging capability: the DPC substrate has high circuit density and fine line width/fine line pitch capability, and can achieve a more compact circuit layout and higher circuit density, facilitating miniaturization and integrated design of the device. Excellent structural performance: the DPC substrate has high structural strength and hardness, can resist environmental stresses such as vibration, impact, thermal expansion and the like, and improves the reliability and durability of the equipment. Good dimensional stability: the DPC substrate has a low thermal expansion coefficient in a high-temperature environment, can maintain good dimensional stability, and reduces the risks of mismatch and cracks caused by thermal stress. Excellent welding performance: the copper film on the surface of the DPC substrate has good welding performance, and reliable circuit connection and welding can be realized. High reliability and durability: the DPC substrate has high reliability and durability due to the material and structural design, and can meet the requirements of severe working environment and long-term use.

AMB (ACTIVE METAL Brazing, active metal braze): AMB is developed based on DBC technology, and AgCu solder containing active elements Ti and Zr wets and reacts at the interface of ceramic and metal at high temperature, thereby realizing heterogeneous bonding of ceramic and metal. The AMB process has the following benefits: 1. high bonding strength and reliability. The core of the AMB process is that active elements are added into the brazing filler metal, and a compact reaction layer is formed on the surface of the ceramic through chemical reaction at high temperature. The reaction layer greatly improves the wettability of the brazing filler metal on the surface of the ceramic, so that the combination between the ceramic and the metal is more compact and firm. Compared with the traditional DBC technology, the ceramic substrate prepared by the AMB technology has higher heat conductivity, better copper layer binding force and smaller heat resistance, thereby remarkably improving the reliability and service life of the product. Among power electronic devices, for example, high-power semiconductor devices such as IGBT (insulated gate bipolar transistor) modules, AMB copper-clad substrates are preferred packaging materials because of their excellent bonding strength and reliability. The IGBT module is used as a core component in the fields of electric automobiles, rail transit, wind power generation and the like, and has extremely high requirements on heat dissipation and reliability. The application of the AMB technology effectively improves the heat dissipation performance of the IGBT module, reduces the heat resistance, and prolongs the service life of the module. 2. Wide applicability of materials. The AMB technology has wide application range to ceramic materials, and can process various ceramic substrates including aluminum oxide (Al 2O 3), aluminum nitride (AlN), silicon nitride (Si 3N 4) and the like. The ceramic materials have unique physical and chemical properties and are suitable for different application scenes. For example, the Al2O3 ceramic is widely applied to small-power heat dissipation devices such as LEDs and the like due to low cost and mature process; alN and Si3N4 ceramics become the preferred materials of high-power IGBT modules of high-speed rail, wind power generation and the like due to high heat conductivity, low dielectric constant and thermal expansion coefficient matched with monocrystalline silicon. in addition, the AMB process can also process different kinds of metal materials, such as copper, nickel, silver, etc., further expanding the application range thereof. This wide material applicability makes AMB technology extremely flexible and adaptable in the field of electronic device packaging. 3. Simple operation flow and high production efficiency. The AMB process has relatively simple and convenient processing process and can be completed in one heating, thereby greatly shortening the production period. This is certainly a great advantage for modern manufacturing, where efficient production is sought. In addition, the operation process of the AMB technology is relatively simple, the technical requirements on operators are relatively low, and the AMB technology is beneficial to reducing the production cost and improving the production efficiency. 4. Excellent thermal performance and heat dissipation capability. The ceramic substrate prepared by the AMB process has excellent thermal performance and heat dissipation capability. Taking an AMB-SiN ceramic substrate as an example, the heat conductivity of the ceramic substrate is higher than 90W/mK and is far higher than that of a traditional Al2O3 ceramic substrate. This makes AMB-SiN ceramic substrates excellent in high power density, high heat dissipation demanding electronic devices. Especially in application scenes such as new energy automobiles, photovoltaic inverters, wind turbines and the like, the AMB-SiN ceramic substrate can effectively reduce the working temperature of devices and improve the stability and reliability of a system. 5. Good thermal matching and structural properties. The ceramic substrate prepared by the AMB process also has good thermal matching property and structural performance. Taking an AMB-SiN ceramic substrate as an example, the thermal expansion coefficient of the AMB-SiN ceramic substrate is close to that of the SiC chip, so that the influence of thermal stress on the packaging structure is reduced. In addition, the AMB-SiN ceramic substrate also has higher bending strength and wear resistance, and can bear larger structural stress and vibration impact. These excellent properties make AMB-SiN ceramic substrates ideal packaging materials in high reliability, high heat dissipation requirements for electronic devices.

In addition, in the present embodiment, the semiconductor package structure further includes a conductive plate connected between the second metal plate 72 and the source of the semiconductor chip 20, where the conductive plate penetrates through the insulating bump and is located in the insulating gel layer. Specifically, the provision of the conductive plate can also exert an effect of stably electrically connecting the second metal plate 72 and the source of the semiconductor chip 20. The width of the insulation bump is more than 0 and less than or equal to 2mm; the height of the insulating bump is greater than 0 and equal to or less than 3mm, and is set such that the insulating bump has a sufficient width and height to increase the areal distance between the first metal plate 71 and the second metal plate 72, it should be noted that the width of the insulating bump refers to the dimension of the insulating bump in the direction parallel to the substrate 12, the height of the insulating bump refers to the dimension of the insulating bump in the direction perpendicular to the substrate 12, specifically, the width of the insulating bump may be 0.5mm, 1mm, 1.2mm, 1.4mm, 1.5mm or 2mm, and the height of the insulating bump may be 0.6mm, 1mm, 1.2mm, 2mm, 2.5mm or 3mm.

As shown in fig. 1 and fig. 5 to 8, a first through hole 1331 is formed in the enclosing plate 13, the first terminal 30 includes a first board segment 31 and a second board segment 32 which are disposed at an included angle, a first end of the first board segment 31 is electrically connected with a drain electrode of the semiconductor chip 20, a second end of the first board segment 31 is connected with a first end of the second board segment 32, a second end of the second board segment 32 passes through the first through hole 1331, and the first board segment 31 is arranged at the first through hole 1331 in a shielding manner. Specifically, the formation of the insulating colloid layer is needed to be realized through a glue filling process, when the insulating colloid is in a flowing state, the insulating colloid is easy to overflow from the first through hole 1331 to the outside of the package shell 10 during glue filling, and the first terminal 30 can shield the first through hole 1331 by enabling the first plate section 31 to shield the first through hole 1331, so that the insulating colloid can not overflow from the first through hole 1331 during glue filling, the reliability of glue filling is enhanced, and the degassing after glue filling is facilitated; in the present embodiment, the second terminal 40 and the third terminal 90 have similar structures to the first terminal 30, and also have similar effects on the second through hole 1332 and the third through hole (both of which have similar structures to the first through hole 1331). In the present embodiment, the first plate section 31 and the second plate section 32 are vertically disposed, and if in the posture of the semiconductor package structure in fig. 2, the first plate section 31 is extended in the vertical direction, and the second plate section 32 is extended in the lateral direction.

As shown in fig. 1 to 5 and fig. 8 to 10, the semiconductor package structure further includes a first insulating collar 83, and the first insulating collar 83 is disposed on the outer surface of the collar 13 and surrounds the outer periphery of the second board section 32. Specifically, the first insulating enclosure 83 is connected to the outer surface of the enclosure 13, the first insulating enclosure 83 is disposed around the first through hole 1331, specifically, the first insulating enclosure 83 is disposed around the outer periphery of the portion of the first terminal 30 penetrating out of the mounting cavity 14 (i.e., the outer periphery of the second board segment 32), the surface distance between the portion of the first terminal 30 penetrating out of the mounting cavity 14 and the portion of the second terminal 40 penetrating out of the mounting cavity 14 includes the portion passing through the outer surface of the first insulating enclosure 83 in addition to the portion passing through the outer surface of the enclosure 13, and compared with the scheme in which the surface distance includes only the portion passing through the outer surface of the enclosure 13, the surface distance between the first terminal 30 and the second terminal 40 in this embodiment can be effectively increased, and thus the insulation performance between the portion of the first terminal 30 penetrating out of the mounting cavity 14 and the portion of the second terminal 40 penetrating out of the mounting cavity 14 is further enhanced, so that the insulation performance of the semiconductor package structure is further enhanced. In addition, the second insulating shroud 13 is disposed at the second through hole 1332 and surrounds the outer periphery of the second terminal 40, and the function of the second insulating shroud 13 is similar to that of the first insulating shroud 83, and will not be described here again.

Further, in the present embodiment, as shown in fig. 3, there is a space between the insulating reinforcement 50 and the semiconductor chip 20, wherein the surface of the insulating reinforcement 50 facing the substrate 12 is disposed away from the substrate 12 with respect to the second plate section 32, the surface of the insulating reinforcement 50 facing the substrate 12 is located in an insulating gel layer, specifically, the first terminal 30, the second terminal 40, and the third terminal 90 each have a similar structure and each have a similar relationship with the insulating reinforcement 50 and the insulating gel layer, so that the first terminal 30, the second terminal 40, and the third terminal 90 are each located in the insulating gel layer, and a pure air path is not formed between the first terminal 30, the second terminal 40, and the third terminal 90 each other, but a solid path having an insulating gel, thereby ensuring the insulating performance of the semiconductor package structure.

In addition, in the present embodiment, the surface of the insulating gel layer facing the cover plate 11 is spaced apart from the cover plate 11. This arrangement is because there is a step of vacuum removing bubbles during the process of filling the insulating gel, in which the bubbles become larger and break, and if the filled insulating gel is too much (i.e., the surface of the insulating gel layer facing the cover plate 11 is not spaced from the cover plate 11), the enlarged bubbles will be the solidified insulating gel extruded to the outside of the package case 10.

Further, in the present embodiment, the package can 10 and the insulation reinforcement 50 are both made of ceramic. Specifically, the package can 10 and the insulation reinforcement 50 may be made of materials such as aluminum oxide, aluminum nitride, silicon nitride, zirconium oxide, silicon carbide, etc., so that the package can 10 has advantages of high temperature resistance, corrosion resistance, good heat conductive property, high structural strength, etc. Alumina has excellent structural strength and chemical resistance, and is suitable for application with high durability requirement. Zirconia is known for its excellent toughness and high temperature resistance and exhibits excellent properties in high temperature and high stress environments. Aluminum nitride has high thermal conductivity and low expansion coefficient, can effectively dissipate heat, and is suitable for high-power electronic devices. Silicon carbide not only has high hardness and high wear resistance, but also remains stable at extremely high temperatures, making it very popular in high temperature electronics and high frequency applications. The diversity and excellent characteristics of the ceramic materials provide a wide selection and significant performance improvement for the design and application of semiconductor packaging structures.

Further, a coating layer is provided on the semiconductor chip 20. Further, a coating layer may be provided on the outer periphery of the bonding wire 82, between the insulating colloid portion and the substrate 12, and between the first metal plate 71 and the substrate 12. The preferred coating may be a PI coating, which may comprise multiple layers. PI is polyimide. The PI coating can ensure insulation, long-term temperature resistance, and moisture isolation of the semiconductor chip 20. The application of PI coating to semiconductor chip 20 has a number of significant benefits, particularly in terms of improving the performance, reliability and durability of semiconductor chip 20. The following are several major advantages of using PI coatings: 1. excellent thermal stability: polyimide materials have excellent thermal stability and can maintain their physical and chemical properties in a high temperature environment. For the chip working under the high temperature condition, the PI coating can effectively protect the chip from the influence of thermal stress, so that the service life of the chip is prolonged. PI materials are generally capable of withstanding high temperatures, which makes them very valuable in high temperature electronics and high power applications. 2. Electrical insulation properties: the PI coating has good electrical insulation performance, and can prevent electrical short circuit and leakage inside the chip. The high insulation ensures the safe operation of the chip in high voltage and high frequency environment, and reduces the risk of electrical faults. This is particularly important for electronic devices requiring high reliability. 3. Structural strength and flexibility: polyimide material has high structural strength and flexibility and can resist external stress and impact. The PI coating applied to the chip surface can provide additional protection against damage to the chip during manufacture, shipping and use. Meanwhile, the flexibility of the PI coating enables the PI coating to adapt to micro deformation and stress variation of the chip surface, and the integrity and effectiveness of the coating are maintained. 4. Chemical resistance: the PI material has excellent chemical corrosion resistance and can resist the attack of various chemical reagents, solvents and corrosive gases. The PI coating can effectively protect the chip from chemical corrosion, especially in severe working environments such as industrial control, chemical production and environmental monitoring equipment. 5. Low dielectric constant: polyimide has a low dielectric constant, which is an important advantage for high speed and high frequency circuits. The low dielectric constant is beneficial to reducing loss and delay in the signal transmission process and improving the transmission speed and integrity of signals, thereby improving the performance and efficiency of the chip. 6. Process compatibility: PI coatings can be applied by a variety of process methods, such as spin coating, spray coating, dip coating, and the like, and the process is relatively simple and suitable for mass production. This process compatibility enables PI coatings to be widely used in different types of chip and electronic device fabrication, providing flexible solutions.

In the description of the present invention, it should be understood that the azimuth or positional relationships indicated by the azimuth terms such as "front, rear, upper, lower, left, right", "lateral, vertical, horizontal", and "top, bottom", etc., are generally based on the azimuth or positional relationships shown in the drawings, merely to facilitate description of the present invention and simplify the description, and these azimuth terms do not indicate and imply that the apparatus or elements referred to must have a specific azimuth or be constructed and operated in a specific azimuth, and thus should not be construed as limiting the scope of protection of the present invention; the orientation word "inner and outer" refers to inner and outer relative to the contour of the respective component itself.

Spatially relative terms, such as "above … …," "above … …," "upper surface on … …," "above," and the like, may be used herein for ease of description to describe one device or feature's spatial location relative to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "above" or "over" other devices or structures would then be oriented "below" or "beneath" the other devices or structures. Thus, the exemplary term "above … …" may include both orientations "above … …" and "below … …". The device may also be positioned in other different ways (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

In addition, the terms "first", "second", etc. are used to define the components, and are only for convenience of distinguishing the corresponding components, and the terms have no special meaning unless otherwise stated, and therefore should not be construed as limiting the scope of the present invention.

The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor package structure, comprising:

A package (10) comprising a substrate (12) and a shroud (13) connected to the substrate (12);

a semiconductor chip (20) connected to the substrate (12);

a first terminal (30) connected to a first side of the semiconductor chip (20);

A second terminal (40) connected to a second side of the semiconductor chip (20);

The insulating reinforcing part (50) is connected with the coaming (13), the insulating reinforcing part (50) comprises a first insulating reinforcing rib (51) and a second insulating reinforcing rib (52), the first insulating reinforcing rib (51) is arranged between the first terminal (30) and the second terminal (40), two ends of the second insulating reinforcing rib (52) are respectively connected with two opposite inner surfaces of the coaming (13), and the first insulating reinforcing rib (51) and the second insulating reinforcing rib (52) are intersected and connected.

2. The semiconductor package according to claim 1, wherein a first end of the first insulating reinforcing rib (51) is connected to the enclosure plate (13), and a second end of the first insulating reinforcing rib (51) is connected to a middle portion of the second insulating reinforcing rib (52).

3. The semiconductor package according to claim 1, further comprising an insulating gel layer, the insulating gel layer being connected to the substrate (12), the semiconductor chip (20) being located within the insulating gel layer.

4. The semiconductor packaging structure according to claim 1, wherein a mounting seat (134) is provided between the second insulating reinforcing rib (52) and the inner surface of the surrounding board (13), the packaging shell (10) further comprises a cover plate (11), mounting holes (111) are provided in the cover plate (11), and the cover plate (11) is connected with the mounting seat (134) through fasteners (60) penetrating through the mounting seat (134) and the mounting holes (111).

5. The semiconductor package structure according to any one of claims 1,2 or 4, further comprising a first metal plate (71), the first metal plate (71) being connected between the substrate (12) and the semiconductor chip (20), the first metal plate (71) being electrically connected to a drain of the semiconductor chip (20), the first terminal (30) being electrically connected to the first metal plate (71).

6. The semiconductor package according to claim 5, further comprising a second metal plate (72) provided on the substrate (12), the second metal plate (72) being electrically connected to the source of the semiconductor chip (20), the second terminal (40) being electrically connected to the second metal plate (72), the second metal plate (72) being spaced apart from the first metal plate (71), and an insulating bump provided between the first metal plate (71) and the second metal plate (72).

7. The semiconductor package structure according to claim 6, further comprising a third terminal (90) and a third metal plate (73) provided on the substrate (12), the third metal plate (73) being electrically connected to the gate of the semiconductor chip (20), the third terminal (90) being electrically connected to the third metal plate (73), the third metal plate (73) and the second metal plate (72) being located on the same side of the insulating bump.

8. The semiconductor package according to claim 6, further comprising a bonding wire (82), the bonding wire (82) being connected between the second metal plate (72) and the source of the semiconductor chip (20), at least a portion of the bonding wire (82) being located above the insulating bump.

9. The semiconductor package according to claim 6, further comprising an insulating gel layer connected to the substrate (12), the semiconductor chip (20) being located in the insulating gel layer, the semiconductor package further comprising a conductive plate connected between the second metal plate (72) and the source of the semiconductor chip (20), the conductive plate penetrating the insulating bump and being located in the insulating gel layer.

10. The semiconductor package according to claim 6, wherein,

The width of the insulation lug is more than 0 and less than or equal to 2mm; and/or the number of the groups of groups,

The height of the insulation bump is more than 0 and less than or equal to 3mm.

11. The semiconductor package according to claim 6, wherein,

The semiconductor packaging structure further comprises an insulating colloid layer, wherein the insulating colloid layer is connected with the substrate (12), the semiconductor chip (20) is positioned in the insulating colloid layer, and the insulating colloid layer is made of silicon rubber; and/or the number of the groups of groups,

The package (10) and the insulation reinforcement (50) are both made of ceramic.

12. A semiconductor package structure according to claim 3, wherein a first through hole (1331) is provided in the surrounding board (13), the first terminal (30) comprises a first board section (31) and a second board section (32) which are arranged at an included angle, a first end of the first board section (31) is electrically connected with a drain electrode of the semiconductor chip (20), a second end of the first board section (31) is connected with a first end of the second board section (32), a second end of the second board section (32) passes through the first through hole (1331), and the first board section (31) is shielded at the first through hole (1331).

13. The semiconductor package according to claim 12, wherein there is a space between the insulating reinforcement (50) and the semiconductor chip (20), the surface of the insulating reinforcement (50) facing the substrate (12) being located away from the substrate (12) with respect to the second plate section (32), the surface of the insulating reinforcement (50) facing the substrate (12) being located within the insulating gel layer.

14. The semiconductor package structure according to claim 12, further comprising a cover plate (11) connected to the peripheral plate (13), wherein the insulating reinforcement portion (50) and the semiconductor chip (20) are spaced apart from each other, and wherein the insulating gel layer is disposed at a distance from the cover plate (11) toward a surface of the cover plate (11).

15. The semiconductor package according to claim 12, further comprising a first insulating collar (83), the first insulating collar (83) being disposed on an outer surface of the collar (13) and surrounding an outer periphery of the second plate section (32).