CN118969737A - A MOSFET with enhanced body diode freewheeling capability and a method for manufacturing the same - Google Patents

Abstract

A MOSFET with enhanced body diode freewheeling capability and a preparation method thereof. The invention relates to the field of semiconductor technology. The invention comprises the following steps: step S100, preparing mutually spaced first heavily doped body regions in an epitaxial wafer; step S200, preparing a second heavily doped source region in an epitaxial wafer; step S300, preparing a gate trench in the epitaxial wafer; step S400, sequentially preparing a gate dielectric and polysilicon in the trench; step S500, depositing an isolation layer on the epitaxial wafer, opening a window to prepare a source trench, wherein the bottom of the source trench extends to the inside of the first heavily doped body region, and the trench width is greater than the spacing width of the first heavily doped body region; step S600, preparing a Schottky contact metal at the bottom of the source trench, forming a Schottky contact with the second lightly doped voltage-resistant region, and the upper surface of the Schottky contact metal is lower than the lower surface of the second heavily doped source region; the invention is conducive to the advancement of the commercialization process and has higher commercial value.

Description

MOSFET for enhancing follow current capability of body diode and preparation method thereof

Technical Field

The invention relates to the technical field of semiconductors, in particular to a MOSFET for enhancing the follow current capability of a body diode and a preparation method thereof.

Background

In the technical field of power electronics, a MOSFET is a commonly used power semiconductor, and has been used as one of the most commonly used switching devices in the field of power semiconductors instead of a triode.

In the iterative process of decades, the flywheel capability of the body diode is more and more emphasized, and one important technology for improving the flywheel capability of the body diode is to integrate the schottky diode at present, and the purpose of reducing the flywheel loss of the body diode is achieved by utilizing the low starting voltage and high current characteristics of the schottky diode.

Related patents of MOSFETs integrated with Schottky diodes exist at present, and publication number CN117334748A discloses a source trench integrated SBD and HK medium SiCUMOS and a preparation method, wherein a source trench penetrates through a body region and extends to a voltage-resistant region, a current expansion layer below the body region of the MOSFET is utilized to form SBD with Schottky contact metal in the trench, and in order to reduce reverse leakage of the integrated SBD, a high-K medium is prepared below the Schottky contact metal, but compared with a common trench MOS, the scheme is characterized in that an additional process step is adopted to prepare the current expansion layer to reduce on resistance of the SBD, and the preparation of the high-K medium below the Schottky contact metal can reduce reverse leakage of the integrated SBD, but also reduces forward current-through capability of the integrated SBD and forward current-through capability of the MOSFET, and also increases additional process steps; other patent documents such as CN117334746A, CN117334747A, CN117334745A, CN110473914B have similar drawbacks.

Disclosure of Invention

Aiming at the research and development direction of improving the free-wheeling capability of the body diode, the invention provides the MOSFET for enhancing the free-wheeling capability of the body diode and the preparation method thereof, thereby reducing the process steps and the process difficulty, and reducing the reverse leakage of the integrated SBD under the condition of not influencing the forward current passing capability of the integrated SBD and the forward current passing capability of the MOSFET device.

The technical scheme of the invention is as follows:

a method of fabricating a MOSFET that enhances body diode freewheeling capability comprising the steps of:

Step S100, preparing first heavily doped body regions which are mutually spaced in an epitaxial wafer;

Step S200, preparing a second heavily doped source region in the epitaxial wafer;

Step S300, preparing a grid groove in an epitaxial wafer;

Step S400, sequentially preparing a gate dielectric and polysilicon in the groove;

Step S500, depositing an isolation layer on the epitaxial wafer, and windowing to prepare a source electrode groove, wherein the bottom of the source electrode groove extends to the inside of the first heavily doped body region, and the width of the groove is larger than the interval width of the first heavily doped body region;

Step S600, preparing Schottky contact metal at the bottom of the source electrode groove, forming Schottky contact with the second lightly doped voltage-resistant region, wherein the upper surface of the Schottky contact metal is lower than the lower surface of the second heavily doped source region;

Step S700, ohmic contact metal is prepared in the source electrode groove, ohmic contact is formed between the ohmic contact metal and the first heavily doped body region and the second heavily doped source region, and the ohmic contact metal and the Schottky contact metal in the source electrode groove jointly form source electrode metal;

Step S800, window is opened at the gate groove, gate metal is prepared, drain metal is prepared at the back of the epitaxial wafer, and the whole device is prepared.

Specifically, step S100 includes:

step S110, adopting a photoetching process, and protecting the outer area of the first heavily doped body region by using a mask; the first heavily doped body regions are formed to be spaced apart from each other by a diffusion process or an ion implantation process.

Specifically, step S200 includes:

step S210, adopting a photoetching process, and protecting the outer area of the second heavy doping source region by using a mask; the second heavily doped source region is formed by a diffusion process or an ion implantation process.

Specifically, step S300 includes:

step S310, adopting a photoetching process, and protecting the outer area of the grid electrode groove by using a mask; forming a gate trench by an etching process;

specifically, step S400 includes:

step S410, protecting the outer area of the gate trench by using a mask through a photoetching process, and preparing a gate dielectric in the gate trench by using a thermal oxygen technology;

in step S420, polysilicon is prepared in the gate trench by chemical vapor deposition.

Specifically, step S500 includes:

Step S510, preparing an isolation layer through chemical vapor deposition, protecting the outer area of a source electrode groove by using a mask through a photoetching process, windowing the source electrode groove through an etching process, wherein the bottom of the source electrode groove extends to the inside of a first heavy doping body region, and the width of the groove is larger than the interval width of the first heavy doping body region;

specifically, step S600 includes:

Step S610, preparing Schottky contact metal at the bottom of the source electrode groove through a stripping process or an etching process, wherein the Schottky contact metal and the second lightly doped voltage-resistant region form Schottky contact, and the upper surface of the Schottky contact metal is lower than the lower surface of the second heavily doped source region;

Specifically, step S700 includes:

Step S710, ohmic contact metal is prepared in the source electrode groove through a stripping process or an etching process, ohmic contact is formed between the ohmic contact metal and the first heavily doped body region and between the ohmic contact metal in the source electrode groove and the Schottky contact metal, and the source electrode metal is formed together;

Specifically, step S800 includes:

Step S810, protecting the outer area of the windowed position of the grid electrode groove by using a mask through a photoetching process, windowing the windowed position of the grid electrode groove by using an etching process, preparing grid electrode metal, preparing drain electrode metal at the bottom of an epitaxial wafer by using a thinning process and a back gold process, and finishing the preparation of the whole device;

a MOSFET for enhancing the free-wheeling capability of a body diode comprises drain electrode metal, an epitaxial wafer and an isolation layer which are sequentially arranged from bottom to top;

The epitaxial wafer is internally provided with:

the first heavily doped body regions are provided with a plurality of first heavily doped body regions which extend downwards from the top of the epitaxial wafer respectively and are spaced from each other; the bottom surface of the first heavily doped body region is higher than the bottom surface of the second lightly doped voltage-resistant region;

The second heavily doped source region extends downwards from the top surface of the epitaxial wafer and is connected with the top surface of the first heavily doped body region;

the gate dielectric is provided with a plurality of gate dielectrics, the cross sections of the gate dielectrics are of U-shaped structures, the gate dielectrics respectively extend downwards from the top surface of the second heavily doped source region, pass through the first heavily doped body region and extend into the second lightly doped voltage-resistant region;

Polysilicon extending downwards from the top surface of the gate dielectric to fill the gate dielectric;

the Schottky contact metal is arranged between the adjacent first heavily doped body regions, and the end parts of the Schottky contact metal extend into the first heavily doped body regions; the Schottky contact metal is connected with the second lightly doped voltage-resistant region to form Schottky contact; the upper surface of the Schottky contact metal is lower than the lower surface of the second heavily doped source region;

an ohmic contact metal extending upward from a top surface of the schottky contact metal and passing through the first heavily doped body region, the second heavily doped source region and the isolation layer in sequence;

the grid metal extends downwards into the polysilicon from the top surface of the isolation layer and forms ohmic contact with the polysilicon;

the first doping region and the second doping region are opposite in doping type, namely a P region and an N region respectively, or an N region and a P region respectively.

The invention has the beneficial effects that:

According to the invention, the schottky contact diode is integrated at the bottom of the source electrode groove by preparing the first heavily doped body regions at intervals and controlling the depth of the source electrode groove, the purpose of reducing the follow current loss of the body diode is achieved by utilizing the low starting voltage and high current characteristics of the schottky diode, meanwhile, the second lightly doped voltage-resistant region of the schottky diode is provided with the first heavily doped body regions at intervals, the first heavily doped body regions, the second lightly doped voltage-resistant region and the super junction structure of the first heavily doped body regions are formed at two sides of the second lightly doped voltage-resistant region, the super junction structure has an excellent shielding effect, the electric field intensity of the second lightly doped voltage-resistant region is effectively reduced, and the reverse electric leakage of the integrated schottky diode is further reduced.

The structure of the second lightly doped voltage-resistant region below the first heavily doped body region of the device is consistent with that of a common trench MOSFET, no special extra process step is needed to reduce the reverse leakage of the integrated Schottky diode, the preparation process of the device is completely compatible with that of the conventional trench MOSFET, only two process steps of preparing a source trench and Schottky contact metal are needed to be additionally added, compared with the existing comparison document, the special extra process step is reduced to reduce the reverse leakage of the integrated Schottky diode, the forward current capacity of the integrated SBD and the forward current capacity of the MOSFET are not influenced, the promotion of the commercialization process is facilitated, and the device has higher commercial value.

Drawings

FIG. 1 is a process flow diagram of the present invention;

Fig. 2 is a schematic cross-sectional structure of the device in step S100;

fig. 3 is a schematic cross-sectional structure of the device in step S200;

fig. 4 is a schematic cross-sectional structure of the device in step S300;

FIG. 5 is a schematic diagram of a structure for preparing a gate dielectric in a trench;

fig. 6 is a schematic diagram of a structure for preparing polysilicon in a trench;

FIG. 7 is a schematic cross-sectional structure of a separator;

Fig. 8 is a schematic cross-sectional structure of a source trench;

fig. 9 is a schematic diagram of a structure for preparing a schottky contact metal at the bottom of a source trench;

fig. 10 is a schematic view of a structure for preparing an ohmic contact metal inside a source trench;

FIG. 11 is a schematic cross-sectional view of a gate metal fenestration;

fig. 12 is a schematic cross-sectional structure of a gate metal;

fig. 13 is a schematic structural diagram of a drain metal preparation;

in the figure, 1 is an epitaxial wafer, 2 is a first heavily doped body region, 3 is a second heavily doped source region, 4 is a gate trench, 5 is a gate dielectric, 6 is polysilicon, 7 is an isolation layer, 8 is a source trench, 9 is a schottky contact metal, 10 is an ohmic contact metal, 11 is a gate metal window, 12 is a gate metal, 13 is a drain metal, 14 is a second heavily doped substrate region, and 15 is a second lightly doped withstand voltage region.

Detailed Description

Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the invention.

In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.

The invention is described below with reference to fig. 1-13;

Step S100, preparing a plurality of first heavily doped body regions 2 which are mutually spaced in the epitaxial wafer 1, referring to FIG. 2;

Step S110, adopting a photoetching process, and protecting the outer area of the first heavily doped body region 2 by using a mask; forming first heavily doped body regions 2 spaced apart from each other by a diffusion process or an ion implantation process;

The doping types of the first doping region and the second doping region are opposite, namely a P region and an N region respectively, or an N region and a P region respectively. Preferably, the first doped region (including the first heavily doped body region 2) is a P region, and the second doped region (including the second heavily doped source region 3, the second heavily doped substrate region 14 and the second lightly doped voltage-resistant region 15) is an N region.

Correspondingly, the epitaxial wafer 1 of the embodiment is a Si-based N-type epitaxial wafer;

The epitaxial wafer 1 consists of a second heavily doped substrate region 14 and a second lightly doped voltage-resistant region 15 from bottom to top, wherein the thickness of the epitaxial wafer 1 is 100-2000um, the thickness of the second heavily doped substrate region 14 is 90-1500um, the thickness of the second lightly doped voltage-resistant region 15 is 10-500um, the thickness of the first heavily doped body region 2 is 1-5um, the spacing distance is set to 1-10um, the doping concentration range of N type doping is 1e ¹⁴.cm^-3-1e²⁰.cm^-3, the doping concentration range of P type doping is 1e ¹⁵.cm^-3-1e²⁰.cm^-3, and related parameter setting and device electrical design are related;

In this embodiment, the thickness of the epitaxial wafer 1 is 350um, the thickness of the second heavily doped substrate region 14 is 330um, the doping concentration is 1e ¹⁹.cm^-3, the thickness of the second lightly doped voltage-resistant region 15 is 20um, the doping concentration is 1e ¹⁶.cm^-3, the thickness of the first heavily doped body region 2 is 2um, the spacing distance is 1um, the doping concentration is 3e ¹⁸.cm^-3, and the ion implantation process is used to prepare the first heavily doped body region 2.

Step S200, preparing a second heavily doped source region 3 in the epitaxial wafer 1, as shown in fig. 3;

Step S210, adopting a photoetching process, and protecting the outer area of the second heavy doping source region 3 by using a mask; forming a second heavily doped source region 3 by a diffusion process or an ion implantation process;

Correspondingly, the second heavily doped source region 3 extends downwards from the top surface of the first heavily doped body region 2, the bottom surface of the second heavily doped source region is higher than the bottom surface of the first heavily doped body region 2, the thickness is set to be 0.5-3um, the doping concentration range is 1e ¹⁸.cm^-3-1e²⁰.cm^-3, and the related parameter setting is related to the electrical design of the device;

In this embodiment, the thickness of the second heavily doped source region 3 is 1um, the doping concentration is 1e ^19.cm^-3, and the second heavily doped source region 3 is prepared by using an ion implantation process.

Step S300, preparing a gate trench 4 in the epitaxial wafer 1, which penetrates the second heavily doped source region 3 and the first heavily doped body region 2 in sequence downwards, as shown in fig. 4;

Step S310, adopting a photoetching process, and protecting the outer area of the grid groove 4 by using a mask; forming a gate trench 4 by an etching process;

Correspondingly, the gate trench 4 extends downwards from the top surface of the epitaxial wafer 1, the bottom surface of the gate trench is lower than the bottom surface of the first heavily doped body region 2 and higher than the bottom surface of the second lightly doped voltage-resistant region 15, the width range is set to be 1-10um, and related parameter settings are related to device electrical design;

In this embodiment, the gate trench 4 has a depth of 4um and a width of 2um, and the trench 4 is prepared using an ICP dry etching process.

Step S400, sequentially preparing a gate dielectric 5 and polysilicon 6 in the gate trench 4, as shown in fig. 5 and 6;

Step S410, protecting the outer area of the gate trench 4 by using a mask through a photoetching process, and preparing a gate dielectric 5 in the gate trench 4 by using a thermal oxygen technology;

Step S420, preparing polysilicon 6 in the gate trench 4 by chemical vapor deposition;

Correspondingly, the gate dielectric 5 is positioned in the groove 4 and is respectively contacted with the second heavily doped source region 3, the first heavily doped body region 2 and the second lightly doped voltage-resistant region 15, the polysilicon 6 is positioned in the groove 4, fills the groove 4 and is contacted with the gate dielectric 5, the upper surface of the polysilicon 6 and the upper surface of the gate groove 4 are horizontal, the gate dielectric 5 is made of SiO ₂, and the thickness is set to be 40-500nm;

In this example, 80nm of SiO ₂ was prepared as gate dielectric 5 using a thermal oxygen technique and polysilicon 6 was prepared using chemical vapor deposition.

Step S500, depositing an isolation layer 7 on the epitaxial wafer 1, and windowing to prepare a source electrode groove 8, wherein the bottom of the source electrode groove 8 extends into the adjacent first heavily doped body region 2, and the width of the groove is larger than the interval width of the first heavily doped body region 2, as shown in reference to figures 7 and 8;

Step S510, preparing an isolation layer 7 by chemical vapor deposition, protecting the outer area of a source electrode groove 8 by using a mask through a photoetching process, windowing the source electrode groove 8 through an etching process, wherein the bottom of the source electrode groove 8 extends to the inside of a first heavy doping body region 2, and the width of the groove is larger than the interval width of the first heavy doping body region 2;

Correspondingly, the isolation layer 7 plays a role in protection, the material is SiO ₂ or Si ₃N₄, the thickness is set to be 10-5000nm, the source electrode groove 8 is prepared by ICP dry etching, the source electrode groove 8 extends downwards from the top surface of the isolation layer 7 to the inside of the first heavily doped body region 2, the bottom surface of the source electrode groove is higher than the bottom surface of the first heavily doped body region 2, the groove width is larger than the interval width of the first heavily doped body region 2, the width range is set to be 1-10um, and related parameter settings and device electrical design are related;

In this example, the source trench 8 was prepared using Si ₃N₄ as the isolation layer 7, the thickness was set to 200nm, the source trench 8 was 2um deep and 1.5um wide by using ICP dry etching window, and the source trench 8 was prepared using ICP dry etching process.

Step S600, preparing a Schottky contact metal 9 at the bottom of the source electrode groove 8, forming Schottky contact with the second lightly doped voltage-resistant region 15, wherein the upper surface of the Schottky contact metal 9 is lower than the lower surface of the second heavily doped source region 3, and referring to FIG. 9;

Step S610, preparing a Schottky contact metal 9 at the bottom of the source electrode groove 8 through a stripping process or an etching process, wherein the Schottky contact metal 9 and the second lightly doped voltage-resistant region 15 form a Schottky contact, and the upper surface of the Schottky contact metal 9 is lower than the lower surface of the second heavily doped source region 3;

Correspondingly, the Schottky contact metal 9 is arranged at the bottom of the source electrode groove 8 and forms Schottky contact with the second lightly doped voltage-resistant region 15, and the upper surface of the Schottky contact metal is lower than the lower surface of the second heavily doped source region 3;

In this embodiment, a lift-off process is used to prepare a 200nm thick Ni/Al two-layer metal as the schottky contact metal 9 at the bottom of the source trench 8, and Ni and the second lightly doped withstand voltage region 15 form schottky contacts.

Step S700, preparing an ohmic contact metal 10 in the source trench 8, forming ohmic contact with the first heavily doped body region 2 and the second heavily doped source region 3, wherein the ohmic contact metal 10 and the schottky contact metal 9 in the source trench together form a source metal, as shown with reference to fig. 10;

Step S710, ohmic contact metal 10 is prepared in the source electrode groove 8 through a stripping process or an etching process, ohmic contact is formed between the ohmic contact metal 10, the first heavily doped body region 2 and the second heavily doped source region 3, and the ohmic contact metal 10 and the Schottky contact metal 9 in the source electrode groove jointly form source electrode metal;

Correspondingly, an ohmic contact metal 10 is arranged in the source electrode groove 8, and the lower surface of the ohmic contact metal 10, the horizontal upper surface of the Schottky contact metal 9 and the horizontal upper surface of the isolation layer 7 form ohmic contact with the first heavily doped body region 2 and the second heavily doped source region 3;

In this embodiment, a lift-off process is used to prepare 1.8um thick Ti/Al two-layer metal as the ohmic contact metal 10 in the source trench 8, and the Ti forms ohmic contact with the first heavily doped body region 2 and the second heavily doped source region 3.

In step S800, a gate metal 12 is prepared by opening a window in the gate trench 4, a drain metal 13 is prepared on the back surface of the epitaxial wafer 1, and the entire device is prepared, as shown in fig. 11, 12 and 13.

Step S810, protecting the outer area of the windowed position of the gate groove 4 by using a mask through a photoetching process, windowing the windowed position of the gate groove 4 by using an etching process, preparing gate metal 12, preparing drain metal 13 at the bottom of the epitaxial wafer 1 by using a thinning process and a back gold process, and finishing the preparation of the whole device;

Correspondingly, the window depth of the gate groove 4 is larger than the thickness of the isolation layer 7, the gate metal 12 extends downwards into the polysilicon 6 from the top surface of the isolation layer 7 to form ohmic contact with the polysilicon 6, and the drain metal 13 forms ohmic contact with the second heavily doped substrate region 14 on the bottom surface of the epitaxial wafer 1;

in this embodiment, a window is opened at the gate trench 4 by an etching process, the window depth is 1um, a lift-off process is used to prepare a 1um thick Ti/Al two-layer metal as the gate metal 12, ohmic contact is formed with the polysilicon 6, a thinning process is used to thin the 350um thick epitaxial wafer 1 to 180um, and a Ti/Al two-layer metal is used to prepare the drain metal 13.

A MOSFET for enhancing the free-wheeling capability of a body diode comprises drain metal 13, an epitaxial wafer 1 and an isolation layer 7 which are sequentially arranged from bottom to top;

the epitaxial wafer 1 is internally provided with:

the first heavily doped body region 2 is provided with a plurality of first heavily doped body regions which extend downwards from the top of the epitaxial wafer 1 respectively and are spaced from each other; the top surface of the first heavily doped body region 2 is lower than the top surface of the epitaxial wafer 1, and the bottom surface is higher than the bottom surface of the second lightly doped voltage-resistant region 15;

A second heavily doped source region 3 extending downward from the top surface of the epitaxial wafer 1 and connected to the top surface of the first heavily doped body region 2;

The gate dielectric 5 is provided with a plurality of gate dielectric bodies, the cross sections of which are U-shaped structures, and extend downwards from the top surfaces of the second heavily doped source regions 3 respectively, pass through the first heavily doped body regions 2 and extend into the second lightly doped voltage-resistant regions 15; namely, the gate dielectric 5 is respectively connected with the second heavily doped source region 3, the first heavily doped body region 2 and the second lightly doped voltage-resistant region 15;

Polysilicon 6 extending downwards from the top surface of the gate dielectric 5 and filling the gate dielectric 5;

The schottky contact metal 9 is arranged between the adjacent first heavily doped body regions 2, and the end parts of the schottky contact metal 9 extend into the first heavily doped body regions 2, i.e. the lateral width of the schottky contact metal 9 is larger than the interval width of the adjacent first heavily doped body regions 2; the Schottky contact metal 9 is connected with the second lightly doped voltage-resistant region 15 to form Schottky contact; the upper surface of the Schottky contact metal 9 is lower than the lower surface of the second heavily doped source region 3;

An ohmic contact metal 10 extending upward from the top surface of the schottky contact metal 9 and passing through the first heavily doped body region 2, the second heavily doped source region 3 and the isolation layer 7 in sequence, the upper surface of which is flush with the upper surface of the isolation layer 7; ohmic contact metal 10 forms ohmic contact with first heavily doped body region 2 and second heavily doped source region 3, and forms source metal together with schottky contact metal 9;

a gate metal 12 extends from the top surface of the isolation layer 7 down into the polysilicon 6 to form an ohmic contact with the polysilicon 6.

The drain metal 13 forms ohmic contact with the second heavily doped substrate region 14 on the bottom surface of the epitaxial wafer 1.

The invention has the following advantages:

The schottky contact diode is integrated at the bottom of the source electrode groove 8 by preparing the first heavily doped body regions 2 at intervals and controlling the depth of the source electrode groove 8, the purpose of reducing the follow current loss of the body diode is achieved by utilizing the low starting voltage and high current characteristics of the schottky diode, meanwhile, the second lightly doped voltage-resistant regions 15 of the schottky diode are arranged at two sides of the first heavily doped body regions 2 at intervals, a super junction structure of the first heavily doped body regions 2, the second lightly doped voltage-resistant regions 15 and the first heavily doped body regions 2 is formed, the super junction structure has an excellent shielding effect, the electric field strength of the second lightly doped voltage-resistant regions 15 is effectively reduced, and then the reverse electric leakage of the integrated schottky diode is reduced.

The structure of the second lightly doped voltage-resistant region 15 below the first heavily doped body region 2 of the device is consistent with that of a common trench MOSFET, no special extra process step is needed to reduce the reverse leakage of the integrated Schottky diode, the preparation process of the device is fully compatible with that of a traditional trench MOSFET, only two process steps of preparing the source trench 8 and the Schottky contact metal 9 are needed to be additionally added, compared with the existing comparison document, the device reduces the reverse leakage of the integrated Schottky diode by reducing the special extra process step, the forward current capacity of the integrated SBD and the forward current capacity of the MOSFET are not influenced, the promotion of commercialization process is facilitated, and the device has higher commercial value.

For the purposes of this disclosure, the following points are also described:

(1) The drawings of the embodiments disclosed in the present application relate only to the structures related to the embodiments disclosed in the present application, and other structures can refer to common designs;

(2) The embodiments disclosed herein and features of the embodiments may be combined with each other to arrive at new embodiments without conflict;

the above is only a specific embodiment disclosed in the present application, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. A method of fabricating a MOSFET for enhancing the freewheeling capability of a body diode, comprising the steps of:

step S100, preparing first heavily doped body regions (2) which are mutually spaced in an epitaxial wafer (1);

step S200, preparing a second heavily doped source region (3) in the epitaxial wafer (1);

step S300, preparing a grid groove (4) in the epitaxial wafer (1);

step S400, sequentially preparing a gate dielectric (5) and polysilicon (6) in the groove (4);

Step S500, depositing an isolation layer (7) on the epitaxial wafer (1), windowing to prepare a source electrode groove (8), wherein the bottom of the source electrode groove (8) extends to the inside of the first heavily doped body region (2), and the width of the groove is larger than the interval width of the first heavily doped body region (2);

Step S600, preparing Schottky contact metal (9) at the bottom of the source electrode groove (8), forming Schottky contact with the second lightly doped voltage-resistant region (15), wherein the upper surface of the Schottky contact metal (9) is lower than the lower surface of the second heavily doped source region (3);

Step S700, preparing ohmic contact metal (10) in a source groove (8), forming ohmic contact with a first heavily doped body region (2) and a second heavily doped source region (3), wherein the ohmic contact metal (10) and a Schottky contact metal (9) in the source groove jointly form source metal;

Step S800, window is opened at the gate groove (4), gate metal (12) is prepared, drain metal (13) is prepared at the back of the epitaxial wafer (1), and the whole device is prepared.

2. A method of manufacturing a MOSFET for enhancing the freewheeling capability of a body diode according to claim 1, wherein step S100 comprises:

step S110, adopting a photoetching process, and protecting the outer area of the first heavily doped body region (2) by using a mask; a plurality of first heavily doped body regions (2) are formed at intervals by a diffusion process or an ion implantation process.

3. A method for manufacturing a MOSFET for enhancing a body diode freewheel capability according to claim 1 characterized in that step S200 comprises:

Step S210, adopting a photoetching process, and protecting the outer area of the second heavy doping source region (3) by using a mask; the second heavily doped source region (3) is formed by a diffusion process or an ion implantation process.

4. A method of manufacturing a MOSFET having enhanced body diode freewheel capability according to claim 1 characterized in that step S300 comprises:

step S310, adopting a photoetching process, and protecting the outer area of the grid groove (4) by using a mask; the gate trench (4) is formed by an etching process.

5. A method of manufacturing a MOSFET for enhancing the freewheeling capability of a body diode according to claim 1, wherein step S400 comprises:

Step S410, protecting the outer area of the gate trench (4) by using a mask through a photoetching process, and preparing a gate dielectric (5) in the gate trench (4) by using a thermal oxidation technology;

in step S420, polysilicon (6) is prepared in the gate trench (4) by chemical vapor deposition.

6. A method of manufacturing a MOSFET having enhanced body diode freewheel capability according to claim 1 characterized in that step S500 comprises:

Step S510, preparing an isolation layer (7) through chemical vapor deposition, protecting the outer area of the source groove (8) through a photoetching process by using a mask, windowing the source groove (8) through an etching process, wherein the bottom of the source groove (8) extends to the inside of the first heavily doped body region (2), and the width of the groove is larger than the interval width of the first heavily doped body region (2).

7. A method of manufacturing a MOSFET for enhancing the freewheeling capability of a body diode according to claim 1, wherein step S600 comprises:

In step S610, a schottky contact metal (9) is prepared at the bottom of the source trench (8) through a lift-off process or an etching process, the schottky contact metal (9) and the second lightly doped voltage-resistant region (15) form schottky contact, and the upper surface of the schottky contact metal (9) is lower than the lower surface of the second heavily doped source region (3).

8. A method for manufacturing a MOSFET for enhancing the freewheeling capability of a body diode according to claim 1, wherein step S700 comprises:

In step S710, ohmic contact metal (10) is prepared in the source trench (8) by a lift-off process or an etching process, the ohmic contact metal (10) forms ohmic contact with the first heavily doped body region (2) and the second heavily doped source region (3), and the ohmic contact metal (10) and the schottky contact metal (9) in the source trench together form the source metal.

9. A method of manufacturing a MOSFET for enhancing the freewheeling capability of a body diode according to claim 1, wherein step S800 comprises:

Step S810, protecting the outer area of the windowed position of the gate groove (4) by using a mask through a photoetching process, windowing the windowed position of the gate groove (4) by using an etching process, preparing the gate metal (12), and preparing the drain metal (13) at the bottom of the epitaxial wafer (1) by using a thinning process and a back gold process, so that the whole device is prepared.

10. A MOSFET for enhancing the free-wheeling capability of a body diode, prepared by a method for preparing a MOSFET for enhancing the free-wheeling capability of a body diode according to any one of claims 1 to 9, characterized by comprising a drain metal (13), an epitaxial wafer (1) and an isolation layer (7) which are arranged in sequence from bottom to top;

The epitaxial wafer (1) is internally provided with:

The first heavily doped body regions (2) are provided with a plurality of first heavily doped body regions which extend downwards from the top of the epitaxial wafer (1) respectively and are spaced from each other; the bottom surface of the first heavily doped body region (2) is higher than the bottom surface of the second lightly doped voltage-resistant region (15);

A second heavily doped source region (3) extending downwards from the top surface of the epitaxial wafer (1) and connected with the top surface of the first heavily doped body region (2);

the gate dielectric (5) is provided with a plurality of gate dielectric structures with U-shaped sections, and the gate dielectric structures respectively extend downwards from the top surface of the second heavily doped source region (3), pass through the first heavily doped body region (2) and extend into the second lightly doped voltage-resistant region (15);

polysilicon (6) extending downwards from the top surface of the gate dielectric (5) and filling the gate dielectric (5);

A schottky contact metal (9) arranged between adjacent first heavily doped body regions (2) and the end parts of which extend into the first heavily doped body regions (2); the Schottky contact metal (9) is connected with the second lightly doped voltage-resistant region (15) to form Schottky contact; the upper surface of the Schottky contact metal (9) is lower than the lower surface of the second heavily doped source region (3);

An ohmic contact metal (10) extending upward from the top surface of the schottky contact metal (9) and passing through the first heavily doped body region (2), the second heavily doped source region (3) and the isolation layer (7) in sequence;

a gate metal (12) extending from the top surface of the isolation layer (7) down into the polysilicon (6) to form ohmic contact with the polysilicon (6);

the first doping region and the second doping region are opposite in doping type, namely a P region and an N region respectively, or an N region and a P region respectively.