CN118966140A

CN118966140A - A method for identifying FPC areas and dividing wiring channels

Info

Publication number: CN118966140A
Application number: CN202410951241.8A
Authority: CN
Inventors: 吴皓莹; 胡頔; 徐宁
Original assignee: Wuhan University of Technology WUT
Current assignee: Wuhan University of Technology WUT
Priority date: 2024-07-16
Filing date: 2024-07-16
Publication date: 2024-11-15

Abstract

The invention discloses a FPC area identification and wiring channel division method, which comprises the following steps: triangulating the FPC wiring area; an ETP region division model is constructed, and an FPC wiring region is divided into an escape region E region, a triangular region T region and a connection region P region based on triangles obtained by triangulation, wherein the method comprises the following steps: dividing an escape area and a channel area; dividing a channel area into a triangular area and a connecting area; and carrying out global wiring of the channel region. In addition, the subsequent wiring is completed in consideration of the power supply integrity. The invention provides a global wiring technology for FPC board area identification and channel area, solves the problems of insufficient area division and unreasonable global wiring of the channel area in the traditional FPC wiring, and realizes the automatic processing of the wiring process and the remarkable improvement of the wiring quality through accurate area division and optimized wiring strategies. The invention can effectively optimize the wiring structure of the FPC board, reduce the intersection and the overlapping of wiring paths and improve the performance and the reliability of the FPC circuit board.

Description

FPC (Flexible printed Circuit) area identification and wiring channel division method

Technical Field

The invention belongs to the technical field of flexible circuit boards, and particularly relates to an FPC (flexible printed circuit) area identification and wiring channel division method.

Background

A flexible circuit board (Flexible Printed Circuit, abbreviated as FPC) is one type of Printed Circuit Board (PCB), which is made of a flexible substrate and can be bent and folded. Compared with the traditional PCB, the FPC has more flexible structure and better heat dissipation, can provide higher performance for high-density interconnected circuits, and is widely applied to small-sized mobile communication equipment and wearable equipment.

At present, research on wiring problems of very large scale integrated circuits (VERY LARGE SCALE Integration Circuit, VLSI) is continuously carried out, but research on the wiring problems of FPCs is still carried out in the primary stage, and particularly industrial FPC wiring is seriously dependent on manual adjustment. The FPC routing problem is different from the IC routing problem because punching holes in the FPC can severely affect signal integrity. The horizontal or vertical wiring pattern of the IC is not applicable in the FPC, and thus a wiring algorithm specific to the FPC needs to be found. And the irregular boundaries of the FPC are a mandatory constraint on the routing path. In addition, very little consideration is given to the irregular routing region constraints in VLSI research.

The routing problem must take into account power integrity, and power and ground planes are typically provided in a multilayer routing area, VLSI. The power and ground networks are introduced to the power or ground planes through a minimum Steiner tree, whereas FPCs are typically not specifically configured for power or ground planes due to the nature of their flexible materials and relatively compact wiring resources.

In summary, the pin distribution of FPCs is more prone to be clustered together to form areas, with the routing areas generally exhibiting irregular polygonal shapes, relative to conventional PCBs. The paths of the different lines often share some common area to ensure stability and reliability of the signal transmission. In addition, FPC routing has a consistency requirement for the topology of the local path. At present, research on the problem of automatic wiring of FPCs is still in a preliminary exploration stage. For the scenario of FPC automatic wiring, there are still other aspects to be further studied, including the following:

and (3) area identification: to realize automatic wiring of the FPC, the area type should be identified first so as to divide the FPC board into different functional areas, and then different algorithms should be designed for the different functional areas, respectively, so as to achieve a better wiring effect. The automatic routing algorithm needs to assign them to different areas with accurate identification based on the pin locations on the FPC. Particularly in the case where the FPC wiring area generally exhibits an irregular shape, accurate identification of the area has a certain difficulty. Currently, there is no special processing method for the division of the wiring area.

Dividing a channel: the FPCs are to build routing paths in common channel areas of the nets that are topologically consistent with the facing bus. I.e. signal lines of the same location or function should employ similar routing strategies and path planning. Therefore, global routing operation is required to be performed on the FPC first, so as to obtain the approximate routing ranges of the pins in different areas, and we call each different range as a routing channel. Dividing the signals into different channels and each of the detailed routing operations can simplify the complexity of the detailed routing problem.

The power integrity is satisfied: when the circuit design is completed, the arrangement of the power lines is considered, the length of the power lines can be shortened by reasonably arranging the power lines, the resistance and inductance of the power lines are reduced, the concentration of local temperature is reduced, and the heat dissipation efficiency and the power stability are improved. However, because the wiring layer resources of the FPC are tense, the power layer is not usually set, and the wiring area of the power line needs to be maximized in the common signal layer to ensure the power integrity.

Algorithm efficiency and convergence: the automatic wiring algorithm needs to have high efficiency and convergence, and can generate a wiring result meeting design requirements in a reasonable time. For example, if all wiring is done directly using the a-x algorithm, the memory and time requirements would be unacceptable. Meanwhile, the expandability and applicability of the algorithm are also required to be considered so as to adapt to FPC wiring design tasks with different scales and complexity.

Disclosure of Invention

The invention aims to provide an FPC area identification and wiring channel division method, which solves the problem of FPC wiring area identification.

The technical scheme of the invention is as follows:

a FPC area recognition and wiring channel division method, the method comprising:

Triangulating the FPC wiring area;

an ETP region division model is constructed, and an FPC wiring region is divided into an escape region E region, a triangular region T region and a connection region P region based on triangles obtained by triangulation, wherein the method comprises the following steps:

Dividing the escape area and the channel area, comprising:

establishing a mapping relation between the pins and the triangles to identify whether the pins are distributed in each triangle or not, and further classifying the triangles into two types;

initial clustering by merging triangles: the method comprises the steps of aggregating triangles of the same type and adjacent triangles together to form triangle sets of different types, so that a plurality of subareas are obtained, and area types are allocated to each subarea; the region type is divided into a subregion containing pins and a subregion without pins;

Updating the sub-region: determining representative points of the sub-areas containing the pins and representative points of the sub-areas without the pins, and judging whether the representative points of the sub-areas without the pins exist within a range of a certain distance around the representative points of the sub-areas containing the pins; if yes, the connecting line between the representative points is positioned in the wiring area, and the area type of the latter is updated into a subarea containing pins;

Merging the subareas, and constructing an escape area and a channel area: merging the same type of adjacent subareas, wherein the subareas containing the pins are escape areas, and the rest subareas without the pins are channel areas;

dividing a channel area into a triangular area and a connecting area, wherein the triangular area is a triangle with three sides having wire net in and out, and the connecting area is a triangle with two sides having wire net in and out;

And carrying out global wiring of the channel region.

Further, triangulating the FPC routing area, comprising:

Encrypting the boundary point set of the FPC wiring area by using a distance threshold T;

creating a delusian triangle network based on the encrypted point set;

determining the gravity center of each triangle, and screening the triangles with the gravity centers in the FPC wiring area;

A triangular partition graph G _CDT (V, E) is constructed, where V represents a triangle and E represents the adjacency of the triangle.

Further, determining the representative point of the sub-region containing the pin and the representative point of the sub-region not containing the pin includes:

Regarding the subarea containing the pins, setting all the pins as representative point candidate points, and taking the representative point candidate point closest to the subarea without the pins as the representative point when judging whether the representative point of the subarea without the pins exists within a range of a certain distance around the representative point of the subarea with the pins;

For the subregion without pins, the center of gravity is taken as a representative point.

Further, dividing the channel region into a triangle region and a connection region includes:

Identifying the channel region side chains as a plurality of unconnected side chains according to the discontinuity of the channel region side chains on the original boundary;

and finding triangles with three vertexes on three different side chains, namely a triangle area, and the rest triangles of the channel area are connection areas.

Further, performing global routing of the channel region includes:

acquiring an initial passing point on an escape line; the escape line is a dividing line of the escape area and the channel area, the initial passing point is a point where a wire net passes on the escape line, and the wire net is connected with pins in the two escape areas;

Constructing an initial wiring diagram G _Route by taking a triangle as a basic unit, and adding initial nodes of a wire net into the wiring diagram G _Route;

Searching a wire network path in the wiring diagram based on a breadth first algorithm BFS and according to a method of dynamically adding and deleting nodes, updating the wiring diagram G _Route and recording the total capacity of the path passed by the nodes;

checking whether the bus fan-out result meets the capacity requirement of the channel area; if so, wiring is completed.

Further, the wiring diagram is represented by G _Route (V, E), V is formed by points of edges through which the wired network passes, the position coordinates of each point and the information of the edge where each point is located are stored in V, and E represents that the nodes belong to the same delaunay triangle;

Determining the net of each subarea in the channel region and the passing point sequence of each subarea on the boundary of the subarea; since each net set has only a unique path, the triangles traversed are determined, thereby yielding the net traversed in each triangle area.

Further, the method for dynamically adding and deleting nodes ensures that the network topology is not crossed, and the method for dynamically adding and deleting nodes is as follows:

For a triangular area T, an initial wiring diagram is divided into four areas by connecting lines of nodes on three sides of a triangle; when a path is newly added, deleting two nodes of a connecting line with the same trend as the newly added path, adding a new node at the middle point of line segments at two sides of the deleted node respectively, adding the connecting line of the node to the overall wiring diagram if the connecting line of the node does not conflict with the laid path, and adding the connecting line of the node to the overall wiring diagram if the connecting line of the node conflicts with the laid path; the area divided by the node connection line is the net path;

For the connection region P, the initial wiring diagram is divided into two regions by connecting lines of nodes on two sides of a triangle, the side of the triangle positioned on the side chain is a boundary constraint side, and no node is arranged; when a path is newly added, deleting two nodes of a connecting line, adding a new node at the middle point of line segments at two sides of the deleted node respectively, wherein the connecting line of the node is not in conflict with the laid path, and the node is added into the overall wiring diagram, and if the connecting line of the node is in conflict with the laid path, the node is not added into the overall wiring diagram; the area divided by the node connection lines is the net path.

Further, the method further comprises:

Considering power integrity, perfecting wiring results, including:

the power line is divided into a variable line width power line and a constant line width wire net;

Firstly, determining a side chain related to a variable-line-width power line;

And wiring the wire net with the constant line width along the other side chain according to the minimum line width and the line spacing, and reserving the rest wiring resources for the power line with the variable line width.

Further, the following two conditions are to be satisfied when the variable line width power line is laid:

(1) The occupied area is wide, and the actual line width of each part on the line network path is larger than the preset minimum line width;

(2) And the position of the boundary of the FPC is set, so that interference to other wires is reduced.

A PCB/FPC that completes FPC routing area division using the FPC area identification and routing channel division method of any one of the above.

Compared with the prior art, the invention has the following advantages:

The invention provides a global wiring technology for FPC board area identification and channel area, solves the problems of insufficient area division and unreasonable global wiring of the channel area in the traditional FPC wiring, and realizes the automatic processing of the wiring process and the remarkable improvement of the wiring quality through accurate area division and optimized wiring strategies. The invention can effectively optimize the wiring structure of the FPC board, reduce the intersection and the overlapping of wiring paths and improve the performance and the reliability of the FPC circuit board.

Drawings

FIG. 1 is a general frame diagram of a FPC area identification and routing channel division method;

FIG. 2 is a diagram of the results of Delaunay triangulation;

FIG. 3 is a schematic diagram of the escape area and the channel area before and after identification; wherein fig. 3 (a) is a schematic diagram before recognition, and fig. 3 (b) is a schematic diagram after recognition;

FIG. 4 is a graph of triangle recognition results for different FPCs;

FIG. 5 is a schematic diagram of a dynamic add-drop node arrangement; wherein FIG. 5 (a) is an initial diagram of the T area, FIG. 5 (b) is an updated diagram of the net after passing through the T area, FIG. 5 (c) is an initial diagram of the P area, and FIG. 5 (d) is an updated diagram of the net after passing through the P area;

FIG. 6 is a global routing result graph;

FIG. 7 is a schematic diagram of a reserved power wiring resource;

FIG. 8 is a graph of the result of a wiring of the present invention;

Fig. 9 is a graph of another wiring result of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention. In addition, the technical features of the embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.

The invention provides a power-integrity-oriented FPC (flexible printed circuit) area identification and wiring channel division method, and belongs to global wiring planning technology in Flexible Printed Circuit (FPC) automatic wiring. The method can effectively identify various functional areas in the FPC, and provides a brand-new wiring channel dividing strategy, so that the connection relation between signals and a power supply is considered, and the rationality and continuity of wiring are ensured. By introducing the area identification and wiring channel division algorithms, a solid foundation can be laid for the subsequent detailed wiring work, and the wiring efficiency and quality are improved.

The overall framework of the present invention is shown in fig. 1, divided into four sections: preprocessing FPC wiring data, dividing wiring areas, overall wiring of channel areas and finishing wiring in consideration of power supply integrity. And finishing the delaunay triangulation of the wiring area according to given wiring information, and then jointly constructing an ETP area division model, namely the division of Escape area (E area), triangle area (T area) and connection area (Passage area) by combining the distribution and the graph relation of pins. And then according to a channel region overall wiring algorithm meeting channel capacity constraint in a two-dimensional plane, realizing that the network path topologies in the same layer are not crossed, and finally completing subsequent wiring by considering the power supply integrity.

Pretreatment of FPC wiring data

The Delaunay triangulation (Delaunay Triangulation, DT) has very important theoretical significance and application value in the aspects of environment measurement, pattern recognition, center axis extraction and the like, and has a plurality of advantages in computer graphics and spatial data processing. The triangular network obtained by performing Delaue triangulation on the discrete point set on the plane has the characteristics of empty circles, maximum minimum angles and the like.

In the FPC, the outer boundary of the wiring region is an irregular polygon, the division of the region by a rectangular frame requires additional complicated processing of the region, and the expressive properties of the triangle to the region are flexible, so the present invention recognizes and divides the wiring region by using the triangle.

When the wiring area of the FPC is processed by the Delaunay triangulation algorithm, the distance threshold T of the boundary point set P [1 … n ] and the encryption boundary point of the wiring area is input. The output is a G _CDT (V, E) graph representing the triangle convex hull within the region, where V represents the triangle and E represents the adjacency between the triangles. The flow is as follows:

(1) Encrypting the boundary point set of the wiring area by using a threshold T;

(2) Creating Jiande Lao internal triangle network;

(3) Checking whether the gravity center of the constructed Delaunay triangle is positioned in the frame or not, and screening the triangle in the area;

(4) And constructing a G _CDT diagram by taking triangles in the region as nodes.

Wherein the distance threshold T is mainly used to divide the boundary line of the wiring area to increase the boundary point. The pseudocode is shown in table 1.

TABLE 1 construction of the G _CDT algorithm pseudo-code Table

The delaunay triangulation results are shown in fig. 2.

2. Construction of ETP region division model

2.1 Escape and channel region identification

In FPCs, the channel area is typically only routed for power, no device is placed, and the circuit is inhibited from performing layer-changing operations in that area. While the escape area is a pad-dense area, typically at the end of the FPC, allowing the net to be layered in this area. Thus, the region can be divided into two adjacent portions by establishing a dividing line. In CDT, any side of any triangle can be a candidate side of the split line. By establishing the mapping relation between the pins and the triangles in the CDT, the channel area and the escape area can be rapidly identified, and the escape area is formed by adjacent triangles. The different sub-areas are marked with area numbers and types.

Since some of the pins of the escape area may be distributed and scattered, individual triangles not containing pins appear in the delaunay triangulation area, and if the triangles are identified as the channel areas, the effect of wiring is affected. So there is also a need to address such situations.

The specific process of identifying the channel region and the escape region is as follows:

(1) Identifying whether pin distribution exists in each triangle, and classifying the triangles;

(2) Initial clustering is performed by merging triangles. The same type and adjacent triangles are aggregated together to form a collection of triangles of different types. Each sub-region is assigned a region number and a region type.

(3) The sub-region is updated. For the sub-region containing pin, the pin center coordinates are selected as representative points. The subregion without pin has the center of gravity as the region representative point. Judging whether the center of gravity of the pin-containing subarea exists or not within a range of a certain distance around the representative point of the pin-containing subarea, and if so, updating the type of the latter area into the pin-containing subarea.

In the present embodiment, the pin center coordinates in the sub-region including the pin are set as the region representative point candidate points, the region representative point is dynamically selected based on the determined adjacent sub-region, and the center coordinates of the pin nearest to the adjacent sub-region are generally set as the region representative point. The connection of the representative points of the merge area cannot cross the boundary of the wire area (crossing the boundary indicates that the two sub-areas are physically unconnected, i.e., cannot merge) and the distance of the representative points is less than the set value.

(4) The sub-regions are merged. And constructing a channel region and an escape region according to the result.

The pseudocode is shown in table 2.

Table 2 algorithm pseudo code table for identifying channel region and escape region

The result of the escape area and the channel area identification is shown in fig. 3. The blue blocks in fig. 3 (a) are pins, showing the soldered locations of the device in the FPC. Fig. 3 (b) clusters triangles, classifying the pins at both ends into two classes. Three dividing lines in the figure divide the wiring region into a channel region and an escape region.

3.2 Identification of triangular and connected regions within a channel region

A triangle is a polygonal area bounded by partial area boundaries. In a general channel area, a group of nets enters from one straight line side of a triangle and exits from the other straight line side, the number of the nets is not changed, and a section of common channel of the nets is represented, and only two sides of the net are normally used for entering and exiting the net. The triangle area is the area where the number of nets changes, and usually three sides have access to nets. The triangle area in the channel area is identified as follows:

(1) The channel region side chains are identified as non-contiguous side chains based on their discontinuities at the original boundaries.

(2) Triangles with three vertices on three different side chains are found and marked as triangles.

The result of the triangle area recognition in the channel area is shown in fig. 4, and the middle red area in the figure is the triangle area. The two graphs in fig. 4 are the recognition results of different FPCs.

FPC global routing

The goal of the overall routing is to provide guidelines for subsequent detailed routing, ensuring good routing paths and efficient operating speeds. The wiring boundary shape of the FPC via area is irregular, and thus a triangle as an overall wiring unit has a strong generalization ability. The overall wiring algorithm provided by the invention ensures that the network topologies cannot cross by dynamically adding and deleting nodes. Then, the net of each sub-region in the channel region and their passing point order on the region boundary are determined according to the ETP region identification model. Each wire net has a unique path, and the delaunay triangles traversed are determined so that the wire nets traversed in each triangle area can be derived.

3.1 Dynamic addition and deletion node setup

(1) T zone

The initial layout of the T-zone is shown in fig. 5 (a). The green line segment divides the triangle into four areas, the three peripheral areas represent the feasible paths of the wire net, and each side of the triangle can be accessed by the wire net. For example, a wire mesh enters Ac, exits Ab, another wire mesh enters Bc, and exits Ba.

When a path is newly added, in fig. 5 (b), two nodes (b, c) of a line segment having the same trend as the newly added path are first deleted. Then, four new nodes (d, e, f, g) are added at the middle points of the line segments at the two sides of (b, c), and green solid line edges (df, eg, ea, ga) are added to the overall wiring diagram without collision with the laid paths. The gray dashed edges (da, fa, fe, dg) collide with the laid out paths and do not add to the overall wiring diagram.

(2) P region

The areas on both sides of the green line segment represent the initial feasible paths of the net. Assuming that the initial net enters from the AB edge and exits from the AC edge, the BC edge is a boundary constraint edge, and no node is set. When the new line segment in fig. 5 (d) passes through the P region, two nodes b and c through which the original line segment passes are deleted first, and then four new nodes d, e, f and g are added at the middle points of the line segments on the two sides of b and c. The green solid line edge df, eg does not conflict with the laid out paths and is thus added to the overall wiring pattern. The gray dashed edges fe, dg conflict with the laid out paths and thus do not add to the overall wiring pattern. Thus, the areas enclosed by Adf, bceg and BCge can all be routed.

3.2 Algorithm flow

The overall wiring diagram of the present invention is denoted by G _Route (V, E), which is made up of the midpoints of the edges through which the wired network passes. The position coordinates of each point and the information of the side where each point is located are stored in V. E represents the Delaunay triangle to which the node belongs. Each net has only a unique path.

The initial wiring diagram G _Route is constructed with triangles in the delaunay triangle mesh as basic units. The initial node of the net is added to G _Route. Nodes and edges are gradually added to G _Route, net paths are searched in the graph based on breadth first algorithm (BFS), G _Route is updated, and the total capacity of the paths traversed by the nodes is recorded. And checking whether the bus fanout result meets the channel area capacity requirement.

The method comprises the following steps:

(1) Inputting an initial passing point on the escape line;

(2) Constructing an initial wiring diagram G _Route by taking a triangle as a basic unit, and recording the total capacity of the edge where the node is located;

(3) Searching net paths in the graph based on breadth first algorithm (BFS) and according to the step of dynamically adding and deleting nodes; (4) And checking whether the bus fanout result meets the channel area capacity requirement.

The pseudocode is shown in table 3.

TABLE 3 Overall routing algorithm pseudo-code Table

The overall routing result based on this algorithm is shown in fig. 6.

4. Completing subsequent wiring considering power integrity

Two kinds of Power lines are laid in the FPC, one kind is to lay metal lines with a certain area, the metal lines are irregular in Shape and variable in line width, the invention is called Power Shape (PS) Power line with variable line width, and the other kind is to set a wire net with constant line width. The latter can be regarded as a normal signal line, the former requiring special handling. In practical application, two conditions are to be satisfied when paving a variable linewidth wire net:

(1) The occupied area is wide, and the actual line width of each part on the line network path is larger than the lowest line width.

(2) Is usually arranged at the boundary of the FPC, so that interference to other wires is reduced.

If wiring resources are to be reserved for the power lines, it is first necessary to determine the boundary edge chain between the power supply and the adjacent P-region. Then, in the direction guide algorithm, the influence of the related side chain on the wiring path direction needs to be excluded. For example, in FIG. 7, assuming that the power lines are associated with side chains A-B-C, then N1 and N2 would be routed in the direction indicated by the dashed lines, as required by the minimum line width and line spacing. The rest of the wiring resources are reserved for the power line.

The part mainly comprises the steps of firstly setting a wire net with a constant wire width so as to reserve wiring resources for the power wires with variable wire widths.

Fig. 8 and 9 are two results from this algorithm. Therefore, the invention realizes FPC area identification and channel division for power supply integrity.

The invention also provides a PCB/FPC, which is manufactured by adopting the FPC area identification and wiring channel division method.

In summary, the invention provides a global wiring technology for FPC board area identification and channel area, which solves the problems of insufficient area division and unreasonable global wiring of the channel area in the traditional FPC wiring. Through accurate regional division and optimized wiring strategies, automatic processing of a wiring process and remarkable improvement of wiring quality are achieved. The technology can effectively optimize the wiring structure of the FPC board, reduce the intersection and the overlapping of wiring paths, and improve the performance and the reliability of the FPC circuit board. .

It should be noted that each step/component described in the present application may be split into more steps/components, or two or more steps/components or part of operations of the steps/components may be combined into new steps/components, according to the implementation needs, to achieve the object of the present application.

It will be readily appreciated by those skilled in the art that the foregoing is merely a preferred embodiment of the invention and is not intended to limit the invention, but any modifications, equivalents, improvements or alternatives falling within the spirit and principles of the invention are intended to be included within the scope of the invention.

Claims

1. A method for identifying FPC areas and dividing wiring channels, characterized in that the method comprises:

Triangulate the FPC routing area;

Construct an ETP area division model, and divide the FPC wiring area into the escape area E area, the triangle area T area, and the connection area P area based on the triangles obtained by triangulation, including:

Divide the escape area and the passage area, including:

Establish a mapping relationship between pins and triangles to identify whether there are pins distributed in each triangle, and then divide the triangles into two categories;

Initial clustering is performed by merging triangles: adjacent triangles of the same type are aggregated together to form a set of triangles of different types, thereby obtaining multiple sub-regions, and assigning a region type to each sub-region; the region types are divided into sub-regions with pins and sub-regions without pins;

Update sub-regions: determine the representative points of the sub-regions containing pins and the representative points of the sub-regions without pins, and determine whether there are representative points of the sub-regions without pins within a certain distance around the representative points of the sub-regions containing pins; if there are, and the connection line between the representative points is within the wiring area, then update the latter area type to the sub-region containing pins;

Merge sub-regions to construct escape regions and channel regions: merge adjacent sub-regions of the same type. The sub-regions containing pins are escape regions, and the remaining sub-regions without pins are channel regions.

The channel area is divided into a triangular area and a connection area, wherein the triangular area is a triangle with wired networks entering and exiting on three sides, and the connection area is a triangle with wired networks entering and exiting on two sides;

Perform global routing in the channel area.

2. The FPC area identification and wiring channel division method according to claim 1 is characterized in that triangulating the FPC wiring area comprises:

Use the distance threshold T to encrypt the boundary point set of the FPC wiring area;

Based on the encrypted point set, create the Delaunay triangulation network;

Determine the centroid of each triangle and select the triangles whose centroid is within the FPC wiring area;

Construct a triangulation graph _GCDT (V,E), where V represents a triangle and E represents the adjacency relationship of a triangle.

3. The FPC area identification and wiring channel division method according to claim 1, characterized in that determining the representative points of the sub-areas containing pins and the representative points of the sub-areas without pins comprises:

For a sub-region containing pins, all its pins are set as candidate representative points. When determining whether there is a representative point of a sub-region without pins within a certain distance around the representative point of the sub-region containing pins, the candidate representative point closest to the sub-region without pins is used as the representative point.

For a sub-region without pins, its centroid is taken as the representative point.

4. The FPC area identification and wiring channel division method according to claim 1 is characterized in that the channel area is divided into a triangle area and a connection area, comprising:

According to the discontinuity of the channel zone edge chain on the original boundary, it is identified as multiple unconnected edge chains;

Find the triangle whose three vertices are on three different edge chains, which is the triangular area, and the remaining triangles in the channel area are the connection area.

5. The method for FPC area identification and wiring channel division according to claim 1, characterized in that performing global wiring in the channel area comprises:

Get the initial passing point on the escape line; the escape line is the dividing line between the escape area and the channel area, the initial passing point is the point where the wire net passes on the escape line, and the wire net connects the pins in the two escape areas;

Using triangle as the basic unit, construct the initial wiring diagram G _Route , and add the initial nodes of the wire network into the wiring diagram G _Route ;

Based on the breadth-first algorithm BFS and the method of dynamically adding and deleting nodes, the wire network path is searched in the wiring diagram, the wiring diagram G _Route is updated and the total capacity of the path passed by the node is recorded;

Check whether the bus fan-out result meets the channel area capacity requirement; if so, complete the routing.

6. The FPC area identification and wiring channel division method according to claim 5, characterized in that the wiring diagram is represented by G _Route (V, E), V is composed of the points on the edge through which the wired network passes, V stores the position coordinates of each point and the information of the edge on which it is located, and E indicates that the nodes belong to the same Delaunay triangle;

Determine the line network of each sub-area in the channel area and the order of its passing points on the area boundary; since each set of line networks has only a unique path, the triangles passed through are certain, thus obtaining the line network passing through each triangular area.

7. The FPC area identification and wiring channel division method according to claim 5 is characterized in that the method of dynamically adding and deleting nodes is used to ensure that the line network topology does not cross, and the method of dynamically adding and deleting nodes is as follows:

For the triangle area T, the initial wiring diagram is divided into four areas by the lines connecting the nodes on the three sides of the triangle; when a new path is added, delete the two nodes of the line with the same direction as the new path, and add a new node at the midpoint of the line segments on both sides of the deleted node. If the node connection line does not conflict with the routed path, it will be added to the overall wiring diagram. If the node connection line conflicts with the routed path, it will not be added to the overall wiring diagram; the area divided by the node connection line is the wire mesh path;

For the connection area P, the initial wiring diagram is divided into two areas by the lines connecting the nodes on the two sides of the triangle. The sides of the triangle located in the edge chain are boundary constraint edges and no nodes are set. When a new path is added, the two nodes of a line are deleted, and a new node is added at the midpoint of the line segments on both sides of the deleted node. If the node connection line does not conflict with the routed path, it is added to the overall wiring diagram. If the node connection line conflicts with the routed path, it is not added to the overall wiring diagram. The area divided by the node connection line is the wire network path.

8. The FPC area identification and wiring channel division method according to claim 1, characterized in that the method further comprises:

Consider power integrity and improve routing results, including:

The power lines are divided into variable line width power lines and constant line width line networks;

First, the edge chains associated with the variable line width power lines are determined;

Route the wire nets with constant line width along the other side chain according to the minimum line width and line spacing, and reserve the remaining routing resources for variable line width power lines.

9. The FPC area identification and wiring channel division method according to claim 8 is characterized in that laying variable line width power lines must meet the following two conditions:

(1) The area occupied is large, and the actual line width at each point on the line network path is greater than the preset minimum line width;

(2) Set it at the edge of the FPC to reduce interference with other wire networks.

10. A PCB/FPC, characterized in that the PCB/FPC is manufactured by using the FPC area identification and wiring channel division method according to any one of claims 1 to 9.