CN118943166A

CN118943166A - Common drain MOSFET device and preparation method, electronic device and preparation method

Info

Publication number: CN118943166A
Application number: CN202411015050.7A
Authority: CN
Inventors: 杨旭刚; 田月姣
Original assignee: Shenzhen Chuangfei Xinyuan Semiconductor Co ltd
Current assignee: Shenzhen Chuangfei Xinyuan Semiconductor Co ltd
Priority date: 2024-07-26
Filing date: 2024-07-26
Publication date: 2024-11-12

Abstract

The present application provides a common-drain MOSFET device and a preparation method, an electronic device and a preparation method. The common-drain MOSFET device comprises: a substrate layer having a first conductivity type; an epitaxial layer, the epitaxial layer is grown on a first surface of the substrate layer and has the first conductivity type; a groove is formed on a second surface of the substrate layer; a metal layer is deposited on a side wall of the groove; a passivation layer is filled in the groove, thereby solving the technical problem of large resistance in the current path of the common-drain MOSFET device in the prior art.

Description

Common-drain MOSFET device, manufacturing method, electronic equipment and manufacturing method

Technical Field

The application relates to the technical field of semiconductors, in particular to a common-drain MOSFET device, a manufacturing method, electronic equipment and a manufacturing method.

Background

A common-drain MOSFET (Metal-Oxide-semiconductor field-Effect Transistor, metal-Oxide-semiconductor field effect transistor) is a bi-directional switch design, whose core feature is that two independent MOSFETs (labeled M1 and M2) are integrated on the same silicon substrate, enabling efficient bi-directional current control. The unique construction mode not only improves the space utilization rate, but also optimizes the switching performance and reduces the parasitic effect, thereby showing remarkable advantages in the fields of power management, signal processing and the like. The current path of the common drain MOSFET device can greatly affect its performance.

Accordingly, there is a need for a common drain MOSFET device with low current path resistance and a method of making the same.

Disclosure of Invention

The application provides a common-drain MOSFET device, a preparation method, electronic equipment and a preparation method, which solve the technical problem of large resistance in a current path of the common-drain MOSFET device in the prior art.

To achieve the above object, in a first aspect, an embodiment of the present application provides a common drain MOSFET device, including: a substrate layer having a first conductivity type; an epitaxial layer grown on a first surface of the substrate layer and having the first conductivity type; a trench formed on a second surface of the substrate layer; a metal layer deposited on the side wall of the trench; a passivation layer; filling in the trench.

Optionally, the common drain MOSFET device comprises at least two MOSFET devices and drains of the at least two MOSFET devices are connected through the substrate.

Optionally, the thickness of the metal layer is smaller than the width of the trench.

Optionally, the shape of the trench is parallel to the current path between the at least two drain MOSFET devices.

Optionally, the common drain MOSFET device has a thickness of 50 μm to 100 μm.

In a second aspect, an embodiment of the present application provides a method for preparing a common drain MOSFET device according to any one of the first aspect, where the method for preparing a common drain MOSFET device includes: growing an epitaxial layer on a first surface of a substrate layer; etching to form a groove on the second surface of the substrate layer; depositing a metal layer on the side wall of the groove; and filling a passivation layer in the groove.

Optionally, etching to form a trench on the second surface of the substrate layer includes: depositing a hard mask and a photoresist on a second surface of the substrate layer; etching the hard mask and the photoresist to form a pattern parallel to the current path of the common drain MOSFET device; removing the photoresist; etching the substrate layer to form a groove; and removing the hard mask.

Optionally, depositing a metal layer on the sidewall of the trench includes: the thickness of the metal layer deposited on the side wall of the groove is smaller than the width of the groove.

In a third aspect, an embodiment of the present application provides an electronic device, including a common drain MOSFET device according to any one of the first aspects.

In a fourth aspect, an embodiment of the present application provides a method for manufacturing an electronic device, where the method for manufacturing an electronic device includes the method for manufacturing a common drain MOSFET according to any one of the second aspects.

The application provides a common drain MOSFET device, which comprises: a substrate layer having a first conductivity type; an epitaxial layer grown on a first surface of the substrate layer and having the first conductivity type; a trench formed on a second surface of the substrate layer; a metal layer deposited on the side wall of the trench; a passivation layer; the trench is filled, so that the technical problem of high resistance in a current path of the common-drain MOSFET device in the prior art is solved.

Drawings

Fig. 1 is a schematic diagram of a common drain MOSFET device in an embodiment of the invention;

Fig. 2 shows a schematic diagram of a common drain MOSFET device in an embodiment of the invention;

FIG. 3 shows a schematic diagram of the current path of a common drain MOSFET device in an embodiment of the present invention;

fig. 4 is a schematic diagram of a common-drain MOSFET device according to an embodiment of the invention;

Fig. 5 is a schematic flow chart of a method for manufacturing a common-drain MOSFET device according to an embodiment of the present invention;

FIG. 6 shows a schematic diagram of an epitaxial layer grown in an embodiment of the invention;

FIG. 7 illustrates a schematic diagram of depositing a hard mask and photoresist on a second surface of a device in an embodiment of the invention;

FIG. 8 is a schematic diagram of a hard mask and photoresist etch pattern in an embodiment of the invention;

FIG. 9 is a schematic diagram of photoresist removal in an embodiment of the invention;

FIG. 10 is a schematic diagram of etching a trench in an embodiment of the invention;

FIG. 11 illustrates a schematic view of a hard mask removed in an embodiment of the invention;

FIG. 12 shows a schematic diagram of depositing a metal layer in a trench in an embodiment of the invention;

Fig. 13 is a schematic view of filling a passivation layer in a trench in an embodiment of the present invention;

Fig. 14 shows a schematic view of the shape and direction of the grooves in an embodiment of the present invention.

Detailed Description

In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, techniques, etc., in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known MOSFET device functional area specific structures, and the operating principles of MOSFETs are omitted so as not to obscure the description of the present application with unnecessary detail.

The terminology used in the following examples is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the specification of the present application and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include, for example, "one or more" such forms of expression, unless the context clearly indicates to the contrary.

Fig. 1 shows a schematic diagram of a common drain MOSFET device in an embodiment of the invention. As shown in fig. 1, the common drain MOSFET is presented as an integrated assembly comprising four electrical terminals including: g1 (gate 1), S1 (source 1), G2 (gate 2), S2 (source 2), which together define the on-state of the device. Specifically, the mechanism of operation of this structure follows the logic that when no forward voltage is applied between G1-S1, the channel through which current flows from S2 to S1 is in the off state; similarly, if there is no forward voltage between G2 and S2, current cannot flow from S1 to S2; and when a forward voltage is applied across both G1-S1 and G2-S2, the connection between S1 and S2 becomes conductive.

It should be noted that M1 and M2 are located on the same chip, and the drains of M1 and M2 are connected through the substrate layer, see fig. 2. Fig. 2 shows a schematic diagram of a common drain MOSFET device in an embodiment of the invention. As shown in fig. 2, the two MOSFET devices M1 and M2 are closely arranged on the same chip and their drains (Drain) are connected by a shared substrate region, forming a common Drain configuration. On the front side (first surface) of the substrate region are the functional regions of M1 and M2, wherein the functional regions of M1 and M2 are isolated by an isolation region. The functional regions include, but are not limited to, epitaxial layers and conductor regions formed in the epitaxial layers.

It should be further noted that in the embodiment of the present application, the common drain of two MOSFET devices is schematically illustrated, but the number of MOSFET devices of the common drain may be greater than two, and the number of MOSFET devices of the common drain is not particularly limited in the embodiment of the present application.

Preferably, the embodiment of the present application also provides a schematic diagram of a current path of the common drain MOSFET device, see fig. 3. Fig. 3 shows a schematic diagram of the current path of a common drain MOSFET device in an embodiment of the application. As shown in fig. 3, the common drain MOSFET device is current-carrying from S1 to S2 in the on-state. This current path exhibits a unique "U" shape, meaning that the current flows first downward in a vertical direction, then turns horizontally to the right, and finally flows back again vertically upward, forming a closed trajectory. It should be noted that, the "U" path is completely embedded in the semiconductor substrate material with relatively high resistance, and the resistance is significantly increased compared to the metal wire. Since the inherent resistance of the semiconductor substrate is much higher than that of the metal wire, the current in the "U" shaped path encounters a large resistance, which results in a significant increase in the equivalent series resistance between S1 and S2. In fact, under certain design conditions, the resistance of the "U" shaped path can account for up to 40% of the total resistance of the entire device, which is a critical factor affecting the performance of the common drain MOSFET device in high frequency applications and high power operating scenarios. The common drain MOSFET device is in an on state with current flowing from the source of one MOSFET device to the source of the other MOSFET device. This current path exhibits a unique "U" shape, meaning that the current flows first downward in a vertical direction, then turns horizontally to the right, and finally flows back again vertically upward, forming a closed trajectory.

The related art can significantly reduce the resistivity thereof by increasing the doping concentration of the substrate material, thereby reducing the substrate resistance. The substrate thickness can be controlled below 100 micrometers, thereby greatly reducing the substrate resistance. Although the method can effectively reduce the substrate resistance, new technical problems and cost burden are introduced at the same time; for example, the complexity of epitaxial growth techniques and backside processes: the requirement of high concentration doping and ultra-thin substrates exacerbates the difficulty of epitaxial growth and increases the complexity of backside processing, which not only increases manufacturing costs, but may also reduce device yield.

Therefore, the common drain MOSFET device provided by the embodiment of the application includes: a substrate layer having a first conductivity type; an epitaxial layer grown on a first surface of the substrate layer and having the first conductivity type; a trench formed on a second surface of the substrate layer; a metal layer deposited on the side wall of the trench; a passivation layer; the trench is filled, so that the technical problem of high resistance in a current path of the common-drain MOSFET device in the prior art is solved.

Fig. 4 is a schematic structural diagram of a common drain MOSFET device according to an embodiment of the present invention, as shown in fig. 4, including: a substrate layer 401, the substrate layer 401 having a first conductivity type; an epitaxial layer 402 grown on the first surface of the substrate layer, the epitaxial layer also having a first conductivity type; a trench 403, the trench 403 being on a second surface of the substrate layer; a metal layer 404 deposited on the sidewalls of the trench and a passivation layer 405 filled in the trench 403.

Note that the common-drain MOSFET device shown in fig. 4 includes at least two MOSFET devices whose drains are connected through the substrate 401. The width of trench 403 is approximately 10 μm to 20 μm and the thickness of the deposited metal layer on the sidewalls of the trench is 3 μm to 7 μm. That is, the thickness of the metal layer is smaller than the width of the trench, i.e., the metal layer does not fill the trench. And filling the gap part of the groove with a passivation layer after the metal layer is deposited. The material of the passivation layer may be PSG (phosphosilicate glass) and/or SRO (silicon rich oxide). The primary aim of filling the passivation layer is to strengthen the physical protection of the back surface of the chip, resist the potential damage of external mechanical force and ensure that the device can still maintain stable performance under severe environment. Secondly, the existence of the filling passivation layer solves the problem of structural stability caused by the difference of thermal expansion coefficients of different materials. In particular, in metal-filled device structures, significant differences in the coefficients of thermal expansion between the metal and semiconductor materials can be a challenge if the metal layer is completely filled inside the chip. When subjected to temperature cycling, this difference can lead to compressive stresses at the metal-semiconductor interface, which in turn can induce mechanical damage that threatens the integrity and functionality of the device.

The introduction of the filled passivation layer effectively acts as a stress buffer by virtue of its inherent flexibility and elastic properties. In the temperature fluctuation process, the passivation layer can absorb and disperse the internal stress caused by thermal expansion and cold contraction, and obviously lighten the stress concentration at the interface of the metal and the semiconductor, thereby greatly improving the overall reliability and the service life of the device.

It should be further noted that after the process of completing the device function region in 402 according to the related art, the chip is thinned to between 50-100um, and then etched into a trench parallel to the current "U" shaped path shown in fig. 3, that is, the shape of the trench is parallel to the current path between two MOSFETs of the common drain MOSFET device, and the depth of the trench is close to the function region of the common drain MOSFET device.

In another aspect, the present invention provides a method of making a common drain MOSFET device. Referring to fig. 5, fig. 5 is a schematic flow chart showing a method for manufacturing a common drain MOSFET device according to an embodiment of the present invention, where the method includes the following steps:

s501: an epitaxial layer is grown on the first surface of the substrate layer.

Specifically, fig. 6 shows a schematic diagram of an epitaxial layer grown in an embodiment of the present invention. As shown in fig. 6, an epitaxial layer 402 is grown on a semiconductor substrate layer 401, in which the functional regions of the semiconductor are located, the substrate layer 401 being of a first conductivity type, the epitaxial layer 402 also being of the first conductivity type.

S502: and etching a groove on the second surface of the substrate layer.

Specifically, a hard mask 701 and a photoresist 702 are first deposited on the second surface of the substrate layer 401, see fig. 7. FIG. 7 illustrates a schematic diagram of depositing a hard mask and photoresist on a second surface of a device in an embodiment of the invention. The deposition hard mask is intended to protect the chip from damage during subsequent processing. Hard mask materials, such as silicon dioxide (SiO 2) or silicon nitride (Si 3N 4), are selected for their excellent chemical stability and high resistance to etching processes. By depositing a hard mask on the second surface of the chip, unnecessary etching reactions can be effectively shielded, ensuring the integrity and function of critical structures.

Photoresist is a photopolymer material used to pattern the microstructures. In the semiconductor manufacturing process, photoresist is uniformly coated on the surface of a chip, and after precise exposure by a photolithography machine, chemical reaction changes occur, thereby forming a predetermined pattern. This patterning process is the template for the subsequent etching step, which determines the microstructure of the final device. The selection and use of the photoresist should take into account its resolution, contrast, stability and photospeed to ensure the accuracy and consistency of pattern transfer.

The hard mask and photoresist are then etched to form a pattern 801 parallel to the current path of the common drain MOSFET device, see fig. 8. FIG. 8 is a schematic diagram of a hard mask and photoresist etch pattern in an embodiment of the invention. First, a photoresist is uniformly coated over a hard mask as a temporary mask layer. The pattern matching the preset design can be formed by photolithographic techniques, i.e., exposing the photoresist-coated areas with a light source, followed by development. The open portions in these patterns will act as windows for subsequent etching processes, allowing the etchant to selectively remove underlying hard mask or substrate material while the unexposed photoresist areas remain intact, continuing to play a protective role.

Once the photoresist patterning is complete, the next step is to etch the hard mask. Hard masks, typically made of a more etch resistant material such as silicon dioxide or silicon nitride, act as a more durable mask during etching, and are capable of withstanding higher strength etching conditions, thereby ensuring accurate transfer of the pattern to the underlying semiconductor material.

As shown in fig. 8, the trenches are etched out in parallel with the current "U" shaped path shown in fig. 3, that is, the shape of the trenches is parallel with the current path between at least two MOSFETs of the common drain MOSFET device.

Next, the photoresist is removed, see fig. 9. FIG. 9 is a schematic diagram of photoresist removal in an embodiment of the invention. Photoresist removal typically involves the use of chemical solvents or plasma etching techniques, depending on the requirements of the process and the type of photoresist. Chemical solvents such as acetone, isopropyl alcohol or special photoresist removers can dissolve the remaining photoresist, making it easy to clean. And the plasma etching utilizes the energy of the plasma to decompose photoresist molecules, so that the photoresist molecules are converted into gas or small molecules which are easier to clean.

Photoresist removal is an important element in the lithography process chain, which not only removes nonfunctional material, but also ensures the accuracy and efficiency of subsequent processes. By thoroughly removing the photoresist, disturbances of subsequent process steps, such as adhesion problems during metal deposition or selective deviations during etching, by residues can be avoided, thus ensuring high quality and reliability of integrated circuits and other microelectronic devices.

The substrate layer is then etched to form trenches, see fig. 10. Fig. 10 shows a schematic diagram of etching a trench in an embodiment of the invention. As shown in fig. 10, a trench 403 is etched into the second surface of the substrate layer. The trench is shaped in parallel with a current path between at least two MOSFETs of the common drain MOSFET device. The substrate layer is typically composed of various semiconductor or insulating materials, such as silicon, silicon dioxide, silicon nitride, etc., which play an important role in supporting, insulating, or conducting electricity in the device. During etching, a mask pattern is first formed on the substrate by photolithographic techniques, the mask will determine which areas of material will remain and which areas will be removed. Subsequently, the portions not covered by the mask are selectively removed using dry etching or wet etching techniques to form the desired trench or recess structure. The etching process is selected as needed to ensure that the depth, width and shape of the trench meet the design specifications. Dry etching, such as Reactive Ion Etching (RIE), can form high aspect ratio trenches in the substrate layer by chemical reaction with the aid of plasma, and is suitable for high precision structures. Wet etching, in turn, utilizes chemical solutions to dissolve the substrate material, typically for applications requiring less precise or large area etching.

The hard mask is then removed, see fig. 11. FIG. 11 illustrates a schematic view of a hard mask removed in an embodiment of the invention. Once the hard mask has completed its task of protecting the underlying structure from damage during etching, it is safely removed in the next step to expose the underlying material ready for subsequent deposition, doping or other process steps. The removal of the hard mask can be performed by chemical wet etching, dry plasma etching, laser lift-off or the like, depending on the material of the hard mask and the requirements of subsequent processes.

S503: and depositing a metal layer on the side wall of the groove.

In particular, see fig. 12. Fig. 12 shows a schematic diagram of depositing a metal layer in a trench in an embodiment of the invention. A metal layer 404 is deposited on the sidewalls of the trench 403 as shown in fig. 12. The width of trench 403 is approximately 10 μm to 20 μm and the thickness of the deposited metal layer on the sidewalls of the trench is 3 μm to 7 μm. That is, the thickness of the metal layer is smaller than the width of the trench, i.e., the metal layer does not fill the trench. First, a metal thin film is uniformly deposited on the sidewalls of the trench by Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), or the like. The choice of metal includes, but is not limited to, aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), or an alloy combination thereof. These metals are widely used for their excellent conductivity, stability and good compatibility with semiconductor materials.

Alternatively, after deposition is completed, the next step is to remove excess metal from the bottom and outer surfaces of the trench, a process known as via etching or contact hole etching. This operation is typically performed by dry etching techniques such as Reactive Ion Etching (RIE) or wet etching, depending on the metal species and etching requirements. The goal of the etch is to ensure that the metal remains only inside the trench, forming a continuous conductive path, while the trench bottom and surrounding areas remain free of metal, facilitating subsequent insulating layer deposition or other process steps.

It should be noted that, in the embodiment of the present application, whether the deposited metal layer is free of the excess metal on the bottom and the outer surface of the trench is not particularly limited, that is, the excess metal on the bottom and the outer surface of the trench may be removed, and the excess metal on the bottom and the outer surface of the trench may be also retained.

S504: and filling a passivation layer in the groove.

Specifically, the void portion of the trench is filled with a passivation layer, see fig. 13. Fig. 13 shows a schematic diagram of filling a passivation layer in a trench in an embodiment of the present invention. The material of the passivation layer may be PSG (phosphosilicate glass) and/or SRO (silicon rich oxide). The primary aim of filling the passivation layer is to strengthen the physical protection of the back surface of the chip, resist the potential damage of external mechanical force and ensure that the device can still maintain stable performance under severe environment. Secondly, the existence of the filling passivation layer solves the problem of structural stability caused by the difference of thermal expansion coefficients of different materials. In particular, in metal-filled device structures, significant differences in the coefficients of thermal expansion between the metal and semiconductor materials can be a challenge if the metal layer is completely filled inside the chip. When subjected to temperature cycling, this difference can lead to compressive stresses at the metal-semiconductor interface, which in turn can induce mechanical damage that threatens the integrity and functionality of the device.

In summary, the common-drain MOSFET device does not need to be packaged conventionally, and thus can be incorporated into various portable electronic devices and energy management systems in a compact form, thereby realizing efficient and stable power conversion and control in a limited space. The common drain MOSFET device provided by the embodiment of the application can obviously reduce the on-resistance. The on-resistance of the common drain MOSFET device provided by the embodiment of the application can be reduced by about 30%.

Preferably, for further explanation of the shape and orientation of the grooves in the embodiments of the present application, see fig. 14. Fig. 14 shows a schematic view of the shape and direction of the grooves in an embodiment of the present application. The direction of the groove (trench) is from M1 to M2 as shown in fig. 14, and the shape is a bar. That is to say the trenches are parallel to the current paths of M1 to M2.

In another aspect, the present invention provides an electronic device comprising a common drain MOSFET device as described above.

In another aspect, the present invention provides a method for manufacturing an electronic device, including the method for manufacturing a common drain MOSFET device described above.

In summary, an embodiment of the present application provides a common drain MOSFET device, including: a substrate layer having a first conductivity type; an epitaxial layer grown on a first surface of the substrate layer and having the first conductivity type; a trench formed on a second surface of the substrate layer; a metal layer deposited on the side wall of the trench; a passivation layer; the trench is filled, so that the technical problem of high resistance in a current path of the common-drain MOSFET device in the prior art is solved.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus/device and method may be implemented in other manners. For example, the apparatus/device embodiments described above are merely illustrative, e.g., the division of the modules or units is merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection via interfaces, devices or units, which may be in electrical, mechanical or other forms.

It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It should also be understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.

As used in the present description and the appended claims, the term "if" may be interpreted as "when..once" or "in response to a determination" or "in response to detection" depending on the context. Similarly, the phrase "if a determination" or "if a [ described condition or event ] is detected" may be interpreted in the context of meaning "upon determination" or "in response to determination" or "upon detection of a [ described condition or event ]" or "in response to detection of a [ described condition or event ]".

Furthermore, the terms "first," "second," "third," and the like in the description of the present specification and in the appended claims, are used for distinguishing between descriptions and not necessarily for indicating or implying a relative importance.

Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.

Claims

1. A common drain MOSFET device, comprising:

A substrate layer having a first conductivity type;

an epitaxial layer, the epitaxial layer being grown on the first surface of the substrate layer and having the first conductivity type;

A groove formed on the second surface of the substrate layer;

a metal layer deposited on the sidewalls of the trench;

A passivation layer is filled in the trench.

2 . The common-drain MOSFET device according to claim 1 , wherein the common-drain MOSFET device comprises at least two MOSFET devices and drains of the at least two MOSFET devices are connected through the substrate.

3 . The common-drain MOSFET device according to claim 1 , wherein a thickness of the metal layer is smaller than a width of the trench.

4 . The common-drain MOSFET device according to claim 2 , wherein a shape of the trench is parallel to a current path between the at least two drain MOSFET devices.

5 . The common-drain MOSFET device according to claim 1 , wherein a thickness of the common-drain MOSFET device is 50 μm-100 μm.

6. A method for preparing a common-drain MOSFET device, for preparing the common-drain MOSFET device according to any one of claims 1 to 5, characterized in that it comprises:

growing an epitaxial layer on a first surface of the substrate layer;

Etching a groove on the second surface of the substrate layer;

depositing a metal layer on the sidewalls of the trench;

A passivation layer is filled in the trench.

7. The method for preparing a common-drain MOSFET device according to claim 6, characterized in that:

Etching a groove on the second surface of the substrate layer comprises:

depositing a hard mask and a photoresist on the second surface of the substrate layer;

Etching the hard mask and the photoresist to form a pattern parallel to the current path of the common-drain MOSFET device;

Removing photoresist;

Etching the substrate layer to form a groove;

The hard mask is removed.

8. The method for preparing a common-drain MOSFET device according to claim 6, characterized in that:

The step of depositing a metal layer on the sidewall of the trench comprises: a thickness of the metal layer deposited on the sidewall of the trench is smaller than a width of the trench.

9. An electronic device comprising the common-drain MOSFET device according to any one of claims 1 to 5.

10. A method for preparing an electronic device, comprising the method for preparing the common-drain MOSFET device according to any one of claims 6 to 8.