CN118939230A - FIFO memory read and write processing circuit and chip - Google Patents
FIFO memory read and write processing circuit and chip Download PDFInfo
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Abstract
本发明公开了一种涉及集成电路技术领域的FIFO存储器读写处理电路和芯片，所述FIFO存储器读写处理电路包括：写操作控制模块、读操作控制模块、可配置模块、空满状态判断模块和双端口存取的FIFO存储器，其中，写操作控制模块用于控制通信模块的写接口的工作，读操作控制模块用于控制通信模块的读接口的工作，可配置模块用于配置时钟同步和分配每个通信模块在FIFO存储器中的地址范围，空满状态判断模块用于判断通信模块的存储空间的空满状态，双端口存取的FIFO存储器支持不同通信模块的读写操作。采用该FIFO存储器读写处理电路能够动态配置通信模块所使用的FIFO存储器的大小，提高FIFO存储器的存储资源利用率，并且还能支持不同时钟域的通信模块的读写操作。
The present invention discloses a FIFO memory read-write processing circuit and chip related to the field of integrated circuit technology, wherein the FIFO memory read-write processing circuit comprises: a write operation control module, a read operation control module, a configurable module, an empty and full state judgment module and a dual-port access FIFO memory, wherein the write operation control module is used to control the operation of the write interface of the communication module, the read operation control module is used to control the operation of the read interface of the communication module, the configurable module is used to configure clock synchronization and allocate the address range of each communication module in the FIFO memory, the empty and full state judgment module is used to judge the empty and full state of the storage space of the communication module, and the dual-port access FIFO memory supports the read and write operations of different communication modules. The FIFO memory read-write processing circuit can dynamically configure the size of the FIFO memory used by the communication module, improve the storage resource utilization of the FIFO memory, and can also support the read and write operations of communication modules in different clock domains.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a read-write processing circuit and a chip of a FIFO memory.
Background
In the related art, in the field of application of industrial control and automotive micro control units (MCUs, microcontroller Unit), various types and a considerable number of communication modules are generally involved. For example, in an automobile gateway control MCU, the controller area network bus (CAN, controller Area Network) controller may be up to 20 paths, the local connection network (LIN, local Interconnect Network) bus controller may be up to 10 paths, and other communication modules may be involved in a considerable number, including serial peripheral interfaces (SPI, serial Peripheral Interface), serial bus interfaces (I2C, inter-INTEGRATED CIRCUIT), serial audio interfaces (I2S, inter-IC Sound), secure and efficient serial interfaces (SENT, single Edge Nibble Transmission), and the like. To improve the communication efficiency, the communication module generally employs a first-in first-out memory (FIFO memory) to buffer data transmitted and received. The FIFO is used in the communication module, so that the data transmission rate can be effectively increased, a large amount of data can be buffered, the burden of the CPU can be lightened, and the system performance can be improved. In different application scenarios, the FIFO requirements of each communication module are different, and each communication module in the chip design is provided with its own FIFO memory, so that the utilization rate of the FIFO memory is reduced, for example, a module with a larger data buffering amount cannot meet the requirements of the system on FIFO buffer memory, and a module with a smaller data buffering amount is empty of its own FIFO memory for a long time, so that resource waste is caused.
Disclosure of Invention
In view of the above, it is desirable to provide a FIFO memory read/write processing circuit capable of improving the FIFO memory resource utilization.
A FIFO memory read-write processing circuit, the FIFO memory read-write processing circuit comprising: the system comprises a write operation control module, a read operation control module, a configurable module, a full empty state judgment module and a dual-port accessed FIFO memory; the write operation control module and the read operation control module are respectively connected with the configurable module, the empty and full state judging module and the FIFO memory;
The configurable module comprises a synchronous definition unit and a reassignment unit; the synchronous definition unit is used for managing clock synchronization of a write interface and a read interface of the communication module in different clock domains; the reassignment unit is used for storing the address range which is distributed for each communication module and is positioned in the FIFO memory;
The write operation control module is connected with a write interface of the communication module and consists of a write interface synchronous logic unit and a write operation judgment gating unit which are connected with each other; the write interface synchronization logic unit is used for executing write operation synchronization of the write interface according to the clock synchronization determined by the synchronization definition unit; the write operation judging and gating unit is used for determining the write authority of the write interface and gating a write interface passage corresponding to the write interface with the write authority;
The read operation control module is connected with a read interface of the communication module and consists of a read interface synchronous logic unit and a read operation judgment gating unit which are connected with each other; the read interface synchronization logic unit is used for executing read operation synchronization of the read interface according to the clock synchronization determined by the synchronization definition unit; the write operation judging and gating unit is used for determining the read authority of the read interface and gating a read interface passage corresponding to the read interface with the read authority;
The empty-full state judging module is connected with the configurable module and is used for outputting full identification according to the address range of the communication module and the write pointer and the read pointer of the communication module with write permission and outputting empty identification according to the address range of the communication module and the read pointer and the write pointer of the communication module with read permission;
the FIFO memory is a memory space shared by a plurality of communication modules, is used for storing data written by a write interface with write permission in an address range allocated by the communication module with write permission, and is used for reading data read by a read interface with read permission in the address range allocated by the communication module with read permission.
A chip includes a FIFO memory read-write processing circuit.
The FIFO memory read-write processing circuit comprises a write operation control module, a read operation control module, a configurable module, a full empty state judging module and a dual-port stored FIFO memory, so that the reconstruction and allocation of the FIFO resources of each communication module are realized, the available FIFO size of each communication module can be configured in real time, a plurality of communication modules can share the FIFO space, the shared FIFO space is subjected to read-write operation, and the utilization rate of the FIFO storage resources is effectively improved.
Drawings
FIG. 1 is a schematic diagram of a read/write processing circuit of a FIFO memory according to an embodiment;
FIG. 2 is a schematic diagram showing an internal structure of a write operation judging gate unit in one embodiment;
FIG. 3 is a schematic diagram showing an internal structure of a read operation judging strobe unit in one embodiment;
fig. 4 is a schematic diagram illustrating an internal structure of the hollow full state determining module according to an embodiment.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
Implementation details of the technical scheme of the embodiment of the present application are described in detail below.
In one embodiment, as shown in fig. 1, fig. 1 shows a schematic diagram of a FIFO memory read-write processing circuit. As shown in FIG. 1, the read-write processing circuit of the FIFO memory mainly comprises a write operation control module, a read operation control module, a configurable module, an empty-full state judging module and the FIFO memory, wherein the write operation control module and the read operation control module are respectively connected with the empty-full state judging module of the configuration module and the FIFO memory.
The following describes each constituent element of the FIFO memory read-write processing circuit in detail.
The FIFO memory read-write processing circuit is provided with a block of FIFO memory with larger size, the FIFO memory is a memory space shared by a plurality of communication modules, and the plurality of communication modules share the FIFO memory. The FIFO memory is configured with two ports, having two independent interfaces, one for writing data (write port) and one for reading data (read port), which are capable of operating simultaneously, even at the same time, for reading and writing. Due to the dual port characteristic of the FIFO memory, parallel data input and output can be realized, data delay is reduced, and throughput of the system is improved. In practice, the FIFO memory may be implemented using dual port RAM.
The configurable module can configure FIFO space and read-write clock of each communication module according to specific requirements or application scenarios. Referring to fig. 1, the configurable module is composed of a synchronization definition unit and a reassignment unit.
In a multi-module system, different communication modules may operate in different clock domains, which requires synchronous control of the read-write interfaces of the communication modules, where a synchronous definition unit plays a vital role. The synchronization definition unit is used for managing clock synchronization of the write interface and the read interface of the communication module in different clock domains, and determining whether to enable clock synchronization according to the relationship of the clock domains by identifying the clock domains used by the write interface and the read interface of each communication module, so that the consistency of data and the correctness of time sequence are ensured, different clock requirements of a plurality of communication modules can be matched, and the read-write requirements of the plurality of communication modules are met.
In this embodiment, the synchronization definition unit can ensure that the same FIFO memory can be effectively used by the communication modules of a plurality of different clock domains by reasonably defining and coordinating the read clock domain and the write clock domain, thereby improving the utilization rate of FIFO memory resources.
In one embodiment, the clock synchronization of the synchronization definition unit is determined by a reference write clock and a reference read clock, which are one standard clock selected by the synchronization definition unit to facilitate and manage data transfer and synchronization between different clock domains in the system.
The synchronous definition unit selects the write clock with higher frequency and more related communication modules in all the communication modules as a reference write clock, and takes the reference write clock as a reference, if the write clock of the communication module is consistent with the reference write clock, the write interface of the communication module is indicated to perform write operation in the same write clock domain, and the write interface of the communication module is not related to clock domain crossing operation, so that no additional synchronous operation is needed, and the synchronous definition unit removes the write clock synchronous logic of the communication module. If the write clock of the communication module is inconsistent with the reference write clock, it indicates that the write interface of the communication module performs write operation in different write clock domains, and in order to ensure the integrity and correctness of data transmission between the different write clock domains, the write clock synchronization logic of the communication module needs to be enabled.
Similarly, the synchronization definition unit selects the read clock with higher frequency and more related communication modules in all the communication modules as the reference read clock, and decides whether to enable the read clock synchronization according to the consistency of the read clock of the communication modules and the selected reference read clock. If the read clock of the communication module is consistent with the reference read clock, the synchronous definition unit removes the read clock synchronous logic of the communication module; if the read clock of the communication module is inconsistent with the reference clock, the synchronization definition unit enables the read clock synchronization logic of the communication module.
In this embodiment, the synchronization definition unit allows the system to operate in a multi-clock domain scenario by setting whether clock synchronization is enabled.
The reassignment unit is used for storing an address range in the FIFO memory assigned to each communication module, the address range being defined by a start address and an end address, i.e. a memory space in the FIFO memory from the start address to the end address is assigned to one communication module. It will be appreciated that all of the memory space of the FIFO memory is shared by all of the communication modules, and that in order to better utilize the memory resources of the FIFO memory, it is necessary to reasonably allocate all of the memory space of the FIFO memory to each communication module, wherein each communication module can use the address range allocated for that communication module in the FIFO memory.
In practical application, the system software configures the address range allocated to each communication module, and the reassignment unit is connected to the system bus, and acquires and stores the allocated address range through the system bus.
In one embodiment, the reassignment unit is mainly composed of a general purpose configuration register, and the system software assigns a corresponding memory space for each communication module by configuring the value of the configuration register corresponding to the address of the FIFO memory. The configuration register is defined as follows:
A start address and an end address of the communication module 1 FIFO;
A start address and an end address of the communication module 2 FIFO;
……
The communication module n FIFO start address and end address.
Wherein the address ranges of each communication module defined in the configuration register are mutually independent, i.e. there is no overlap of the address ranges allocated to each communication module, to prevent FIFO access collision. Meanwhile, the address boundary of each address range stored in the configuration register cannot exceed the effective range of the FIFO memory, so that invalid FIFO access operation is prevented from occurring, and data loss and error fetching are caused.
In the FIFO memory read-write processing circuit in this embodiment, read control and write control are separated, so that parallel execution of FIFO write operation and read operation is supported through the write operation control module and the read operation control module, respectively, and execution efficiency of the system is improved.
It should be noted that, the write operation control module and the read operation control module may use different clocks, so as to meet the requirement of separating the read clock and the write clock of the plurality of communication modules, for example, the write interface may use a functional clock, receive data from the external interface of the chip according to the configurable baud rate and store the data into the FIFO, and the read interface may use a system bus clock to read FIFO data to the CPU processor. Based on this, the write operation control module and the read operation control module have important significance in handling asynchronous operations, improving system performance and flexibility.
Referring to fig. 1, the write operation control module is composed of a write interface synchronization logic unit and a write operation judgment strobe unit connected to each other.
The write operation control module accesses the write interfaces (write interface 1, write interfaces 2, …, write interface n) of different communication modules, wherein the write interfaces of different communication modules may use different clock signals, which may lead to different timing between the different write interfaces when data is written into the FIFO memory, and a risk of data collision or loss may occur. The main function of the write interface synchronization logic unit is to carry out synchronization processing on different write clock signals which are accessed, the write interface synchronization logic unit is connected with the synchronization definition unit, the write interface synchronization logic unit executes write operation synchronization of the write interface according to the clock synchronization determined by the synchronization definition unit, and the data (including write enable signals and write data) of the write interface of the communication module can be correctly transmitted to the write interface synchronization logic unit.
Specifically, in the case where the synchronization definition unit removes the write clock synchronization logic of the communication module, the write interface synchronization logic unit may directly receive data transmitted by the write interface of the communication module. In the case where the synchronous definition unit enables the write clock synchronous logic of the communication module, the write interface synchronous logic unit may use a two-stage synchronous and asynchronous handshake mechanism to ensure that the data of the write interface is properly transferred and processed between the unsynchronized clock domains so that the write interface synchronous logic unit is able to receive the data of the write interface.
It can be understood that the write operation control module accesses the write interfaces of all the communication modules, and in one operation period, there may be multiple write interfaces to initiate write operation requests, and for the safety and integrity of data, write authority arbitration needs to be performed on the write interfaces where the communication modules initiate write operations. The write operation judging gating unit in the write operation control module is used for determining the write authority of the write interface synchronized by the write interface synchronization logic unit, judging whether the write interface has the write authority, namely whether the write interface is allowed to write data into the FIFO memory, and gating a write interface passage corresponding to the write interface with the write authority, wherein the write operation judging gating unit is respectively connected with the FIFO memory and the empty-full state judging module, and the passage selection can be understood as selecting the output passage of the write operation control module, so that the gated write interface passage can output the data related to the write interface with the write authority to the FIFO memory to complete the writing of the data and output the data to the empty-full state judging module to judge the full state. For example, both the communication module 1 and the communication module 2 initiate a write request, and the write operation judging gating unit confirms that the write interface of the communication module 1 has write permission, and at this time, the write interface channel corresponding to the communication module 1 is gated, so that relevant data of the write interface of the communication module 1 is output to the FIFO memory and the empty-full state judging module, while relevant data of the write interface of the communication module 2 is not externally transmitted to other modules.
In one embodiment, the write operation judging strobe unit determines only one write interface having write authority in one operation cycle. If multiple write interfaces write data to FIFO memory simultaneously in the same operating cycle, data collisions may result, causing problems with the integrity of the data. The write operation judging and gating unit ensures that only one write interface obtains write permission in each operation period, and can ensure that each write operation is performed under the condition of no interference, thereby ensuring the integrity of written data.
Referring to fig. 2, fig. 2 shows an internal structure schematic diagram of the write operation judgment gate unit. The write operation judging gating unit includes n sets of write pointer counters and n first waiting control units, a write operation arbitration judging unit, and a first path selector. The n write pointer counting units and the n first waiting control units are respectively configured for the n communication modules, the write pointer counting units can track the data writing position of one communication module, the first waiting control unit controls the execution state of writing operation of one communication module, and one write pointer counting unit and one first waiting control unit form a write interface input circuit. The write operation arbitration judging unit and the first path selector constitute an interface output circuit of the write operation judgment strobe unit.
The write operation judging gating unit receives the write enabling signal and the write data output by the write interface synchronous logic unit, and the write enabling signal triggers the write pointer counting unit to count so as to obtain a write pointer of the communication module. In practical applications, the address range allocated by the reassignment unit to the communication module will be accessed to the write pointer counting unit allocated to the corresponding communication module, and for example, the start address 1 and the end address 1 of the communication module 1 will be accessed to the write pointer counting unit configured for the communication module 1. The write pointer counting unit counts in the address range allocated by the communication module, namely, the change range of the write pointer is positioned in the address range formed by the starting address and the ending address allocated by the communication module. The write pointer counting unit outputs the obtained write pointer to the outside of the first path selector (FIFO memory and empty-full state judgment module).
The write operation arbitration judging unit receives write enable signals sent by all write interfaces to carry out arbitration judgment, ensures that only one write interface obtains write permission in each operation period, and feeds back an arbitration result to a corresponding first waiting control unit, wherein the arbitration result refers to the write permission of the write interface of the communication module. For example, the write operation arbitration judging unit performs authority arbitration on the received write enable signal 1 of the communication module 1, obtains an arbitration feedback 1, and returns the arbitration feedback 1 to the communication module 1 through the first waiting control unit.
In one embodiment, the write operation arbitration determination unit determines the write permission of the write interface based on the arbitration priority. The write operation arbitration judging unit determines which write interface can obtain the write authority according to the arbitration judging priority, and the process ensures that when a plurality of write interfaces simultaneously request write operation, the write operation can be orderly arbitrated, so that collision is avoided and data consistency is maintained. The write operation arbitration judging unit performs arbitration judgment on the write interface transmitting the write enable signal according to a preset arbitration judgment priority, wherein the priority rule can be a fixed priority method or a cyclic priority, etc.
In one embodiment, the write operation arbitration judging unit arbitrates the judging priority by the reassigning unit, and selects one of the fixed priority or the round-robin priority as the arbitration judging priority of the write operation arbitration judging unit. In practical application, the reassigning unit can set default arbitration priority when the system is initialized, and can also receive configuration commands through the external interface, wherein the commands are used for modifying the arbitration priority, so that the reassigning unit can set different arbitration priorities and dynamically adjust the arbitration priority in the running process so as to adapt to different application scenes and requirements.
The first waiting control unit judges whether the write interface obtains the write permission according to the judgment result fed back by the write operation arbitration judgment unit (i.e. the arbitration feedback in fig. 2), if the write interface does not obtain the write permission, a waiting signal is output, so that the write interface enters a waiting state until the write interface obtains the write permission. If the write interface obtains write permission, the write interface is capable of performing a write operation to write data to the FIFO memory.
The write operation arbitration determination unit also outputs an identifier (i.e., write interface ID) corresponding to the write interface that acquired the write authority after performing the arbitration.
The first path selector receives the identifier from the write operation arbitration judging unit, and gates the corresponding write interface path according to the received identifier, and transmits the related data of the write interface with the write authority to other modules or units. Referring to fig. 2, the first path selector accesses the relevant data of the write interfaces of all the communication modules, and if the write interface of the communication module 1 is the write interface of the communication module 1, the first path selector gates the relevant write interface path of the communication module 1, and the first path selector outputs the relevant data about the write interface of the communication module 1.
The output of the first path selector may be received by the FIFO memory so that data can be written to the FIFO memory in accordance with the data. In addition, the output of the first path selector can be received by the empty-full state judging module, so that the empty-full state judging module can correctly update the empty-full state of the storage space allocated by the communication module, and correct storage and reading of data are guaranteed.
The read operation control module is very similar in function and structure to the write operation control module. Referring to fig. 1, the read operation control module is composed of a degree interface synchronization logic unit and a read operation judgment gating unit, which are connected with each other.
The read operation control module accesses the read interfaces (read interface 1, read interfaces 2, …, read interface n) of the communication module, wherein the read interfaces of different communication modules may use different clock signals, which may cause different timing between the different read interfaces when reading the data of the FIFO memory, and may cause erroneous reading or loss of the data. The main function of the read interface synchronous logic unit is to synchronously process different read clock signals which are accessed, the read interface synchronous logic unit is connected with the synchronous definition unit, and the read interface synchronous logic unit executes read operation synchronization of the read interface according to the clock synchronization determined by the synchronous definition unit, so that the data (including a read enabling signal) of the read interface of the communication module can be correctly transmitted to the read interface synchronous logic unit.
Specifically, in the case that the synchronization definition unit removes the read clock synchronization logic of the communication module, the read interface synchronization logic unit may directly receive data transmitted by the read interface of the communication module. In the case where the synchronous definition unit enables read clock synchronization of the communication module, the read interface synchronization logic unit may use a two-stage synchronous and asynchronous handshake mechanism to ensure that data of the read interface is properly transferred and processed between unsynchronized clock domains, enabling the read interface synchronization logic unit to receive data of the read interface.
It can be understood that the read operation control module accesses the read interfaces of all the communication modules, and in one operation period, there may be multiple read interfaces to initiate a read operation request, and for the safety of data, it is necessary to perform read authority arbitration on the read interfaces of the communication modules that initiate the read operation. The read operation judging and gating unit in the read operation control module is used for determining the read authority of the read interface synchronized by the read interface synchronization logic unit, judging whether the read interface obtains the read authority, namely whether the read interface is allowed to read related data in the FIFO memory, and gating a read interface passage corresponding to the read interface with the read authority, wherein the read operation judging and gating unit is respectively connected with the FIFO memory and the empty-full state judging module, and the passage selection can be understood as selecting the output passage of the read operation control module, so that the gated read interface passage can output the data related to the read interface with the read authority to the FIFO memory to complete the reading of the data and output the data to the empty-full state judging module to judge the empty state. For example, both the communication module 1 and the communication module 2 initiate a read request, and the read operation judging and gating unit confirms that the read interface of the communication module 1 has read permission, and at this time, the corresponding read interface channel of the communication module 1 is gated, so that relevant data of the read interface of the communication module 1 is output to the FIFO memory and the empty-full state judging module, while relevant data of the read interface of the communication module 2 is not externally transmitted to other modules.
In one embodiment, the read operation judgment strobe unit determines only one read interface having read authority in one operation cycle. If multiple read interfaces access the FIFO memory simultaneously within the same operating cycle, data collisions may result, causing problems with the integrity of the data, resulting in incorrect data being read by the system. The read operation judging and gating unit ensures that only one read interface obtains the read permission in each operation period, and can ensure that each read operation is performed under the condition of no interference, thereby ensuring the consistency of data.
Referring to fig. 3, fig. 3 shows an internal structure schematic diagram of the read operation judgment gate unit. The read operation judging gating unit comprises n groups of read pointer counters, n second waiting control units, a read operation arbitration judging unit and a second path selector. The n groups of read pointer counting units and the n second waiting control units are respectively configured for the n communication modules, the read pointer counting units can track the data reading position of one communication module, and the second waiting control units control the execution state of the read operation of one communication module. A read pointer counting unit and a second waiting control unit form a read interface input circuit. The read operation arbitration judging unit and the second path selector constitute an interface output circuit of the read operation judgment gate unit.
The read operation judging gating unit receives a read enabling signal output by the read interface synchronous logic unit, and the read enabling signal triggers the read pointer counting unit to count so as to obtain a read pointer of the communication module. In practical applications, the address range allocated by the reassignment unit to the communication module will be accessed to the read pointer counting unit allocated to the corresponding communication module, and for example, the start address 1 and the end address 1 of the communication module 1 will be accessed to the read pointer counting unit configured for the communication module 1. The read pointer counting unit counts in the address range allocated by the communication module, namely, the change range of the read pointer is positioned in the address range formed by the starting address and the ending address allocated by the communication module. The read pointer counting unit outputs the obtained read pointer to the second path selector.
The read operation arbitration judging unit receives the read enabling signals sent by all the read interfaces to carry out arbitration judgment, and feeds back an arbitration result to the corresponding second waiting control unit, wherein the arbitration result refers to the read authority of the read interface of the communication module. For example, the read operation arbitration judging unit performs authority arbitration on the received read enable signal 1 of the communication module, obtains arbitration feedback 1, and returns the arbitration feedback 1 to the communication module 1 through the second waiting control unit.
In one embodiment, the read operation arbitration determination unit determines the read authority of the read interface based on the arbitration determination priority. The read operation arbitration judging unit determines which read interface can obtain the read authority according to the arbitration judging priority, and the process ensures that when a plurality of read interfaces simultaneously request read operation, the read operation can be orderly arbitrated, so that collision is avoided and data consistency is maintained. The read operation arbitration judging unit judges the priority according to the preset arbitration, and performs arbitration on the read interface which sends the read enabling signal, wherein the priority rule can be a fixed priority method or a cyclic priority, etc.
In one embodiment, the arbitration priority used by the read operation arbitration unit is controlled by the reassignment unit, and one of the fixed priority or the round-robin priority is selected as the arbitration priority of the read operation arbitration unit. In practical application, the reassigning unit can set default arbitration priority when the system is initialized, and can also receive configuration commands through the external interface, wherein the commands are used for modifying the arbitration priority, so that the reassigning unit can set different arbitration priorities and dynamically adjust the arbitration priority in the running process so as to adapt to different application scenes and requirements.
The second waiting control unit judges whether the read interface obtains the read right according to the read right of the read interface (i.e. arbitration feedback in fig. 3), if the read interface does not obtain the read right, a waiting signal is output to enable the read interface to enter a waiting state until the read interface obtains the read right. If the read interface obtains read rights, the read interface is capable of performing a read operation to read data from the FIFO memory.
The read operation arbitration judging unit also outputs an identifier (i.e., a read interface ID) corresponding to the read interface that obtains the read right after performing the arbitration.
The second path selector receives the identifier from the read operation arbitration judging unit, and gates the corresponding read interface path according to the received identifier, and transmits the related data of the read interface with the read authority to other modules or units. Referring to fig. 2, the second path selector has access to the relevant data of the read interfaces of all the communication modules, and if the read interfaces of the communication module 1 have read authority, the second path selector gates the relevant read interface path of the communication module 1, and the second path selector outputs the relevant data about the read interfaces of the communication module 1.
The output of the second path selector may be received by the FIFO memory so that the associated data can be read from the FIFO memory based on the data. In addition, the output of the second path selector can be received by the empty-full state judging module, so that the empty-full state judging module can correctly update the empty-full state of the storage space allocated by the communication module, and correct storage and reading of data are guaranteed.
The FIFO memory is connected with the write operation judgment gating unit, and can obtain the related data of the write interface with the write permission, so that the FIFO memory can store the data written by the write interface with the write permission in the address range allocated by the communication module with the write permission. Referring to fig. 1, the relevant data of the write interface with write permission includes a write pointer of a communication module with write permission, write data and a write enable signal, and the three parameters can realize writing data into the FIFO memory, wherein the write pointer address is a specific address where the data needs to be written in the FIFO memory, the write data is data information actually to be written into the FIFO memory, the write enable signal is a control signal for indicating whether the FIFO memory allows writing operation, and when the write enable signal is high (logic 1), the FIFO memory allows writing data; when the write enable signal is low (logic 0), the FIFO memory will ignore the write request.
The FIFO memory is connected with the read operation judgment gating unit and can obtain the related data of the read interface with the read right, so that the FIFO memory can read the data read by the read interface with the read right in the address range allocated by the communication module with the read right. Referring to fig. 1, the relevant data of the read interface with read permission includes a read pointer address and a read enable signal, which enable reading data from the FIFO memory, wherein the read pointer address points to the position of the data to be read in the FIFO memory, the read enable signal is a control signal for indicating whether the FIFO memory is allowed to perform a read operation, and when the read enable is high (logic 1), the FIFO memory is allowed to read data; when the read enable is low (logic 0), the FIFO memory does not allow the data to be read.
In practical applications, the same type of write interface and read interface are used for each communication module, where the bit width of the read-write data of the communication module needs to be equal to or smaller than the effective bit width of the FIFO memory.
Referring to fig. 1, the empty-full state judging module is connected with a write operation judging gating unit in the write operation control module, and obtains relevant data of a write interface for obtaining write permission by a write interface passage gated by the write operation judging gating unit, including a write pointer of a communication module for obtaining the write permission. The empty-full state judging module is also connected with the reconfiguration unit to acquire the address range of the communication module for acquiring the writing authority.
It can be understood that the address range of the communication module is a space where the write interface of the communication module can write data into the FIFO memory, and the write pointer address is a position where the latest written data is recorded, based on which the empty-full state determination module can determine whether the memory space of the communication module is full by comparing the write pointer and the read pointer within the address range of the communication module that obtains the write permission.
In practical application, the full flag output by the empty-full state judging module is returned to the communication module, and the full flag can indicate that the storage space allocated by the communication module has reached the upper limit of the capacity of the communication module, and writing operation can not be performed any more, which is very important for ensuring the integrity of data and the normal operation of the system.
Similarly, the empty-full state judging module is also connected with the reading operation judging gating unit in the reading operation control module, and obtains the related data of the reading interface for obtaining the reading authority through the reading interface passage gated by the reading operation judging gating unit, and the reading pointer comprises a reading pointer of the communication module for obtaining the reading authority, and the reading pointer is the position for recording the latest data reading. Based on this, the empty-full state judgment module determines whether the communication module is empty or not by comparing the read pointer and the write pointer within the address range of the communication module that acquires the read right.
In practical application, the empty identifier output by the empty-full state judging module can be returned to the communication module, and the empty identifier can indicate that the storage space allocated by the communication module does not store any data and cannot be read any more, so that invalid or erroneous data are avoided.
In this embodiment, writing data may change the storage space of the communication module from an unfilled state to a filled state, and reading data may change the storage space of the communication module from a non-empty state to an empty state, so that the empty-filled state determination module may determine the empty-filled state of the storage space of the communication module after each writing operation and each reading operation, thereby timely and accurately reflecting the actual use state of the storage space and ensuring correct processing of the data.
Referring to fig. 4, fig. 4 is a schematic diagram showing an internal structure of the empty-full state judgment module. The empty-full state judgment module can be functionally divided into a full state judgment circuit and an empty state judgment circuit.
The configuration of the full state determination circuit is described in detail below.
Referring to fig. 4, the full state judgment circuit is constituted by a third path selector, a fourth path selector, a first gray code synchronizer, and a full state judgment unit. The third and fourth path selectors are path selectors with n being one. The identifier (write interface ID) corresponding to the write interface that obtains the write permission by the write operation arbitration determination unit is output to the third and fourth path selectors, so that the third and fourth path selectors can gate the write interface path corresponding to the write interface having the write permission according to the identifier. The third path selector is connected to the address ranges of n communication modules, each path corresponds to the address range of one communication module, and the address range of the communication module obtaining the writing authority is output by gating the path corresponding to the identifier in the third path selector. The fourth path selector is connected to the read pointers of n communication modules, each path corresponds to the read pointer of one communication module, where the read pointers of n communication modules are the read pointers 1-n (representing the read pointers of the communication modules 1-n) output by the read operation control module in fig. 1, and the read pointers of the communication modules obtaining the write permission are output by gating the paths corresponding to the identifiers in the fourth path selector.
Since the read pointer of the communication module that takes the write rights is generated by the read clock domain and is a multi-bit signal, appropriate synchronization processing is required to avoid metastability and inconsistencies when passing between the different clock domains. The first Gray code synchronizer performs synchronization processing on the read pointer to generate a full judgment read pointer. The basic processing procedure of the first gray code synchronizer is as follows: 1) Converting the read pointer into Gray code data, and sampling once by using a read clock; 2) Performing two-stage synchronous sampling by using a write clock; 3) Gray code data is converted into hexadecimal data.
In the write clock domain, the full state determination unit determines the full state of the memory space allocated by the communication module by determining the full determination read pointer and the write pointer of the communication module that obtains the write permission within the address range of the communication module that obtains the write permission, where the write pointer is output by the write pointer counting unit in the write operation control module. In a write operation, when the write pointer is equal to or smaller than but close to the full judgment read pointer, the storage space allocated by the communication module is considered to be full, and a valid full identification is output.
In practical application, the full flag output by the full state judging circuit is returned to the communication module with the write permission through the path gated by the first path selector in the write operation control module.
The configuration of the air condition determination circuit will be described in detail with reference to fig. 4.
The empty state judgment circuit is composed of a fifth path selector, a sixth path selector, a second Gray code synchronizer and an empty state judgment unit. The fifth and sixth path selectors are each one-n path selectors. The identifier (read interface ID) corresponding to the read interface for acquiring the read right, which is obtained by the read operation arbitration judging unit, is output to the fifth path selector and the sixth path selector, so that the fifth path selector and the sixth path selector can gate the read interface path corresponding to the read interface for acquiring the read right according to the identifier. The fifth path selector is connected to the address ranges of n communication modules, each path corresponds to the address range of one communication module, wherein the write pointers of the n communication modules are the write pointers 1-n (representing the write pointers of the communication modules 1 to n) output by the write operation control module in fig. 1, and the address range of the communication module obtaining the read authority is output by gating the path corresponding to the identifier in the fifth path selector. The sixth path selector is connected with the write pointers of the n communication modules, each path corresponds to the write pointer of one communication module, and the write pointer of the communication module obtaining the read authority is output by gating the path corresponding to the identifier in the sixth path selector.
Since the write pointer of the communication module that takes the read rights is generated by the write clock domain and is a multi-bit signal, appropriate synchronization processing is required to avoid metastability and inconsistencies when passing between the different clock domains. The second Gray code synchronizer performs synchronization processing on the write pointer to generate a blank judgment read pointer. The basic processing procedure of the second gray code synchronizer is as follows: 1) Converting the write pointer into Gray code data, and sampling once by using a write clock; 2) Performing two-stage synchronous sampling by using a read clock; 3) Gray code data is converted into hexadecimal data.
In the write clock domain, the empty state judging unit judges through empty judgment a write pointer and a read pointer of a communication module for obtaining the read permission, wherein the read pointer is output by a read pointer counter in the read operation control module, and can determine the empty state of the storage space allocated by the communication module. In the reading operation, when the read pointer is equal to the empty judgment write pointer, the storage space allocated by the communication module is considered to be empty, and the output empty mark is valid.
In practical application, the empty identifier output by the empty state judging circuit is returned to the communication module with the read authority through the read interface channel gated by the second channel selector in the write operation control module.
In the above embodiment, the FIFO memory read-write processing circuit is configured with a FIFO memory shared by all communication modules, and the configurable module divides the storage space allocated by each communication module in the FIFO memory, and performs clock synchronization on the read-write interfaces of different clock domains, and then is configured with an independent write operation control module and a read operation control module to control the read-write operations of different clock domains, so that the communication modules of different clock domains can initiate the read-write operations on the FIFO memory, effectively improving the utilization rate of the storage resources of the FIFO memory, and reducing the total size of the FIFO memory.
In one embodiment, a chip is provided, the chip comprising a FIFO memory read-write processing circuit.
It should be noted that the logic and/or steps represented in the flowcharts or otherwise described herein, for example, may be considered as a ordered listing of executable instructions for implementing logical functions, and may be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). In addition, the computer readable medium may even be paper or other suitable medium on which the program is printed, as the program may be electronically captured, via, for instance, optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory.
It is to be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, may be implemented using any one or combination of the following techniques, as is well known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, application specific integrated circuits having suitable combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.
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