CN118916210A

CN118916210A - Data processing method and device, electronic device and computer readable storage medium

Info

Publication number: CN118916210A
Application number: CN202411187106.7A
Authority: CN
Inventors: 王宇轩; 周鹏
Original assignee: Hygon Information Technology Co Ltd
Current assignee: Hygon Information Technology Co Ltd
Priority date: 2024-08-27
Filing date: 2024-08-27
Publication date: 2024-11-08

Abstract

At least one embodiment of the present disclosure provides a data processing method and device, an electronic device, and a computer-readable storage medium. The data processing method includes: receiving first data and a first cyclic redundancy check code of the first data; performing a cyclic redundancy check operation on the first data to generate a second cyclic redundancy check code; generating a syndrome based on the first cyclic redundancy check code and the second cyclic redundancy check code; and correcting errors of the first data based on the syndrome. The data processing method can correct data errors, improve data transmission efficiency, and achieve data protection in low-cost scenarios, for example.

Description

Data processing method and device, electronic device and computer readable storage medium

Technical Field

Embodiments of the present disclosure relate to a data processing method and apparatus, an electronic apparatus, and a computer-readable storage medium.

Background

Memory, such as Double Data Rate (DDR) memory, is inevitably subject to interference from environmental factors such as electromagnetic during operation, resulting in memory errors. For example, memory errors can cause fatal problems for users with high stability requirements.

From a severity perspective, memory errors can be categorized into three categories: correctable Errors (CEs), uncorrectable Errors (UEs) and undetectable errors. The sources of errors are errors introduced in the link transmission, potential flipping due to unstable retention time in the memory particles, circuit failure, etc.

For example, where a memory bank with error checking and correction (Error Correcting Code, ECC) is used in a situation where the system stability is required, a memory controller of a processor (e.g., CPU) generates an ECC code while writing data into the memory bank, then stores the data together with the data to be written, reads the data together with the ECC code when reading, and then performs error correction by using the ECC code. However, this approach requires an increase in the total number of memory particles (e.g., an increase in memory particles for storing ECC codes), resulting in a significant increase in cost and power consumption.

Disclosure of Invention

At least one embodiment of the present disclosure provides a data processing method, including: receiving first data and a first cyclic redundancy check code of the first data; performing cyclic redundancy check operation on the first data to generate a second cyclic redundancy check code; generating a syndrome based on the first cyclic redundancy check code and the second cyclic redundancy check code; and error correcting the first data based on the syndrome.

For example, a data processing method according to at least one embodiment of the present disclosure, which corrects error of first data based on a syndrome, includes: determining whether the first data has an error based on the syndrome; in response to determining that the first data has an error, error correction is performed on the first data.

For example, according to a data processing method of at least one embodiment of the present disclosure, in response to determining that first data has an error, correcting the first data includes: responsive to determining that the first data has an error, determining whether the error is a correctable error based on a syndrome value of the syndrome; and determining an error location of the error in response to the error being a correctable error, and correcting the data of the error location.

For example, according to a data processing method of at least one embodiment of the present disclosure, generating a syndrome based on a first cyclic redundancy check code and a second cyclic redundancy check code includes: performing an exclusive or operation on the first and second cyclic redundancy check codes to generate a syndrome, determining whether the first data has an error based on the syndrome, comprising: determining that the first data is free of errors in response to the syndrome being 0; and determining that the first data is in error in response to the syndrome not being 0.

For example, according to a data processing method of at least one embodiment of the present disclosure, determining whether an error is a correctable error based on a syndrome value of a syndrome and determining an error location of the error includes: determining whether the error is a correctable error and determining an error location of the error by the syndrome value and a lookup table in which a target syndrome value characterizing the error as a correctable error and a corresponding target error location are recorded.

For example, a data processing method according to at least one embodiment of the present disclosure, determining whether an error is a correctable error and determining an error location of the error by a syndrome value and a lookup table, includes: indexing a lookup table based on the syndrome value to determine whether the syndrome value hits the target syndrome value; and in response to the hit, determining that the error is a correctable error, and determining a target error location in the lookup table corresponding to the syndrome value as an error location; or in response to a miss, determine that the error is an uncorrectable error.

For example, according to a data processing method of at least one embodiment of the present disclosure, an error signal is output in response to an error being an uncorrectable error.

For example, according to a data processing method of at least one embodiment of the present disclosure, in response to an error being a correctable error, correcting data of an error location includes: and in response to the error being a correctable error, flipping bits of the error location to obtain corrected first data.

For example, a data processing method according to at least one embodiment of the present disclosure further includes: and in response to determining that the first data is free of errors, taking the first data as the first data after error correction.

For example, a data processing method according to at least one embodiment of the present disclosure further includes: only data corresponding to the data code in the corrected first data is output, and data corresponding to the cyclic redundancy check code in the corrected first data is not output.

For example, according to a data processing method of at least one embodiment of the present disclosure, the data processing method is applied to a 5 th generation double data rate memory standard, and the cyclic redundancy check operation includes a cyclic redundancy check generation algorithm defined in a protocol using the 5 th generation double data rate memory standard.

For example, according to a data processing method of at least one embodiment of the present disclosure, first data and a first cyclic redundancy check code are received via transmission of a link, and the first cyclic redundancy check code before transmission is generated by performing a cyclic redundancy check operation on the first data before transmission.

At least one embodiment of the present disclosure provides a data processing apparatus including: a cyclic redundancy check generation module configured to: receiving first data; performing cyclic redundancy check operation on the first data to generate a second cyclic redundancy check code; and a cyclic redundancy check and error correction module configured to: receiving a first cyclic redundancy check code of the first data; generating a syndrome based on the first cyclic redundancy check code and the second cyclic redundancy check code; and error correcting the first data based on the syndrome.

For example, in order to correct the first data based on the syndromes, the data processing apparatus according to at least one embodiment of the present disclosure, the cyclic redundancy check and correction module is further configured to: determining whether the first data has an error based on the syndrome; in response to determining that the first data has an error, error correction is performed on the first data.

For example, in order to perform error correction on the first data in response to determining that the first data has an error, the data processing apparatus according to at least one embodiment of the present disclosure, the cyclic redundancy check error correction module is further configured to: responsive to determining that the first data has an error, determining whether the error is a correctable error based on a syndrome value of the syndrome; and determining an error location of the error in response to the error being a correctable error, and correcting the data of the error location.

For example, in order to determine whether an error is a correctable error and to determine an error location of the error based on a syndrome value of a syndrome, a data processing apparatus according to at least one embodiment of the present disclosure, the cyclic redundancy check error correction module is further configured to: determining whether the error is a correctable error and determining an error location of the error by the syndrome value and a lookup table in which a target syndrome value characterizing the error as a correctable error and a corresponding target error location are recorded.

For example, in order to correct data of an error location in response to an error being a correctable error, the data processing apparatus according to at least one embodiment of the present disclosure, the cyclic redundancy check and correction module is further configured to: and in response to the error being a correctable error, flipping bits of the error location to obtain corrected first data.

For example, in order to generate a syndrome based on the first cyclic redundancy check code and the second cyclic redundancy check code, the data processing apparatus according to at least one embodiment of the present disclosure, the cyclic redundancy check error correction module is further configured to: performing an exclusive or operation on the first cyclic redundancy check code and the second cyclic redundancy check code to generate a syndrome, the cyclic redundancy check error correction module further configured to, in order to determine whether the first data has an error based on the syndrome: determining that the first data is free of errors in response to the syndrome being 0; and determining that the first data is in error in response to the syndrome not being 0.

For example, a data processing device according to at least one embodiment of the present disclosure is a memory controller or memory.

For example, a data processing apparatus according to at least one embodiment of the present disclosure is applied to DDR5, and the cyclic redundancy check operation includes using a cyclic redundancy check generation algorithm defined in a protocol of DDR 5.

At least one embodiment of the present disclosure provides an electronic device including at least one processing unit and a memory; wherein the memory stores computer readable instructions and is communicatively coupled to the at least one processing unit; the at least one processing unit is configured to execute computer readable instructions stored in the memory to implement the data processing method as described above.

At least one embodiment of the present disclosure provides a computer-readable storage medium having computer-readable instructions stored therein, which when executed by a processor, implement the data processing method as described above.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments of the present disclosure will be briefly described below. It is apparent that the figures in the following description relate only to some embodiments of the present disclosure and are not limiting of the present disclosure.

FIG. 1 illustrates a schematic diagram of an exemplary memory controller read-write DDR5 DRAM;

FIG. 2 illustrates a flow chart of a data processing method in accordance with at least one embodiment of the present disclosure;

FIG. 3 illustrates a schematic diagram of a data processing apparatus 300 in accordance with at least one embodiment of the present disclosure;

FIG. 4 illustrates a schematic diagram of a CRC error correction architecture in accordance with at least one embodiment of the present disclosure;

FIG. 5 illustrates a diagram of the distribution of data bits and CRC in a single DDR5 memory granule in accordance with at least one embodiment of the present disclosure;

FIG. 6 illustrates a schematic diagram of an exemplary CRC check module;

FIG. 7 illustrates a schematic diagram of a CRC error correction module according to at least one embodiment of the present disclosure;

FIG. 8 illustrates a schematic diagram of using CRC error correction at a 32-bit DDR5 channel in accordance with at least one embodiment of the disclosure;

FIG. 9 illustrates a schematic diagram of an electronic device in accordance with at least one embodiment of the present disclosure;

FIG. 10 illustrates a schematic diagram of a computer-readable storage medium in accordance with at least one embodiment of the present disclosure;

fig. 11 illustrates a schematic diagram of another electronic device in accordance with at least one embodiment of the present disclosure.

Detailed Description

Reference will now be made in detail to the specific embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. While the disclosure will be described in conjunction with the specific embodiments, it will be understood that it is not intended to limit the disclosure to the described embodiments. On the contrary, it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the disclosure as defined by the appended claims. It should be noted that the method operations described herein may be implemented by any functional block or arrangement of functions, and that any functional block or arrangement of functions may be implemented as a physical entity or a logical entity, or a combination of both.

In order that those skilled in the art will better understand the present disclosure, the present disclosure will be described in further detail below with reference to the accompanying drawings and detailed description.

Note that the examples to be presented below are only specific examples and are not intended to limit the embodiments of the present disclosure to the particular shapes, hardware, connection relationships, operations, values, conditions, data, sequences, etc., shown and described. Those skilled in the art can, upon reading the present specification, utilize the concepts of the present disclosure to construct additional embodiments not described in the present specification.

The terms used in the present disclosure are those general terms that are currently widely used in the art in view of the functions of the present disclosure, but may vary according to the intention, precedent, or new technology in the art of the person of ordinary skill in the art. Furthermore, specific terms may be selected by the applicant, and in this case, their detailed meanings will be described in the detailed description of the present disclosure. Accordingly, the terms used in the specification should not be construed as simple names, but rather based on the meanings of the terms and the general description of the present disclosure.

A flowchart is used in this disclosure to describe the operations performed by a system according to embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed in order precisely. Rather, the various steps may be processed in reverse order or simultaneously, as desired. Also, other operations may be added to or removed from these processes.

The abbreviations and related terms involved in the present application are first defined and explained.

DDR (Double Data Rate): double rate.

DDR5: the 5 th generation Double Data Rate (Double Data Rate) memory standard.

DDR SDRAM: double rate synchronous dynamic random access memory, commonly known as DDR.

ECC (Error Check Correction): error correcting codes or error correcting codes are a technology capable of realizing error checking and correcting, and can improve the running stability and reliability of a computer.

CE (Correctable Error): errors can be corrected. CE refers to an error that the hardware (chip) can correct based on the ECC algorithm employed by itself. There may be differences in the ability to correct errors due to the different memory controller designs. For example, the memory controller of the mainstream X86 server (supporting memory banks with ECC) can correct any error in a single read operation in a memory granule that is 4 bits wide (X4 width/bit width). If the memory bank (Rank) is composed of 8-bit data bit wide (X8 width/bit wide) memory granules, its correction capability is consistent with that of X4 width memory granules and locations, and in one memory granule of X8 width, 8-bit data of DQ0-7 is included, where only DQ0-3, or DQ4-7 can be corrected.

UE (Uncorrectable Error): errors cannot be corrected. UE refers to an error that cannot be corrected by hardware (chip) based on the ECC algorithm employed by itself. For example, in a read operation, the erroneous data bits are distributed across memory grain of different X4 widths, i.e., errors across memory grain occur, which are uncorrectable errors in view of existing memory control designs. For another example, the memory group is composed of memory granules of X8 width, and its correction capability is consistent with those of memory granules of X4 width, and if the error position is, for example, DQ2-5 in one memory granule of X8 width, the position does not correspond to X4 width although it is X4 width, where the error position DQ2-3 corresponds to one X4 bit width and the error position DQ4-5 corresponds to another X4 bit width, i.e., if the error position of one memory granule spans different X4 bit widths, it cannot be corrected. For another example, if the memory group is made up of memory grains of width X8, its correction capability is consistent with that of the memory grains of width X4, and in one memory grain of X8, if DQ0-4 is, for example, the erroneous bit width (in this case, the width of X5) exceeds the bit width (X4) that can be corrected, and cannot be corrected.

CRC (Cyclic Redundancy Check): cyclic redundancy check. The cyclic redundancy check is a fast algorithm for generating a short fixed bit check code according to data, and is mainly used for detecting or checking errors possibly occurring after data transmission or storage.

It is to be understood that the terminology defined above is for the purpose of describing particular embodiments only, and is not intended to be limiting. For example, the exemplary definitions described above for a particular memory may be extended to other types of memory or other storage. As another example, the above exemplary definition does not exclude its conventional meaning in the art.

The inventors of the present application have realized that in a low cost application scenario, there is a need to not use memory with ECC functionality.

For example, in a low cost application scenario, memory banks with ECC are typically not used. On-die ECC (on-die-ECC) technology has been introduced into DDR5 memory granules, which is an error correction method implemented inside the memory granules, and also generates an ECC code from written data, then stores the ECC code together with the data to be written, performs error correction using the ECC code when reading, and then sends the error corrected data out from inside the memory granules. The technique can greatly reduce potential inversion caused by unstable retention time in memory particles, thereby protecting data inside the memory particles. Although the technology ensures that the data in the memory particles are protected to a certain extent, random errors on a data transmission link (called a link for short) are not in the protection range of on-die-ECC, so that the error on a large number of links can not be corrected directly without using a memory bank with ECC.

Illustratively, in high-speed links, random errors often occur in transmission, as the rate of the link is increasing, resulting in greater challenges for signal integrity. The reliability of the link is generally evaluated using the bit error rate as an indicator. For example, the maximum value of the link error rate specified in the DDR5 protocol is 10-16, and under this level of link reliability, DDR5 may experience link transmission errors every few hours if it continues to operate at a rate of tens of GB/s. This error interval is completely unacceptable, so CRC checks are also defined in DDR 5.

For example, the general procedure of CRC check is that a link transmitting end generates a CRC code via a CRC generation module, a receiving end of the link checks the CRC code, and if the CRC check fails, the link transmitting end initiates a retransmission request or reports the UE to the system. The CRC check can only protect the data on the link, for example, for the process of data reading, if the data sent to the link is in error (for example, the error caused by potential inversion in the memory granule) at the beginning, the sending end of the link can also directly use the erroneous data to generate the CRC code, if no random error occurs in the transmission process, the CRC check can pass, and the read error data can be directly sent to the system (the upper system of the memory controller, for example, the CPU or the Cache) without ECC granule.

FIG. 1 shows a schematic diagram of an exemplary memory controller read-write DDR5 DRAM.

Referring to fig. 1, a memory controller 102 may perform read/write operations of data with a memory granule 104 via a link.

Memory controller 102 and memory granule 104 may have a CRC generation module 106 and a CRC generation module 108, respectively, for performing CRC calculations on the corresponding data or performing corresponding algorithms to generate CRC codes.

Memory controller 102 and memory granule 104 may have a CRC check module 110 and a CRC check module 112, respectively, for performing a CRC check.

The CRC codes in the DDR5 link as shown in fig. 1 can be divided into a Read CRC (Write CRC) code and a write CRC (Read CRC) code, which correspond to the directions of reading and writing, respectively. Typically, the read CRC code and the write CRC code are generated using the same CRC algorithm.

In the memory system shown in fig. 1, the exemplary writing process is generally that the memory controller 102 performs CRC calculation on the data (Wdata) to be transmitted to the memory granule 104 through the CRC generation module 106, to obtain WCRC codes as check codes, and then the memory controller 102 transmits the data and WCRC to the memory granule 104. The memory granule 104 performs CRC calculation on the received data by the CRC generation module 108 (or the CRC check module 112) to obtain a CRC code. Then, the memory granule 104 performs consistency comparison on the received WCRC codes and the calculated CRC codes through the CRC check module 112, so as to implement CRC check. If the CRC check passes, as the received WCRC codes agree with the calculated CRC code, which indicates that the data is error free, then the memory granule 104 may store the read data in the memory granule's storage array 114. If the CRC check fails, as the received WCRC code and the calculated CRC code do not agree, indicating that there is an error in the data, CRC check module 112 sends a retransmission request to CRC generation module 106 for the memory controller to retransmit the data Wdata to the memory controller.

The read process is similar to the write process described above, except that the sender and receiver of the data and the transmission direction of the data are opposite, e.g., the sender of the data is changed from the memory controller 102 to the memory granule 104, the receiver of the data is changed from the memory granule 104 to the memory controller 102, and the data Wdata transmitted therebetween will be changed to Rdata, WCRC code to RCRC code. In order to avoid obscuring the present application, description thereof is omitted. It will be appreciated that in order to facilitate distinguishing between the CRC check processes between the read and write processes, the CRC check between the read and write processes will be referred to herein simply as the read CRC check and the write CRC check, respectively.

The inventors of the present application have appreciated that in a memory system such as that shown in fig. 1 described above, CRC is generally used only to detect errors, which are overcome by retransmission after an error is detected.

Taking the example of the memory controller 102 reading data from the memory granule 104, after detecting an error through the read CRC check, the data is generally considered to be still "intact" (i.e., without error) stored in the memory granule 104, and correct data can be obtained as long as it is reread by the receiving end, so if an error is detected through the read CRC check, the memory controller 102 generally sends a retransmission request and rereads the data at this address from the memory granule 104.

However, the retransmission described above results in a significant amount of bandwidth being wasted. For example, retransmission requires retransmission of an instruction (e.g., a retransmission request) and then the sender can retransmit data based on the instruction, which is not a normal operation of the link. In addition, retransmissions also create significant power consumption overhead. In addition, if the link is severely interfered in a period of time, the error rate may be greatly increased in a period of time, and then the data retransmitted each time in the period of time may not be completely correct, so that each CRC check cannot be passed, the number of retransmission requests reaches the upper limit set by the system, and finally, only the UE can be reported to the system. Thus, although errors can always be detected, the system can be down finally, and the stability and usability of the system are seriously affected.

At least one embodiment of the application provides a data processing method and device, an electronic device and a computer readable storage medium, which can correct data errors, improve data transmission efficiency and realize data protection in a low-cost scene.

Fig. 2 illustrates a flow diagram of a data processing method 200 in accordance with at least one embodiment of the present disclosure. The data processing method 200 described with reference to fig. 2, and additional aspects thereof, may be implemented in a data processing apparatus, an electronic apparatus, a hardware structure, a software structure, or a combination of hardware and software as described below.

Referring to fig. 2, the data processing method 200 includes steps S210 to S240.

In step S210, first data and a first cyclic redundancy check code for the first data are received.

It is understood that the transmission of data may be via a data transmission link (link).

In some embodiments, the first data may be data transmitted between a data sender and a data receiver. For example, the first data may be data transferred between a memory controller and a memory (including memory granules).

In step S220, a cyclic redundancy check operation is performed on the first data to generate a second cyclic redundancy check code.

A Cyclic Redundancy Check (CRC) operation on the first data may generate a short fixed-bit number check code corresponding to the first data, i.e., the second cyclic redundancy check code described above.

In step S230, a syndrome is generated based on the first cyclic redundancy check code and the second cyclic redundancy check code.

The syndrome data may thus characterize the consistency between the first and second cyclic redundancy check codes, and may thus characterize whether an error exists in the first data.

In step S240, the first data is error-corrected based on the syndrome.

In some embodiments, when there is an error in the data, the first data may be error corrected, such as by bit flipping or other operations, as the syndromes may characterize the information of the error.

As described above, the data processing method according to at least one embodiment of the present disclosure may correct data errors by syndrome data obtained based on two CRC codes. For example, in contrast to the idea that a CRC employed in a memory architecture such as that described with reference to FIG. 1 is generally only used for error detection, a data processing method in accordance with at least one embodiment of the present disclosure may use the CRC for error correction, thereby correcting data errors.

In other additional aspects, the data processing method according to at least one embodiment of the present disclosure may use CRC for error correction, for example, in comparison with the idea of employing retransmission to avoid errors in the memory architecture described with reference to fig. 1, thereby reducing the number of retransmissions and improving the data transmission efficiency. For another example, a data processing method according to at least one embodiment of the present disclosure may use CRC for error correction, and thus may be applicable to low cost scenarios where ECC techniques are not supported, thereby enabling data protection in low cost scenarios, for example.

Some exemplary additional aspects of data processing methods according to at least one embodiment of the present disclosure are described below.

For example, a data processing method according to at least one embodiment of the present disclosure, wherein correcting the first data based on the syndrome, includes: determining whether the first data has an error based on the syndrome; in response to determining that the first data has an error, error correction is performed on the first data.

As such, the data processing method according to at least one embodiment of the present disclosure may correct erroneous data.

As such, the data processing method according to at least one embodiment of the present disclosure may determine whether the type of the data error is a correctable error and an error location of the correctable error based on the syndrome, and correct the data of the error location, thereby correcting the data error.

In an additional or alternative embodiment, in response to determining that the first data has an error, correcting the first data includes: responsive to determining that the first data has an error, determining whether the error is an uncorrectable error based on the syndrome value of the syndrome; and optionally determining an error location of the error in response to the error being a correctable error, and correcting the data of the error location. That is, the data processing method according to at least one embodiment of the present disclosure may also partially correct uncorrectable errors. For example, for a memory, where the correctable error is a 1-bit error for each x4 memory granule, a data processing method according to at least one embodiment of the present disclosure may correct a 1-bit error for a certain x4 memory granule for a 2-bit error of that x4 memory granule. In terms of accessories, error correction of remaining errors may be achieved in combination with other algorithms or redundant information, thereby achieving error correction of uncorrectable errors.

As such, the data processing method according to at least one embodiment of the present disclosure may determine whether data has an error based on the syndrome by simply obtaining the syndrome through an exclusive or operation.

In additional or alternative embodiments, other operations (exclusive or, addition, subtraction, etc.) may be performed on the first and second cyclic redundancy check codes to generate syndromes, and the adaptation determines whether the data is erroneous by the values of the respective syndromes. For example, the syndrome may be generated by exclusive-or' ing the first and second cyclic redundancy check codes, determining that the first data is not in error in response to the syndrome being all 1, and determining that the first data is in error in response to the syndrome being not all 1.

As such, a data processing method according to at least one embodiment of the present disclosure may determine the type of error and the error location through a lookup table. In an additional aspect, for example, for data transferred between the memory and the memory controller, the relationship of the resulting syndrome value to the error location is generally fixed because the data corresponds to a pin (pin) of a particular memory granule, in which case the type of error and the error location can be efficiently obtained by a pre-obtained look-up table.

In additional or alternative embodiments, the type of error and the error location may be determined by hardware logic (e.g., a processor) or other circuitry.

In additional or alternative embodiments, some or all of the target syndrome values that characterize the errors as uncorrectable errors may also be selectively recorded in the lookup table, or some or all of the target syndrome values that characterize the absence of errors may also be selectively recorded in the lookup table.

As such, a data processing method according to at least one embodiment of the present disclosure may determine the type of error and the error location through a syndrome value index lookup table.

For example, a data processing method according to at least one embodiment of the present disclosure further includes: and outputting an error signal in response to the error being an uncorrectable error.

As such, a data processing method according to at least one embodiment of the present disclosure may output an uncorrectable error, e.g., instruct a technician to perform a corresponding operation, e.g., replace a corresponding component or adjust an environment in which the data error is caused.

For example, a data processing method according to at least one embodiment of the present disclosure, wherein correcting data of an error location in response to an error being a correctable error, includes: and in response to the error being a correctable error, flipping bits of the error location to obtain corrected first data.

In this way, the data processing method according to at least one embodiment of the present disclosure may implement error correction of data of an error location, thereby obtaining error-corrected data.

In an additional or alternative embodiment, the flipping of the bits of the error location may be achieved by exclusive-or-ing the first data with the data of the error location, resulting in error corrected data.

Thus, according to the data processing method of at least one embodiment of the present disclosure, unnecessary error correction operation on data without errors can be avoided, and corresponding calculation overhead is saved.

Thus, the data processing method according to at least one embodiment of the present disclosure can avoid transmission of unnecessary cyclic redundancy check codes, and improve transmission efficiency of data codes. In an additional aspect, for example, for data transferred between the memory and the memory controller, only the information code may be made to be stored in the memory, improving the storage efficiency of the memory.

For example, according to a data processing method of at least one embodiment of the present disclosure, the data processing method is applied to DDR5, and the cyclic redundancy check operation includes using a cyclic redundancy check generation algorithm defined in a protocol of DDR 5.

As such, a data processing method according to at least one embodiment of the present disclosure may be applied to a memory controller and/or memory granule in DDR5, for example, and may implement a corresponding CRC check based on a CRC generation algorithm defined in the DDR5 protocol.

The link here may be any link between a data receiver and a data sender. For example, the link may be a data link between memory control and memory. In some examples, the memory control and memory may be DDR5 enabled memory control and memory.

As such, a data processing method according to at least one embodiment of the present disclosure may correct data errors in link transmission.

Corresponding to the data processing method 200 according to at least one embodiment of the present disclosure, at least one embodiment of the present disclosure also provides a data processing apparatus.

Fig. 3 shows a schematic diagram of a data processing apparatus 300 in accordance with at least one embodiment of the present disclosure.

Referring to fig. 3, a data processing apparatus 300 according to at least one embodiment of the present disclosure includes a CRC generation module 310 and a CRC error correction module 320.

The CRC generation module 310 is configured to: receiving first data; and performing cyclic redundancy check operation on the first data to generate a second cyclic redundancy check code.

The CRC error correction module 320 is configured to: receiving a first cyclic redundancy check code of the first data; generating a syndrome based on the first cyclic redundancy check code and the second cyclic redundancy check code; and error correcting the first data based on the syndrome.

As described above, the data processing apparatus according to at least one embodiment of the present disclosure may correct data errors, improve data transmission efficiency, and achieve data protection in, for example, a low cost scenario.

The additional aspects of the data processing apparatus 300 according to at least one embodiment of the present disclosure may correspond to the additional aspects of the data processing method 200 according to at least one embodiment of the present disclosure, and thus technical effects of the additional aspects of the data processing method 200 according to at least one embodiment of the present disclosure may also be mapped to the additional aspects of the data processing apparatus 300 according to at least one embodiment of the present disclosure, which will not be described again herein.

Some exemplary additional aspects of data processing apparatus 300 in accordance with at least one embodiment of the present disclosure are described below.

One or more exemplary aspects described above in connection with fig. 2 and 3 are described below in connection with example application scenarios. It will be appreciated that the example application scenarios described below are merely examples and are not intended to be limiting, and that one or more aspects described above in connection with fig. 2 and 3 are intended to be implemented in a particular application scenario, and that aspects described below in connection with the example application scenarios may be combined with one or more aspects described above in connection with fig. 2 and 3.

Fig. 4 shows a schematic diagram of a CRC error correction architecture in accordance with at least one embodiment of the present disclosure. It will be appreciated that the CRC error correction architecture shown in fig. 4 will be described below as an example application scenario, and that the various aspects described therein may equally be mapped to other types of memories and memory controllers or other data processing devices having data processing capabilities.

Referring to fig. 4, a memory controller 402 may perform read/write operations of data with a memory granule 404 via a link.

Memory controller 402 and memory granule 404 may have a CRC generation module 406 and a CRC generation module 408, respectively, for performing a CRC calculation or algorithm on the corresponding data to generate a CRC code. CRC generation module 406 and CRC generation module 408 herein may be CRC generation module 310 as described above with reference to fig. 3.

Memory controller 402 and memory granule 404 may have a CRC error correction module 410 and a CRC error correction module 412, respectively. The CRC error correction module 410 and the CRC error correction module 412 herein may be the CRC error correction module 320 described above with reference to fig. 3.

In the CRC error correction architecture, the CRC error correction module 410 and the CRC error correction module 412 may use CRC to perform error correction, and directly output the error corrected data, so as to achieve the purpose of protecting the data on the link, reducing the number of retransmissions, and improving the bandwidth efficiency.

The above-described CRC error correction architecture is provided with a CRC error correction module 410 and a CRC error correction module 412 in both sides of the memory controller 402 and the memory granule 404, thereby implementing data error correction during both data writing and reading. However, depending on the limitations or needs of the memory system design, the CRC error correction module may be provided in only one side, thereby achieving data error correction only during either data writing or reading. For example, the CRC error correction module 410 may be provided only in the memory controller 402, thereby implementing data error correction during reading. For another example, the CRC error correction module 412 may be provided only in the memory granule 404, thereby implementing data error correction in read and write.

The CRC error correction architecture depicted in FIG. 4 may be embodied as a DDR5 memory system. For example, memory controller 402 in FIG. 4 may be a DDR 5-enabled memory controller (referred to as DDR5 memory controller), and memory granule 404 in FIG. 4 may be a DDR 5-enabled memory granule (check DDR5 memory granule).

FIG. 5 illustrates a diagram of the distribution of data bits and CRC in a single DDR5 memory granule in accordance with at least one embodiment of the present disclosure.

Referring to fig. 5, the ddr5 memory system transmits 18 data (also referred to as burst data, i.e., burst 0 through burst 17) in one transmission, and one x4 memory granule (x 4 device) has 4 DQs (pins), i.e., 4 bits (bits) per data, and each x4 memory granule transmits a total of 64 bits of data at a time. After the data transmission is completed, the DDR5 memory granule will continue to transmit CRC codes, i.e., burst 16 and burst 17, for a total of 8 bits.

It will be appreciated that the distribution of data bits and CRCs depicted in fig. 5 is merely exemplary, and that the distribution of data bits and CRCs may be adjusted as appropriate. For example, after the CRC code is generated, the data in burst corresponding to the same pin (i.e., the data for each pin column) within each memory granule or between memory granules may be swapped during transmission.

An exemplary generation formula for an 8-bit CRC code is as follows:

CRC[0]＝D[63]^D[60]^D[56]^D[54]^D[53]^D[52]^D[50]^D[49]^D[48]^D[45]^D[43]^D[40]^D[39]^D[35]^D[34]^D[31]^D[30]^D[28]^D[23]^D[21]^D[19]^D[18]^D[16]^D[14]^D[12]^D[8]^D[7]^D[6]^D[0];

CRC[1]＝D[63]^D[61]^D[60]^D[57]^D[56]^D[55]^D[52]^D[51]^D[48]^D[46]^D[45]^D[44]^D[43]^D[41]^D[39]^D[36]^D[34]^D[32]^D[30]^D[29]^D[28]^D[24]^D[23]^D[22]^D[21]^D[20]^D[18]^D[17]^D[16]^D[15]^D[14]^D[13]^D[12]^D[9]^D[6]^D[1]^D[0];

CRC[2]＝D[63]^D[62]^D[61]^D[60]^D[58]^D[57]^D[54]^D[50]^D[48]^D[47]^D[46]^D[44]^D[43]^D[42]^D[39]^D[37]^D[34]^D[33]^D[29]^D[28]^D[25]^D[24]^D[22]^D[17]^D[15]^D[13]^D[12]^D[10]^D[8]^D[6]^D[2]^D[1]^D[0];

CRC[3]＝D[63]^D[62]^D[61]^D[59]^D[58]^D[55]^D[51]^D[49]^D[48]^D[47]^D[45]^D[44]^D[43]^D[40]^D[38]^D[35]^D[34]^D[30]^D[29]^D[26]^D[25]^D[23]^D[18]^D[16]^D[14]^D[13]^D[11]^D[9]^D[7]^D[3]^D[2]^D[1];

CRC[4]＝D[63]^D[62]^D[60]^D[59]^D[56]^D[52]^D[50]^D[49]^D[48]^D[46]^D[45]^D[44]^D[41]^D[39]^D[36]^D[35]^D[31]^D[30]^D[27]^D[26]^D[24]^D[19]^D[17]^D[15]^D[14]^D[12]^D[10]^D[8]^D[4]^D[3]^D[2];

CRC[5]＝D[63]^D[61]^D[60]^D[57]^D[53]^D[51]^D[50]^D[49]^D[47]^D[46]^D[45]^D[42]^D[40]^D[37]^D[36]^D[32]^D[31]^D[28]^D[27]^D[25]^D[20]^D[18]^D[16]^D[15]^D[13]^D[11]^D[9]^D[5]^D[4]^D[3];

CRC[6]＝D[62]^D[61]^D[58]^D[54]^D[52]^D[51]^D[50]^D[48]^D[47]^D[46]^D[43]^D[41]^D[38]^D[37]^D[33]^D[32]^D[29]^D[28]^D[26]^D[21]^D[19]^D[17]^D[16]^D[14]^D[12]^D[10]^D[6]^D[5]^D[4];

CRC[7]＝D[63]^D[62]^D[59]^D[55]^D[53]^D[52]^D[51]^D[49]^D[48]^D[47]^D[44]^D[42]^D[39]^D[38]^D[34]^D[33]^D[30]^D[29]^D[27]^D[22]^D[20]^D[18]^D[17]^D[15]^D[13]^D[11]^D[7]^D[6]^D[5].

The above operations conform to the "≡" indication exclusive OR (XOR) operation.

The CRC generation formula is, for example, a CRC generation formula specified by the DDR5 protocol.

Fig. 6 shows a schematic diagram of an exemplary CRC check module. The CRC check module is, for example, the CRC check module described with reference to fig. 1.

Referring to fig. 6, an exemplary CRC check is to use a CRC, that is, a CRC is regenerated once by Data (i.e., data in fig. 6) in the same generation formula in a CRC generation module, and then the generated CRC (output by the CRC generation module) is compared with the read CRC (i.e., CRC in fig. 6), and if not consistent, a crc_error signal is output, reported to a control module, which in turn sends a retransmission request to a transmitting end, or directly reports the UE to the system.

Fig. 7 shows a schematic diagram of a CRC error correction module in accordance with at least one embodiment of the present disclosure. The CRC error correction module is, for example, or comprises, or is part of, CRC error correction module 320, CRC error correction module 410, and CRC error correction module 412.

Referring to fig. 7, the generated CRC (output by the CRC generation module) may be xored (Xor) with the read CRC (i.e., the CRC of fig. 6), resulting in Syndrome (syncrome):

the syndrome is 0, and the original data is directly output without errors;

if the syndrome is not 0, then the index lookup table is performed:

the size of the lookup table is 72 entries (entries), corresponding to 64+8 bits;

if the syndrome value (e.g., corresponding to the syndrome value above) is in the lookup table, the error is a correctable error, then the corresponding bit may be corrected, and the corrected data is output; if the value of the syndrome is not in the lookup table, the error is an uncorrectable error.

An exemplary look-up table is as follows:

As can be seen from the exemplary lookup table, the lookup table may include values for the syndromes (e.g., corresponding to the target syndrome values described above) and corresponding error locations (e.g., corresponding to the target error locations described above). If the value of the syndrome is in the first column of the table, i.e., hits, then the second column of the same row indicates the error location. In this manner, the determination that the error is a correctable error and the error location can be implemented through a lookup table.

If the syndrome value is not in the lookup table, i.e., does not hit, then the error is an uncorrectable error and the CRC_error signal may be output.

After determining the error location, the bits of the error location may be flipped to obtain error corrected data. For example, referring to FIG. 7, when the value of the syndrome is equal to the value of the lookup table, the corresponding bit is flipped, resulting in error corrected data CorData. For example, the value output by the= 0x7 block is 1 bit, and CorData [0] = Data [0] xor 1 if the value of the syndrome is 0x 07.

In an additional aspect, the error correction module may also correct the value of the 8-bit CRC code. However, in some embodiments, it is not necessary to output the value of the corrected CRC code (e.g., data corresponding to the cyclic redundancy check code in the corrected first data described above) to the outside, and it may be used only to determine whether the current error belongs to a correctable error or an uncorrectable error.

FIG. 8 illustrates a schematic diagram of using CRC error correction at a 32-bit DDR5 channel (channel) in accordance with at least one embodiment of the disclosure.

The DDR5 memory granule corresponding to the DDR5 channel shown in fig. 8 is 8, that is, x4 devices 0 to 7, and the distribution of the data bits and the CRC in each DDR5 memory granule may be the same as the distribution of the data bits and the CRC in the memory granule described with reference to fig. 5.

Referring to FIG. 8, a single transmission sent out by the 32-bit DDR5 channel includes 18 data bursts (burst 0 through burst 17), wherein burst 16 and burst 17 may be CRC codes. As shown in fig. 8, 8 x4 particles correspond to a DDR5 channel of 32 bits, and all 8 particles are data particles.

Of course, embodiments of the present disclosure are not limited thereto, and embodiments of the present disclosure may be applicable to all DDR5 memory banks, whether or not they have ECC functionality. For example, embodiments of the present disclosure may also be applicable to 36-bit DDR5 channels, 40-bit DDR5 channels, and the like. Illustratively, a 36-bit DDR5 channel may correspond to 8 x4 data particles, plus 1 x4 ECC particle, because the ECC particles also generate CRC, thus correcting errors that occur on the link. Similarly, the 40-bit DDR5 channel corresponds to 8 x4 data grains, and in addition to 2 x4 ECC grains, CRC correction can be performed, and 1bit error can be corrected in 18 data+CRC data sent by each grain.

All 64 bits of data sent every 4 DQs specified by the DDR5 protocol form a data packet, and an 8-bit CRC code is generated following the data using a CRC generation algorithm, thereby protecting data integrity. For example, the CRC error correction algorithm used in the example application scenario can correct any 1-bit error in the transmission of each x4 memory granule.

As shown in fig. 8, there is only a 1-bit error (shown by the shaded block) in the region corresponding to each x4 memory granule, so the case of the upper graph belongs to a correctable error, and the correctable error can be corrected. For example, during a data read process, the memory controller 402 may output corrected data directly from the memory controller without requiring the memory granule 404 to retransmit. For another example, during a data read process, the memory granule 404 may store the corrected data directly into the storage array 414 without requiring the memory controller 402 to retransmit.

Accordingly, one or more aspects of the above example should be viewed as describing a novel CRC error correction hardware architecture that uses a CRC generation algorithm defined in the DDR5 protocol to perform error correction via a CRC error correction module, thereby greatly improving the efficiency of link transmission.

Exemplary technical effects of the above example should be in a scene include at least one of:

1. errors on the DDR5 link can be corrected without requiring extra ECC memory particles through retransmission;

2. In each of the 6-bit data and 8-bit CRC codes consisting of 4DQ and BL 18 (Burst Length 18, i.e., one transmission corresponding to 18 data) transmissions, 1-bit errors can be corrected;

3. it is still possible to report the UE correctly when an uncorrectable error is encountered;

4. The method can correct data bits and correct the value of the CRC code, provide complete protection for the whole link and reduce the error rate of the link;

5. By direct error correction, bandwidth waste caused by retransmission can be reduced, and bandwidth efficiency can be improved.

Fig. 9 shows a schematic diagram of an electronic device 900 in accordance with at least one embodiment of the present disclosure.

As shown in fig. 9, the electronic device 900 includes at least one processing unit 920 and a memory 910. Memory 910 stores computer readable instructions and is communicatively coupled to processing unit 920. The processing unit 920 executes computer-readable instructions stored by the memory 910 to implement a data processing method in accordance with at least one embodiment of the present disclosure, as well as additional aspects thereof.

For example, the memory 910 and the processing unit 920 may communicate with each other directly or indirectly. For example, in some examples, as shown in fig. 9, the electronic device 900 may further include a system bus 930, and the memory 910 and the processing unit 920 may communicate with each other through the system bus 930, e.g., the processing unit 920 may access the memory 910 through the system bus 930. For example, in other examples, components such as memory 910 and processing unit 920 may communicate via a Network On Chip (NOC) connection.

For example, the processing unit 920 may control other components in the electronic device 900 to perform desired functions. The processing unit 920 may be a Central Processing Unit (CPU), a Tensor Processor (TPU), a Network Processor (NP), or a Graphics Processor (GPU) with data processing capability and/or program execution capability, or may be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, or the like.

For example, memory 910 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and/or nonvolatile memory. Volatile memory can include, for example, random Access Memory (RAM) and/or cache memory (cache) and the like. The non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, and the like.

For example, one or more computer-readable instructions may be stored on memory 910 and processing unit 920 may execute the computer-readable instructions to implement various functions. Various applications and various data, such as instruction processing code and various data used and/or generated by the applications, may also be stored in the computer readable storage medium.

For example, some of the computer instructions stored by memory 910, when executed by processing unit 920, may perform one or more steps in accordance with the data processing methods described above.

For example, as shown in fig. 9, the electronic apparatus 900 may further include an input interface 940 that allows an external device to communicate with the electronic apparatus 900. For example, input interface 940 may be used to receive instructions from an external computer device, from a user, and so forth. The electronic apparatus 900 may also include an output interface 950 that interconnects the electronic apparatus 900 and one or more external devices. For example, the electronic device 900 may be through the output interface 950, etc.

It should be noted that, the electronic device 900 according to at least one embodiment of the present disclosure is exemplary, and not limiting, and the electronic device 900 may further include other conventional components or structures according to practical application requirements, for example, to implement the necessary functions of the electronic device, and those skilled in the art may set other conventional components or structures according to specific application scenarios, which the embodiments of the present disclosure are not limited to.

At least one embodiment of the present disclosure also provides a processor, such as an SMT processor, that includes an electronic device according to at least one embodiment of the present disclosure. The maximum number of threads supportable by an SMT processor may be, for example, 2,4, 8, etc., may be a single-core or multi-core processor, for example, a processor core may employ a microarchitecture of X86, ARM, RISC-V, etc., may include one or more levels of cache, and embodiments of the present disclosure are not limited in this respect.

At least one embodiment of the present disclosure also provides a computer-readable storage medium. Fig. 10 shows a schematic diagram of a computer-readable storage medium 1000 in accordance with at least one embodiment of the present disclosure.

For example, as shown in fig. 10, the computer-readable storage medium 1000 stores computer-readable instructions 1010, which when executed by a computer (including a processor) can implement a data processing method in accordance with at least one embodiment of the present disclosure, as well as additional aspects thereof.

For example, one or more computer-readable instructions may be stored on computer-readable storage medium 1000. Some computer readable instructions stored on computer readable storage medium 1000 may be, for example, instructions for implementing one or more steps of the data processing methods described above.

For example, a computer-readable storage medium may include a memory component of a tablet computer, a hard disk of a personal computer, random Access Memory (RAM), read Only Memory (ROM), erasable Programmable Read Only Memory (EPROM), compact disc read only memory (CD-ROM), flash memory, or any combination of the foregoing, as well as other suitable storage media. For example, computer-readable storage medium 1000 may include memory 910 in electronic device 900 described above.

At least some embodiments of the present disclosure also provide an electronic device. Fig. 11 illustrates a schematic diagram of another electronic device 1100 in accordance with at least one embodiment of the present disclosure.

An electronic device according to at least one embodiment of the present disclosure may be implemented as, but is not limited to, a mobile terminal such as a mobile phone, a notebook computer, a digital broadcast receiver, a PDA (personal digital assistant), a PAD (tablet computer), a PMP (portable multimedia player), an in-vehicle terminal (e.g., an in-vehicle navigation terminal), etc., and a fixed terminal such as a digital TV, a desktop computer, etc.

The electronic device 1100 illustrated in fig. 11 is merely an example and should not be construed as limiting the functionality and scope of use of embodiments of the present disclosure in any way.

For example, as shown in fig. 11, in some examples, an electronic device 1100 includes a processor 1101, which may include a processor (e.g., an SMT processor) of any of the above embodiments, that may perform various suitable actions and processes according to a program stored in a Read Only Memory (ROM) 1102 or a program loaded from a storage device 1108 into a Random Access Memory (RAM) 1103. In the RAM 1103, various programs and data required for the operation of the computer system are also stored. The processor 1101, ROM 1102, and RAM 1103 are connected thereto by a bus 1104. An input/output (I/O) interface 1105 is also connected to bus 1104.

For example, the following components may be connected to the I/O interface 1105: input devices 1106 including, for example, a touch screen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, and the like; an output device 1107 including a Liquid Crystal Display (LCD), speaker, vibrator, and the like; storage 1108, including for example, magnetic tape, hard disk, etc.; for example, communication device 1109 may also include a network interface card such as a LAN card, modem, or the like. The communication device 1109 may allow the electronic device 1100 to perform wireless or wired communication with other apparatuses to exchange data, performing communication processing via a network such as the internet. The drive 1110 is also connected to the I/O interface 1105 as needed. Removable media 1111, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like, is installed as needed in drive 1110, so that a computer program read therefrom is installed as needed in storage 1108. While fig. 11 illustrates an electronic device 1100 that includes various devices, it is to be understood that not all illustrated devices are required to be implemented or included. More or fewer devices may be implemented or included instead.

For example, the electronic device 1100 may further include a peripheral interface (not shown), and the like. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning (lighting) interface, etc. The communication device 1109 may communicate with a network, such as the internet, an intranet, and/or a wireless network such as a cellular telephone network, a wireless Local Area Network (LAN), and/or a Metropolitan Area Network (MAN), and other devices via wireless communication. The wireless communication may use any of a variety of communication standards, protocols, and technologies including, but not limited to, global System for Mobile communications (GSM), enhanced Data GSM Environment (EDGE), wideband code division multiple Access (W-CDMA), code Division Multiple Access (CDMA), time Division Multiple Access (TDMA), bluetooth, wi-Fi (e.g., based on the IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and/or IEEE 802.11n standards), voice over Internet protocol (VoIP), wi-MAX, protocols for email, instant messaging, and/or Short Message Service (SMS), or any other suitable communication protocol.

For the present disclosure, in addition to the above exemplary descriptions, the following points are required:

(1) The drawings of the embodiments of the present disclosure relate only to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

(2) The embodiments of the present disclosure and features in the embodiments may be combined with each other to arrive at a new embodiment without conflict.

The foregoing is merely exemplary embodiments of the present disclosure and is not intended to limit the scope of the disclosure, which is defined by the appended claims.

Claims

1. A data processing method, comprising:

receiving first data and a first cyclic redundancy check code of the first data;

Performing a cyclic redundancy check operation on the first data to generate a second cyclic redundancy check code;

generating a syndrome based on the first cyclic redundancy check code and the second cyclic redundancy check code; and

Error correction is performed on the first data based on the syndrome.

2. The data processing method according to claim 1, wherein the error correction of the first data based on the syndrome comprises:

determining whether there is an error in the first data based on the syndrome;

In response to determining that the first data has an error, the first data is corrected.

3. The data processing method according to claim 2, wherein, in response to determining that the first data has an error, correcting the error of the first data comprises:

In response to determining that an error exists in the first data, determining whether the error is a correctable error based on a syndrome value of the syndrome; and

In response to the error being a correctable error, an error location of the error is determined, and error correction is performed on data at the error location.

4. The data processing method according to claim 2, wherein generating a syndrome based on the first cyclic redundancy check code and the second cyclic redundancy check code comprises:

performing an XOR operation on the first cyclic redundancy check code and the second cyclic redundancy check code to generate the syndrome,

Determining whether there is an error in the first data based on the syndrome includes:

In response to the syndrome being 0, determining that there is no error in the first data; and

In response to the syndrome being not 0, it is determined that an error exists in the first data.

5. The data processing method according to claim 3, wherein determining whether the error is a correctable error and determining the error position of the error based on the syndrome value of the syndrome comprises:

Whether the error is a correctable error and the error position of the error are determined by using the syndrome value and a lookup table, wherein the lookup table records a target syndrome value indicating that the error is a correctable error and a corresponding target error position.

6. The data processing method according to claim 5, wherein determining whether the error is a correctable error and determining the error position of the error by using the syndrome value and a lookup table comprises:

Indexing a lookup table based on the syndrome value to determine whether the syndrome value hits the target syndrome value; and

In response to a hit, determining that the error is a correctable error, and determining a target error position corresponding to the syndrome value in the lookup table as the error position; or

In response to a miss, the error is determined to be an uncorrectable error.

7. The data processing method according to claim 3, further comprising:

In response to the error being an uncorrectable error, an error signal is outputted.

8. The data processing method according to claim 3, wherein, in response to the error being a correctable error, correcting the data at the error location comprises:

In response to the error being a correctable error, the bit at the error position is flipped to obtain first data after error correction.

9. The data processing method according to claim 2, further comprising:

In response to determining that the first data does not have errors, the first data is used as error-corrected first data.

10. The data processing method according to claim 1, further comprising:

Only the data corresponding to the data code in the error-corrected first data is output, and the data corresponding to the cyclic redundancy check code in the error-corrected first data is not output.

11. The data processing method according to any one of claims 1 to 10, wherein the data processing method is applied to a fifth generation double data rate memory standard, and the cyclic redundancy check operation comprises utilizing a cyclic redundancy check generation algorithm defined in a protocol of the fifth generation double data rate memory standard.

12. The data processing method according to any one of claims 1 to 10, wherein the first data and the first cyclic redundancy check code are received via transmission of a link, and the first cyclic redundancy check code before transmission is generated by performing a cyclic redundancy check operation on the first data before transmission.

13. A data processing device, comprising:

The cyclic redundancy check generation module is configured as follows:

receiving first data;

Performing a cyclic redundancy check operation on the first data to generate a second cyclic redundancy check code; and

The cyclic redundancy check error correction module is configured as follows:

Receiving a first cyclic redundancy check code of the first data;

Error correction is performed on the first data based on the syndrome.

14. The data processing device according to claim 13, wherein, in order to perform error correction on the first data based on the syndrome, the cyclic redundancy check error correction module is further configured to:

determining whether there is an error in the first data based on the syndrome;

15. The data processing device according to claim 14, wherein, in order to correct errors in the first data in response to determining that the first data has errors, the cyclic redundancy check error correction module is further configured to:

16. The data processing device according to claim 15, wherein, in order to determine whether the error is a correctable error and determine the error position of the error based on the syndrome value of the syndrome, the cyclic redundancy check error correction module is further configured to:

17. The data processing device according to claim 15, wherein, in order to correct the data at the error location in response to the error being a correctable error, the cyclic redundancy check error correction module is further configured to:

18. The data processing device according to claim 14, wherein, in order to generate a syndrome based on the first cyclic redundancy check code and the second cyclic redundancy check code, the cyclic redundancy check error correction module is further configured to:

In order to determine whether the first data has an error based on the syndrome, the cyclic redundancy check error correction module is further configured to:

19. An electronic device comprising at least one processing unit and a memory; wherein:

The memory stores computer-readable instructions and is communicatively connected to the at least one processing unit;

The at least one processing unit is configured to execute the computer-readable instructions stored in the memory to implement the data processing method according to any one of claims 1 to 12.

20. A computer-readable storage medium, wherein the computer-readable storage medium stores computer-readable instructions, and when a processor executes the computer-readable instructions, the data processing method according to any one of claims 1 to 12 is implemented.