CN118914826B - Differential Crosstalk Noise Coupler, PCB Board and SerDes Test System - Google Patents
Differential Crosstalk Noise Coupler, PCB Board and SerDes Test System Download PDFInfo
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- CN118914826B CN118914826B CN202411405592.5A CN202411405592A CN118914826B CN 118914826 B CN118914826 B CN 118914826B CN 202411405592 A CN202411405592 A CN 202411405592A CN 118914826 B CN118914826 B CN 118914826B
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- 238000010168 coupling process Methods 0.000 description 12
- 238000005859 coupling reaction Methods 0.000 description 12
- 230000003071 parasitic effect Effects 0.000 description 10
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
- G01R31/2863—Contacting devices, e.g. sockets, burn-in boards or mounting fixtures
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
- G01R31/2868—Complete testing stations; systems; procedures; software aspects
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
- G01R31/2879—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads
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Abstract
The differential crosstalk noise coupler comprises a victim line, an attack line and a second attack line, wherein the victim line comprises a first attack sub-line and a second attack sub-line, the first attack sub-line and the first victim sub-line are coupled to form a first differential signal line pair, and the second attack sub-line and the second victim sub-line are coupled to form a second differential signal line pair. The technical scheme disclosed by the invention is beneficial to maintaining the impedance of the victim line to be basically unchanged, and the impedance of the victim line can not be influenced under the condition that larger noise is applied through the attack line, so that the test of the crosstalk tolerance boundary of the victim line is facilitated, and the reliability of the crosstalk test of the differential signal line is facilitated to be improved.
Description
Technical Field
The present disclosure relates to the field of integrated circuit testing technologies, and in particular, to a differential crosstalk noise coupler, PCB board, and SerDes (Serializer/Deserializer) testing system.
Background
SI (SIGNAL INTEGRITY ) testing in integrated circuits is a test means to ensure that signals in electronic systems maintain their integrity and quality during transmission. SI testing is particularly important for high-speed electronic devices because the high-speed signals may be affected by various factors such as noise, attenuation, distortion, reflection, crosstalk, etc. during transmission, which may result in a decrease in signal quality and thus affect the performance of the overall system.
The crosstalk test of differential signal lines is an important test item in SI test, which is to introduce crosstalk through an attack line (Aggressor Line, which may also be called a victim line) in the vicinity of the differential signal line as a victim line (VICTIM LINE) and perform the crosstalk test. However, in the manner of testing in which the attack line is arranged near the differential signal line, there is a large difference between the environment of the differential signal line and the environment of the differential signal line in the actual application circuit, so that the result of the crosstalk test is difficult to reflect the crosstalk condition of the differential signal line in the actual application circuit.
Therefore, the crosstalk test mode of the differential signal lines is still further improved.
Disclosure of Invention
In view of the above, the present disclosure provides a differential crosstalk noise coupler, a PCB board, and a SerDes test system to help improve the results of differential signal line crosstalk testing.
According to an aspect of the disclosed embodiments, there is provided a differential crosstalk noise coupler comprising:
a victim line comprising a first victim sub-line and a second victim sub-line, the first victim sub-line and the second victim sub-line being single ended wires;
An attack line comprising a first attack sub-line and a second attack sub-line, the first attack sub-line and the first victim sub-line being coupled to form a first differential signal line pair, the second attack sub-line and the second victim sub-line being coupled to form a second differential signal line pair;
A victim differential lead pair comprising a first victim sub-lead and a second victim sub-lead, wherein the first victim sub-lead is connected with the first victim sub-line and the second victim sub-lead is connected with the second victim sub-line;
The attack differential lead pair comprises a first attack sub-lead and a second attack sub-lead, wherein the first attack sub-lead is connected with the first attack sub-line, and the second attack sub-lead is connected with the second attack sub-line;
Wherein the victim differential lead pair and the victim line are positioned at the same inner layer in the PCB, the attack differential lead pair and the attack line are positioned at different inner layers in the PCB; or the victim differential lead pair and the victim line are positioned on different inner layers in the PCB, and the attack differential lead pair and the attack line are positioned on the same inner layer in the PCB.
In one possible implementation, the first victim sub-line, the second victim sub-line, the first aggressor sub-line, and the second aggressor sub-line all extend in a straight line.
In one possible implementation, the victim line and the aggressor line are located on the same inner layer in the PCB board.
In one possible implementation, in a case where the victim differential lead pair and the victim line are located in the same inner layer in the PCB board, the aggressor differential lead pair and the aggressor line are located in different inner layers in the PCB board:
The victim differential lead pair is connected with the victim line through a victim transition line, and the victim transition line and the victim line are positioned on the same inner layer in the PCB;
The attack differential lead pair is connected with the attack line through an attack transition through hole and an attack transition line, wherein the attack transition line and the attack line are positioned on the same inner layer in the PCB, the attack transition line is connected with the attack line, and the attack transition through hole is connected between the attack differential lead pair and the attack transition line.
In one possible implementation, in a case where the victim differential lead pair and the victim line are located in different inner layers in the PCB board, the aggressor differential lead pair and the aggressor line are located in the same inner layer in the PCB board:
the attack differential lead pair is connected with the attack line through an attack transition line, and the attack transition line and the attack line are positioned at the same inner layer in the PCB;
The victim differential lead pair is connected with the victim line through a victim transition through hole and a victim transition line, wherein the victim transition line and the victim line are positioned on the same inner layer in the PCB, the victim transition line is connected with the victim line, and the victim transition through hole is connected between the victim differential lead pair and the victim transition line.
In one possible embodiment, the method further comprises:
a victim line SMA interface connected to the victim differential pair of leads;
and the attack line SMA interface is connected to the attack differential lead pair.
In one possible implementation, the victim transition line comprises a first victim transition sub-line and a second victim transition sub-line, the attack transition via comprises a first attack transition sub-via and a second attack transition sub-via, the attack transition line comprises a first attack transition sub-line and a second attack transition sub-line, wherein,
The first victim sub-line is connected with the first victim sub-line through the first victim transition sub-line, the second victim sub-line is connected with the second victim sub-line through the second victim transition sub-line, and the first victim transition sub-line and the second victim transition sub-line are positioned on the same inner layer in the PCB board as the victim line;
The first attack sub-lead is connected with the first attack sub-line through the first attack transition sub-through hole and the first attack transition sub-line, the second attack sub-lead is connected with the second attack sub-line through the second attack transition sub-through hole and the second attack transition sub-line, wherein the first attack transition sub-line and the second attack transition sub-line are positioned on the same inner layer in the PCB board with the attack line, the first attack transition sub-line is connected with the first attack sub-line, the second attack transition sub-line is connected with the second attack sub-line, the first attack transition sub-through hole is connected between the first attack sub-lead and the first attack transition sub-line, and the second attack transition sub-through hole is connected between the second attack sub-lead and the second attack transition sub-line.
In one possible implementation, the attack transition line includes a first attack transition sub-line and a second attack transition sub-line, the victim transition via includes a first victim transition sub-via and a second victim transition sub-via, the victim transition line includes a first victim transition sub-line and a second victim transition sub-line, wherein,
The first attack sub-lead is connected with the first attack sub-line through the first attack transition sub-line, the second attack sub-lead is connected with the second attack sub-line through the second attack transition sub-line, and the first attack transition sub-line, the second attack transition sub-line and the attack line are positioned on the same inner layer in the PCB;
the first victim sub-line is connected with the first victim sub-line through the first victim transition sub-via and the first victim transition sub-line, the second victim sub-line is connected with the second victim sub-line through the second victim transition sub-via and the second victim transition sub-line, wherein the first victim transition sub-line and the second victim transition sub-line are located at the same inner layer in the PCB board as the victim line, and the first victim transition sub-line is connected with the first victim sub-line, the second victim transition sub-line is connected with the second victim sub-line, the first victim transition sub-via is connected between the first victim sub-line and the first victim transition sub-line, and the second victim transition sub-via is connected between the second victim sub-line and the second victim transition sub-line.
According to another aspect of the disclosed embodiments, a PCB board is provided, employing the differential crosstalk noise coupler as described in any one of the above.
According to another aspect of embodiments of the present disclosure, there is provided a SerDes test system employing a differential crosstalk noise coupler as described in any one of the above.
As can be seen from the above-mentioned scheme, in the differential crosstalk noise coupler, PCB board and SerDes test system according to the embodiment of the present disclosure, since the first attack sub-line and the first victim sub-line are coupled to form the first differential signal line pair, and further from the perspective of the first victim sub-line, the first victim sub-line still belongs to one single-end line among a pair of differential signal lines, and only another single-end line (first attack sub-line) among the differential signal lines (first differential signal line pair) is near the first victim sub-line, such a structure will not cause a change in parasitic capacitance of the first victim sub-line under ideal conditions, and further the impedance of the first victim sub-line under ideal conditions will not change. In the same way, since the second attack sub-line and the second victim sub-line are coupled to form a second differential signal line pair, the second victim sub-line still belongs to one single-ended line among a pair of differential signal lines from the perspective of the second victim sub-line, and only the other single-ended line (the second attack sub-line) among the differential signal lines (the second differential signal line pair) is near the second victim sub-line, the structure does not cause the change of the parasitic capacitance of the second victim sub-line under the ideal condition, and the impedance of the second victim sub-line under the ideal condition is not changed. Thus, from the perspective of the victim line consisting of the first victim sub-line and the second victim sub-line, the overall parasitic capacitance of the victim line is not changed in an ideal case, and the impedance is not changed in an ideal case. Therefore, compared with the related art, the differential crosstalk noise coupler, the PCB board and the SerDes test system of the present disclosure help to maintain the impedance of the victim line to be kept substantially unchanged, and also cannot influence the impedance of the victim line under the condition that larger noise is applied through the aggressor line, so that the differential crosstalk noise coupler, the PCB board and the SerDes test system of the present disclosure help to test the crosstalk tolerance boundary of the victim line, and help to improve the reliability of the differential signal line crosstalk test.
Drawings
FIG. 1 is a schematic diagram of a wiring structure used for crosstalk testing of differential signal lines in the related art;
fig. 2 is a schematic diagram of a differential crosstalk noise coupler according to an exemplary embodiment;
FIG. 3A is a partial block diagram of one connection area of the victim differential lead pair, the aggressor differential lead pair, and the victim and aggressor lines of FIG. 2;
FIG. 3B is a partial block diagram of the victim differential lead pair, the aggressor differential lead pair, and another connection region of the victim and aggressor lines of FIG. 2;
fig. 4 is another structural schematic diagram of a differential crosstalk noise coupler shown according to an exemplary embodiment;
FIG. 5A is a partial block diagram of one connection area of the victim differential lead pair, the aggressor differential lead pair, and the victim and aggressor lines of FIG. 4;
FIG. 5B is a partial block diagram of the victim differential lead pair, the aggressor differential lead pair, and another connection region of the victim and aggressor lines of FIG. 4;
fig. 6 is a schematic diagram of the overall structure of a differential crosstalk noise coupler shown according to an exemplary embodiment;
FIG. 7 is a schematic diagram of a modeling structure of a simulation segment in a differential crosstalk noise coupler according to an exemplary embodiment;
FIG. 8 is a schematic diagram of an impedance simulation curve for the structure shown in FIG. 7;
fig. 9 is a schematic diagram of a crosstalk simulation graph for the structure shown in fig. 7.
Detailed Description
In order to make the objects, technical solutions and advantages of the present disclosure more apparent, the present disclosure will be further described in detail below with reference to the accompanying drawings and examples.
It should be noted that the terms "first," "second," and the like in the description and claims of the present disclosure and in the foregoing figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.
Fig. 1 is a schematic diagram of a wiring structure used for crosstalk testing on differential signal lines in the related art, as shown in fig. 1, in the related art, noise is coupled into a victim line 1 in a manner that an aggressor line 2 is close to and parallel to the victim line 1 when the differential signal lines are subjected to crosstalk testing. In the related art, a distance between the attack line 2 and the victim line 1 is generally controlled to be 2 to 3 times line width for coupling noise. In this scheme, if the coupling capability between the attack line 2 and the victim line 1 needs to be increased, the attack line 2 and the victim line 1 need to be close as much as possible, for example, the interval between them is reduced to about 1 time of line width, however, although the coupling capability can be enhanced, this approach brings new problems, the approach of the attack line 2 and the victim line 1 can increase the parasitic capacitance of the victim line 1, the closer the attack line 2 is to the victim line 1, the lower the impedance of the victim line 1 is, the problem that whether the error rate of the transmission data in the victim line 1 is high due to noise or the lower impedance is caused by the test error rate of the transmission data in the victim line 1 is high in the crosstalk test process is difficult to distinguish, and the contribution of the attack line 2 and the victim line 1 to the SerDes test system cannot be decoupled, so that the reliability of the test result is insufficient is caused. Therefore, the attack line 2 and the victim line 1 cannot be close to each other as much as possible, so that the distance between the attack line 2 and the victim line 1 is controlled to be 2 to 3 times the line width, and this way, too, cannot increase the crosstalk into the SerDes test system, and thus the crosstalk tolerance boundary of the victim line 1 is difficult to be detected by the test.
In view of this, the embodiments of the present disclosure provide a differential crosstalk noise coupler, a PCB board, and a SerDes test system, so that the impedance of a victim line in a test is equivalent to the impedance of a differential signal line in a practical application circuit, and in this case, larger crosstalk can be coupled from an attack line to a victim line, thereby helping the crosstalk test result of the victim line to be closer to its real crosstalk tolerance boundary, so as to help to improve the result of the differential signal line crosstalk test.
Fig. 2 is a schematic structural diagram of a differential crosstalk noise coupler according to an exemplary embodiment, where the differential crosstalk noise coupler according to the embodiment of the present disclosure mainly includes a victim line 1 and an aggressor line 2, specifically, as shown in fig. 2, the victim line 1 includes a first victim sub-line 101 and a second victim sub-line 102, the first victim sub-line 101 and the second victim sub-line 102 are single-ended wires (i.e., from the perspective of the victim line 1, the first victim sub-line 101 and the second victim sub-line 102 are pulled by a distance from each other, so that the first victim sub-line 101 and the second victim sub-line 102 are each single-ended wires), the aggressor line 2 includes a first aggressor sub-line 201 and a second aggressor sub-line 202, the first aggressor sub-line 201 is coupled with the first victim sub-line 101 into a first differential signal line pair 11, and the second aggressor sub-line 202 is coupled with the second victim sub-line 102 into a second differential signal line pair 21.
Based on the structure shown in fig. 2, from the perspective of the attack line 2, the distance between the first attack sub-line 201 and the second attack sub-line 202 is also increased, so that the first attack sub-line 201 and the second attack sub-line 202 are also single-ended wires.
In the exemplary embodiment, noise is coupled from the aggressor wire 2 to the victim wire 1, the first aggressor sub-wire 201 couples noise to the first victim sub-wire 101 in the first differential signal wire pair 11, and the second aggressor sub-wire 202 couples noise to the second victim sub-wire 102 in the second differential signal wire pair 21.
In the differential crosstalk noise coupler of the embodiment of the present disclosure, since the first attack sub-line 201 is coupled to the first victim sub-line 101 to form the first differential signal line pair 11, and further from the perspective of the first victim sub-line 101, the first victim sub-line 101 still belongs to one single-ended line among a pair of differential signal lines, and only the other single-ended line (the first attack sub-line 201) among the differential signal lines (the first differential signal line pair 11) is near the first victim sub-line 101, the structure will not cause a change in parasitic capacitance of the first victim sub-line 101 under ideal conditions, and thus the impedance of the first victim sub-line 101 under ideal conditions will not change. Similarly, since the second attack sub-line 202 is coupled to the second victim sub-line 102 to form the second differential signal line pair 21, and thus from the perspective of the second victim sub-line 102, the second victim sub-line 102 still belongs to one single-ended line of the pair of differential signal lines, and only the other single-ended line (the second attack sub-line 202) of the differential signal lines (the second differential signal line pair 21) is near the second victim sub-line 102, the structure will not ideally cause the parasitic capacitance of the second victim sub-line 102 to change, and thus the impedance of the second victim sub-line 102 will not ideally change. Therefore, from the perspective of the victim line 1 composed of the first victim sub-line 101 and the second victim sub-line 102, the parasitic capacitance of the whole of the victim line 1 is not changed in an ideal case, and the impedance is not changed in an ideal case. Therefore, compared to the related art, the differential crosstalk noise coupler of the embodiment of the present disclosure helps to maintain the impedance of the victim line 1 substantially unchanged, and does not affect the impedance of the victim line 1 even in the case of applying large noise through the aggressor line 2, and thus helps to test the crosstalk tolerance boundary of the victim line 1 and to improve the reliability of the differential signal line crosstalk test when the differential crosstalk noise coupler of the embodiment of the present disclosure is applied to a SerDes test system.
Since the differential signal lines may raise parasitic capacitance due to other wirings in the vicinity thereof, and thus cause a problem of impedance reduction, in order to avoid such a problem as much as possible, in the exemplary embodiment, the distance between the first differential signal line pair 11 and the second differential signal line pair 21 is a distance capable of ensuring that the parasitic capacitance of the first differential signal line pair 11 and the second differential signal line pair 21 due to the distance therebetween is negligible.
In order to obtain a better crosstalk test result, it is necessary to ensure that the lengths of the victim line 1 and the aggressor line 2 are equal, so that the crosstalk noise obtained by the first victim sub-line 101 from the first aggressor sub-line 201 and the crosstalk noise obtained by the second victim sub-line 102 from the second aggressor sub-line 202 are correlated, and based on this, in the exemplary embodiment, the first victim sub-line 101, the second victim sub-line 102, the first aggressor sub-line 201 and the second aggressor sub-line 202 all extend in a straight line. Based on the straight-line extending structure, the strict control of the length design of the victim line 1 and the aggressor line 2 is facilitated.
As shown in fig. 2, in order to reduce design and manufacturing difficulties for the differential crosstalk noise coupler to be compact, in the illustrated embodiment, the victim line 1 and the aggressor line 2 are located on the same inner layer in the PCB board. In this way, the first victim sub-line 101, the second victim sub-line 102, the first attack sub-line 201 and the second attack sub-line 202 are easily routed in the same inner layer of the PCB board.
In the differential crosstalk noise coupler of the embodiment of the present disclosure, the first attack sub-line 201 is coupled with the first victim sub-line 101 to form the first differential signal line pair 11, and the second attack sub-line 202 is coupled with the second victim sub-line 102 to form the second differential signal line pair 21, however, from the perspective of the victim line 1, the first victim sub-line 101 and the second victim sub-line 102 belong to two single-ended lines in the victim line 1, and from the perspective of the attack line 2, the first attack sub-line 201 and the second attack sub-line 202 belong to two single-ended lines in the attack line 2. In the circuit design, both the victim line 1 and the aggressor line 2 are required to be present in pairs and run as differential signal lines, that is, the victim line 1 and the aggressor line 2 are required to be present in pairs and run, respectively, only so that the transmission of differential signals can be ensured. Thus, with continued reference to fig. 2, in an exemplary embodiment, the differential crosstalk noise coupler of the disclosed embodiments further comprises a victim differential lead pair 12 and an aggressor differential lead pair 22, in addition to the first victim sub-line 101, the second victim sub-line 102, the first aggressor sub-line 201, and the second aggressor sub-line 202 described above. Wherein the victim differential lead pair 12 comprises a first victim sub-lead 121 and a second victim sub-lead 122, wherein the first victim sub-lead 121 is connected to the first victim sub-line 101 and the second victim sub-lead 122 is connected to the second victim sub-line 102. The attack differential lead pair 22 includes a first attack sub-lead 221 and a second attack sub-lead 222, wherein the first attack sub-lead 221 is connected to the first attack sub-line 201 and the second attack sub-lead 222 is connected to the second attack sub-line 202. Wherein, the victim differential lead pair 12 is used as the extension of the victim line 1, the attack differential lead pair 22 is used as the extension of the attack line 2, and the paired appearance and wiring of the two differential signal lines of the victim line 1 and the attack line 2 are realized.
As shown in fig. 2, because the victim line 1 and the aggressor line 2 are located on the same inner layer in the PCB board, and the first aggressor sub-line 201 is coupled with the first victim sub-line 101 into a first differential signal line pair 11, and the second aggressor sub-line 202 is coupled with the second victim sub-line 102 into a second differential signal line pair 21, based on which case if the victim differential lead pair 12 and the aggressor differential lead pair 22, which are connected to the victim line 1 and the aggressor line 2, respectively, are also located on the same inner layer at the same time, a situation of crossing between the victim differential lead pair 12 and the aggressor differential lead pair 22 will be faced, which will result in shorting of the two differential signal lines. To avoid this, in the illustrative embodiment, the victim differential lead pair 12 is located at the same inner layer in the PCB board as the victim line 1, and the aggressor differential lead pair 22 is located at a different inner layer in the PCB board than the aggressor line 2, such as shown in fig. 2. Or in other exemplary embodiments, the victim differential lead pair 12 and the victim line 1 are located on different inner layers in the PCB board, and the aggressor differential lead pair 22 and the aggressor line 2 are located on the same inner layer in the PCB board, specifically, see the circuit structure implemented as shown in fig. 4. Or in other exemplary embodiments, the victim differential lead pair 12 and the victim line 1 are located at different inner layers in the PCB board, the aggressor differential lead pair 22 and the aggressor line 2 are located at different inner layers in the PCB board, and the victim differential lead pair 12 and the aggressor differential lead pair 22 are also located at different inner layers in the PCB board, wherein the traces between the different inner layers may be connected by corresponding vias.
Fig. 3A shows a partial structure diagram of one connection region of the victim differential lead pair 12, the aggressor differential lead pair 22 and the victim line 1 and the aggressor line 2 in fig. 2, and fig. 3B shows a partial structure diagram of the other connection region of the victim differential lead pair 12, the aggressor differential lead pair 22 and the victim line 1 and the aggressor line 2 in fig. 2, as shown in fig. 3A, 3B in combination with fig. 2, in the case that the victim differential lead pair 12 and the victim line 1 are located at the same inner layer in the PCB board, the aggressor differential lead pair 22 and the aggressor line 2 are located at different inner layers in the PCB board, the victim differential lead pair 12 and the victim line 1 are connected through the victim transition line 13, the victim transition line 13 and the victim line 1 are located at the same inner layer in the PCB board, the aggressor differential lead pair 22 and the aggressor line 2 are connected through the aggressor transition via 24 and the aggressor transition line 23, wherein the aggressor line 23 and the aggressor transition line 23 are located at the same inner layer in the PCB board, and the differential pair 24 and the aggressor transition line 23 are connected between the victim transition line 1 and the victim line 1.
Specifically, the victim transition line 13 includes a first victim transition sub-line 131 and a second victim transition sub-line 132, the attack transition via 24 includes a first attack transition sub-via 241 and a second attack transition sub-via 242, and the attack transition line 23 includes a first attack transition sub-line 231 and a second attack transition sub-line 232. The first victim sub-wire 121 is connected with the first victim sub-wire 101 through a first victim transition sub-wire 131, the second victim sub-wire 122 is connected with the second victim sub-wire 102 through a second victim transition sub-wire 132, the first victim transition sub-wire 131 and the second victim transition sub-wire 132 are positioned on the same inner layer of the PCB board as the victim wire 1, the first attack sub-wire 221 is connected with the first attack sub-wire 201 through a first attack transition sub-through hole 241 and a first attack transition sub-wire 231, and the second attack sub-wire 222 is connected with the second attack sub-wire 202 through a second attack transition sub-through hole 242 and a second attack transition sub-wire 232. The first attack transition sub-line 231 and the second attack transition sub-line 232 are located at the same inner layer in the PCB board as the attack line 2, the first attack transition sub-line 231 is connected to the first attack sub-line 201, the second attack transition sub-line 232 is connected to the second attack sub-line 202, the first attack transition sub-via 241 is connected between the first attack sub-line 221 and the first attack transition sub-line 231, and the second attack transition sub-via 242 is connected between the second attack sub-line 222 and the second attack transition sub-line 232.
As can be seen from fig. 2, 3A and 3B, the first victim transition sub-line 131 and the second victim transition sub-line 132 are not in parallel relation, but the impedance of a single-ended line in the differential signal line is affected by the adjacent other parallel single-ended line in the differential signal line, so that in the case that the widths of the first victim sub-line 121, the first victim transition sub-line 131 and the first victim sub-line 101 are equal, the impedance of the first victim transition sub-line 131 is increased, and therefore, in order to enable the impedance of the first victim transition sub-line 131 to be the same as or to be similar to the impedance of the first victim sub-line 101 and the first victim sub-line 121, preferably, the width of the first victim transition sub-line 131 needs to be larger than the width of the first victim sub-line 101 and the first victim sub-line 121, and the width of the second victim transition sub-line 132 is identical, and the width of the first victim transition sub-line 131 and the second victim transition sub-line 132 can be adaptively set according to the actual application scenario.
Similar to the victim transition line 13, the same situation is also the case of the attack transition line 23, however, the crosstalk test is performed on the victim line 1, and the influence of the width of the attack transition line 23 on the crosstalk test of the victim line 1 may not be great, but in order to facilitate the crosstalk test result to be more ideal, it is preferable that the width of the first attack transition sub-line 231 is larger than the widths of the first attack sub-line 201 and the first attack sub-line 221, the second attack transition sub-line 232 is the same, and in particular, the widths of the first attack transition sub-line 231 and the second attack transition sub-line 232 may be adaptively set according to the actual application scenario. In addition, because the first attack transition sub-through hole 241 is different from the first attack sub-lead 221 in structure, in order to facilitate the ideal tamper test result, the parameters related to the first attack transition sub-through hole 241 may be adaptively set according to the actual application scenario, and the second attack transition sub-through hole 242 is the same.
In the exemplary embodiment, the attack differential lead pair 22 and the attack line 2 may be respectively located in two adjacent inner layers in the PCB board, or may be located in two non-adjacent inner layers in the PCB board.
In the case where the victim differential lead pair 12 and the victim line 1 are located at different inner layers in the PCB board and the aggressor differential lead pair 22 and the aggressor line 2 are located at the same inner layer in the PCB board, the connection manner of the aggressor differential lead pair 22 and the victim differential lead pair 12 opposite to fig. 2 may be adopted. Fig. 4 is another schematic diagram of a differential crosstalk noise coupler according to an exemplary embodiment, and the embodiment shown in fig. 4 only exchanges the aggressor wires 2 and the victim wires 1 with each other, and thus the associated aggressor differential lead pairs 22 and victim differential lead pairs 12, as compared to fig. 2. Fig. 5A shows a partial structure diagram of one connection region of the differential lead pair 12, the differential lead pair 22 and the victim line 1 and the attack line 2 in fig. 4, and fig. 5B shows a partial structure diagram of the other connection region of the differential lead pair 12, the differential lead pair 22 and the victim line 1 and the attack line 2 in fig. 4, as shown in fig. 5A, 5B in combination with fig. 4, in a case where the differential lead pair 12 and the victim line 1 are located at different inner layers in the PCB board, the differential lead pair 22 and the attack line 2 are located at the same inner layer in the PCB board, the differential lead pair 22 and the attack line 2 are connected by the attack transition line 23, the attack transition line 23 and the attack line 2 are located at the same inner layer in the PCB board, the differential lead pair 12 and the victim line 1 are connected by the transition via 14 and the victim transition line 13, wherein the transition line 13 and the victim line 1 are located at the same inner layer in the PCB board, and the transition via 14 and the victim transition line 13 are connected between the differential lead pair 12 and the victim transition line 13.
Specifically, attack transition line 23 includes a first attack transition sub-line 231 and a second attack transition sub-line 232, victim transition via 14 includes a first victim transition sub-via 141 and a second victim transition sub-via 142, and victim transition line 13 includes a first victim transition sub-line 131 and a second victim transition sub-line 132. The first attack sub-lead 221 is connected with the first attack sub-line 201 through a first attack transition sub-line 231, the second attack sub-lead 222 is connected with the second attack sub-line 202 through a second attack transition sub-line 232, the first attack transition sub-line 231 and the second attack transition sub-line 232 are located at the same inner layer in the PCB board as the attack line 2, the first victim sub-lead 121 is connected with the first victim sub-line 101 through a first victim transition sub-via 141 and a first victim transition sub-line 131, and the second victim sub-lead 122 is connected with the second victim sub-line 102 through a second victim transition sub-via 142 and a second victim transition sub-line 132. The first victim transition sub-line 131 and the second victim transition sub-line 132 are located on the same inner layer in the PCB board as the victim line 1, the first victim transition sub-line 131 is connected to the first victim sub-line 101, the second victim transition sub-line 132 is connected to the second victim sub-line 102, the first victim transition sub-via 141 is connected between the first victim sub-line 121 and the first victim transition sub-line 131, and the second victim transition sub-via 142 is connected between the second victim sub-line 122 and the second victim transition sub-line 132.
Similar to the embodiment shown in fig. 2, in the implementation shown in fig. 4, in order that the impedance of the first victim transition sub-line 131 may be the same as or similar to the impedance of the first victim sub-line 101 and the first victim sub-line 121, preferably, the width of the first victim transition sub-line 131 needs to be larger than the width of the first victim sub-line 101 and the first victim sub-line 121, the width of the second victim transition sub-line 132 is similar, the width of the specific first victim transition sub-line 131 and the second victim transition sub-line 132 may be adaptively set according to the actual application scenario, and preferably, the width of the first attack transition sub-line 231 needs to be larger than the width of the first attack sub-line 201 and the first attack sub-line 221, and the width of the specific first attack transition sub-line 231 and the second attack transition sub-line 232 may be adaptively set according to the actual application scenario. Meanwhile, because the first victim transition sub-via 141 is different from the first victim sub-via 121 in structure, in order to facilitate the ideal tamper test result, the parameters related to the first victim transition sub-via 141 need to be adaptively set according to the actual application scenario, and the second victim transition sub-via 142 is the same.
In addition to the structure of the differential crosstalk noise coupler of the above embodiments, in practical applications, an associated interface is also required to connect with devices in the SerDes test system. Fig. 6 is a schematic diagram of the overall structure of a differential crosstalk noise coupler according to an exemplary embodiment, as shown in fig. 6, which further includes a victim line SMA (SubMiniature version A, ultra-small version a) interface 15 and an aggressor line SMA interface 25. Wherein the victim wire SMA interface 15 is connected to the victim differential lead pair 12 and the aggressor wire SMA interface 25 is connected to the aggressor differential lead pair 22. It should be noted that the structure shown in fig. 6 is extended from the structure of the embodiment shown in fig. 2, and further details of the routing can be seen from the description of fig. 2 and the above.
In the differential crosstalk noise coupler of the embodiment of the present disclosure, parameters such as width and line spacing of each single-end line in the related differential signal lines may all adopt parameters in related technologies to meet the transmission requirement of the high-speed differential signal, which is not described here in detail.
Fig. 7 is a schematic diagram of a modeling structure of a simulation segment in a differential crosstalk noise coupler according to an exemplary embodiment, fig. 8 is a schematic diagram of an impedance simulation curve for the structure shown in fig. 7, and fig. 9 is a schematic diagram of a crosstalk simulation curve for the structure shown in fig. 7. As shown in fig. 7, a dummy segment 702 selects a major part of the circuitry in the differential crosstalk noise coupler in relation to the embodiments of the present disclosure in a PCB701, the dummy segment 702 mainly comprising the structure of the victim line 1, the aggressor line 2, and a segment of the wire in the vicinity thereof. In fig. 8, the vertical axis corresponds to the impedance, the horizontal axis corresponds to the position (represented by time) of the simulation segment 702 in fig. 7, the flat area in the middle of the two curves corresponds to the impedance of the first victim sub-line 101 and the second victim sub-line 102 in the simulation segment 702, it can be seen from fig. 8 that the impedance of the first victim sub-line 101 and the second victim sub-line 102 can be maintained around 100 ohms, the impedance change of the two differential pairs of the victim line 1 and the aggressor line 2 is always stable, and can be maintained in the impedance interval applied by the differential signal line, which indicates that the victim line 1 in the differential crosstalk noise coupler of the embodiment of the disclosure does not cause a significant decrease in impedance due to the increased aggressor line 2. As can be seen from the crosstalk simulation result shown in fig. 9, the crosstalk coupling capability of the attack line 2 to the victim line 1 can reach about-28 dB, the coupling capability of the coupling band at 30GHz can still reach-30 dB, the coupling capability of the coupling band at the sampling point of 26.56GHz is-33.03 dB, and serious attenuation does not occur when the coupling band reaches 50GHz, and still is about-30 dB, which indicates that the differential crosstalk noise coupler of the embodiment of the present disclosure can achieve larger noise coupling under the condition of smaller swing of the noise signal of the attack line 2 (for the SerDes system, the swing of the signal is about 1V, and therefore, if the crosstalk of the attack line to the victim line is increased by increasing the swing, the differential crosstalk noise coupler cannot operate). The complementary explanation of the crosstalk curves is that the presence of RC (resistance and parasitic capacitance) of the signal line results in the generation of periodic resonance points where the coupling ability of the crosstalk curve is the weakest, and that the frequency points corresponding to the tip positions of the respective bottoms of the wavy shapes among the curves presented in fig. 9 are those resonance points that are present in the crosstalk curves for the related art crosstalk coupling.
In an exemplary embodiment, a PCB board employing the differential crosstalk noise coupler of any of the above embodiments is also provided.
In an exemplary embodiment, there is also provided a SerDes test system employing the differential crosstalk noise coupler of any of the above embodiments.
The foregoing description of the preferred embodiments of the present disclosure is not intended to limit the disclosure, but rather to cover all modifications, equivalents, improvements and alternatives falling within the spirit and principles of the present disclosure.
Claims (10)
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| CN104915496A (en) * | 2015-06-08 | 2015-09-16 | 浪潮电子信息产业股份有限公司 | Method for wiring differential signal wires and device |
| CN116315891A (en) * | 2021-12-21 | 2023-06-23 | 上海寒武纪信息科技有限公司 | Connector and setting method for the same |
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| US6486405B2 (en) * | 2000-12-01 | 2002-11-26 | Hon Hai Precision Ind. Co., Ltd. | Arrangement of differential pair for eliminating crosstalk in high speed application |
| CN100396165C (en) * | 2003-11-08 | 2008-06-18 | 鸿富锦精密工业（深圳）有限公司 | Differential wire assembling method for eliminating high speed board interferes |
| US7382210B2 (en) * | 2005-09-29 | 2008-06-03 | Avago Technologies General Ip Pte. Ltd | Broadband differential coupling circuit having coupled differential aggressor and signal channels |
| US9166650B2 (en) * | 2008-07-02 | 2015-10-20 | Rambus Inc. | Capacitive-coupled crosstalk cancellation |
| US8216001B2 (en) * | 2010-02-01 | 2012-07-10 | Amphenol Corporation | Connector assembly having adjacent differential signal pairs offset or of different polarity |
| US9069910B2 (en) * | 2012-12-28 | 2015-06-30 | Intel Corporation | Mechanism for facilitating dynamic cancellation of signal crosstalk in differential input/output channels |
| CN118301840B (en) * | 2023-07-14 | 2025-01-24 | 上海钫铖微电子有限公司 | A PCB layout structure and design method for injecting crosstalk noise |
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| CN104915496A (en) * | 2015-06-08 | 2015-09-16 | 浪潮电子信息产业股份有限公司 | Method for wiring differential signal wires and device |
| CN116315891A (en) * | 2021-12-21 | 2023-06-23 | 上海寒武纪信息科技有限公司 | Connector and setting method for the same |
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