CN118900570B

CN118900570B - 3D group-pair structure single storage tube NOR flash memory and operation method thereof

Info

Publication number: CN118900570B
Application number: CN202411364920.1A
Authority: CN
Inventors: 金波
Original assignee: Shanghai Lingnai Semiconductor Technology Co ltd
Current assignee: Shanghai Lingnai Semiconductor Technology Co ltd
Priority date: 2024-09-29
Filing date: 2024-09-29
Publication date: 2025-01-28
Anticipated expiration: 2044-09-29
Also published as: CN118900570A

Abstract

The invention provides a single storage tube NOR flash memory with a 3D pairing structure and an operation method thereof. In the flash memory, a gate layer in a gate stack structure is arranged between two adjacent isolation layers in a penetrating way, a plurality of openings are formed in the gate stack structure, two first doping columns of a first conductivity type are arranged in one group at intervals and stand in one opening, two second doping columns of a second conductivity type are arranged in one group and are respectively adhered to two side walls of one first doping column, one second doping column of the same group is in contact with one local bit line, the other second doping column is in contact with one local source line, and a charge trap structure fills a gap between one first doping column and the corresponding side wall of the opening. This can significantly increase the storage density of the flash memory. The operation method provided by the invention is used for performing data operation on the flash memory.

Description

Single-storage-tube NOR flash memory with 3D pairing structure and operation method thereof

Technical Field

The invention relates to the technical field of memories, in particular to a single storage tube NOR flash memory with a 3D pairing structure and an operation method thereof.

Background

Modern electronic devices typically contain electronic memory configured to store data, such as volatile memory and/or nonvolatile memory. The nonvolatile memory has an advantage of preventing the stored data from disappearing even after power failure, and is therefore widely used as a memory element for personal computers and electronic devices.

Flash memory is one type of nonvolatile memory. In the conventional NOR flash memory array, the memory cell of the 1T (1 Transistor) structure has the advantage of small area, but has relatively large programming power consumption, and the memory cell of the 2T (2 Transistor) and split gate structures has the advantages that the selection tube is added, and the current of the memory tube is improved, but the memory area of the cell is increased. In addition, with the development of planar nonvolatile memories, the production process of semiconductors has made great progress. However, the storage density of the planar flash memory array cannot meet the market demand, and a nonvolatile memory with higher storage density needs to be researched.

Disclosure of Invention

One of the purposes of the present invention is to increase the storage density of NOR flash memory and reduce the programming power consumption of NOR flash memory.

In order to achieve the above object, the present invention provides a 3D pair-structured single storage tube NOR flash memory. The single memory tube NOR flash memory with the 3D group pair structure comprises a grid stacking structure, a first memory tube and a second memory tube, wherein the grid stacking structure comprises a plurality of first isolation layers and a plurality of grid layers which are stacked, one grid layer is arranged between two adjacent first isolation layers in a penetrating way, and a plurality of openings are formed in the grid stacking structure; a plurality of first doped columns of a first conductivity type, wherein two first doped columns are arranged in a group and are erected in one opening at intervals; the first doping column is provided with a first side wall, a second side wall, a third side wall, a fourth side wall, a plurality of second doping columns, a plurality of local bit lines, a plurality of local source lines, a plurality of first doping columns, a plurality of second doping columns, a plurality of local source lines and a plurality of local source lines, wherein the first side wall and the second side wall are opposite to each other, the third side wall and the fourth side wall are opposite to each other, the first side wall faces the side wall of the opening, the second side wall faces the other first doping column, the second doping columns are opposite to each other, the second doping columns are arranged in the same opening, the second doping columns are respectively attached to the third side wall and the fourth side wall of one first doping column, the charge trap structure fills gaps between the first doping column and the side wall of the opening facing the first side wall of the first doping column, the local bit lines and the local source lines stand in the openings, the local bit lines and the local source lines are arranged in the openings, the local source lines and the local source lines are in a group, the local source lines are in contact with the local source lines, and the local source lines are in contact with the local source lines, and the local source lines are in the local contact with the local source lines.

Optionally, the plurality of openings are arranged in a plurality of rows in the gate stacking structure, and the openings in two adjacent rows are arranged in a staggered manner in a vertical direction in the row direction.

Optionally, the 3D paired structure of single memory tube NOR flash memory includes a plurality of memory tubes, a channel region of one memory tube is a portion of one first doped column corresponding to a sidewall of one gate layer in the opening, a channel of one memory tube is a planar channel, and two memory tubes of one gate layer corresponding to two memory tubes in one opening are paired.

Optionally, the first side wall and the second side wall of the first doped column are both straight planes, and the channel of the storage tube is a straight channel.

Optionally, the 3D pair-structured single memory tube NOR flash memory further includes a substrate, and the gate stack structure is formed on the substrate.

Optionally, a plurality of bit line selection tubes and a plurality of source line selection tubes are formed on the substrate, the two bit line selection tubes are in a group, the two source line selection tubes are in a group, a plurality of global bit lines and a plurality of global source lines are also formed on the top surface of the substrate, the two global bit lines are in a group, the two global source lines are in a group, first ends of the two bit line selection tubes in the same group are connected with the same local bit line, second ends of the two bit line selection tubes in the same group are respectively connected with the two global bit lines in the same group, first ends of the two source line selection tubes in the same group are respectively connected with the same local source line, and second ends of the two source line selection tubes in the same group are respectively connected with the two global source lines in the same group.

The semiconductor device comprises a substrate, a plurality of word lines, a group of bit line selection tubes, a group of source line selection tubes and a group of word line selection tubes, wherein the substrate is provided with the plurality of word lines, the group of bit line selection tubes comprises a first bit line selection tube and a second bit line selection tube, the group of source line selection tubes comprises a first source line selection tube and a second source line selection tube, and the grid electrode of the first bit line selection tube and the grid electrode of the first source line selection tube are connected with one word line together for the group of local bit lines and selection tubes corresponding to the local source lines, and the grid electrode of the second bit line selection tube and the grid electrode of the second source line selection tube are connected with the other word line together.

Optionally, the plurality of openings are arranged in rows and columns on the substrate, the local bit lines and the local source lines of the same group in one opening are arranged in a row, the local bit lines and the local source lines of the same group in one opening are arranged in two rows, the local bit lines and the local source lines in one row are arranged in two rows, the local bit lines and the local source lines in the same row are corresponding to the selection tubes of the local bit lines and the local source lines, the grid electrode of the first bit line selection tube and the grid electrode of the first source line selection tube are commonly connected with one word line, and the grid electrode of the second bit line selection tube and the grid electrode of the second source line selection tube are commonly connected with the other word line.

Optionally, the group of global bit lines includes a first global bit line and a second global bit line, the group of global source lines includes a first global source line and a second global source line, in bit line selection tubes corresponding to the local bit lines in the same column of openings, a second end of each first bit line selection tube is connected to the first global bit line, a second end of each second bit line selection tube is connected to the second global bit line, in source line selection tubes corresponding to the local source lines in the same column of openings, a second end of each first source line selection tube is connected to the first global source line, and a second end of each second source line selection tube is connected to the second global source line.

Optionally, the charge trap structure comprises a first oxide layer, a nitride layer and a second oxide layer stacked in the vertical direction of the first side wall of the first doped column, wherein the first oxide layer is in contact with the corresponding first side wall of the first doped column, the second oxide layer is in contact with the opening side wall, and the nitride layer is located between the first oxide layer and the second oxide layer.

The invention further provides an operation method of the single storage tube NOR flash memory with the 3D group pair structure, which is used for carrying out reading operation on the single storage tube NOR flash memory with the 3D group pair structure and comprises the steps of respectively enabling a grid layer, a local bit line and a local source line corresponding to a storage tube to be read to be called a selected grid layer, a selected local bit line and a selected local source line, applying an opening positive voltage to the selected grid layer to enable the storage tube corresponding to the selected grid layer to be in an opening state, applying a closing negative voltage to an unselected grid layer to enable the storage tube corresponding to the unselected grid layer to be in a closing state, applying a first reading voltage to the selected local bit line, applying a second reading voltage to the selected local source line, suspending the unselected local bit line and the unselected local source line, and applying a well region negative voltage to all the first doped columns.

The invention further provides an operation method of the single memory tube NOR flash memory with the 3D group pair structure, which is used for writing the single memory tube NOR flash memory with the 3D group pair structure and comprises the steps of respectively calling a grid layer, a local bit line and a local source line corresponding to a memory tube to be written into as a selected grid layer, a selected local bit line and a selected local source line, applying a first positive voltage to the selected grid layer, applying a first negative voltage to unselected grid layers, applying a second negative voltage to all the first doped columns, applying a third negative voltage to both the selected local bit line and the selected local source line, and applying a second positive voltage to both the unselected local bit line and the unselected local source line.

The invention further provides an operation method of the single storage tube NOR flash memory with the 3D group pair structure, which is used for performing erasing operation on the single storage tube NOR flash memory with the 3D group pair structure and comprises the steps of respectively enabling a grid layer, a local bit line and a local source line corresponding to a storage tube to be erased to be called a selected grid layer, a selected local bit line and a selected local source line, applying erasing negative voltage to the selected grid layer, applying protective positive voltage to unselected grid layers, applying first erasing positive voltage to all the local bit lines, applying second erasing positive voltage to all the local source lines and applying well region positive voltage to all the first doping columns.

In the single memory tube NOR flash memory with the 3D group pair structure, the grid stacking structure comprises a plurality of grid layers which are isolated from each other, a plurality of openings are formed in the grid stacking structure, the first doping columns, the second doping columns and the charge trap structure are all erected in the openings, so that a NOR memory array with the 3D structure is formed, wherein a channel region of one memory tube is a part of one first doping column corresponding to the side wall of one grid layer in the opening, two first doping columns are arranged in one opening, each first doping column independently corresponds to two second doping columns and one charge trap structure, two memory tubes in the vertical direction are formed in the same opening, two memory tubes in the same group are independently controlled by two groups of local source lines and local bit lines, the memory structure of 1T is realized, the memory density of the NOR flash memory with 3D is remarkably improved, and the voltage of the local bit lines and the local source lines corresponding to one memory tube is equal to the voltage of the NOR flash memory during data writing, so that the power consumption of the NOR flash memory can be reduced.

Drawings

Fig. 1 is a schematic plan view illustrating a gate layer of a 3D pair-wise structured single-storage-tube NOR flash memory according to an embodiment of the present invention.

Fig. 2 is a cross-sectional view of a gate stack structure of a 3D paired structure single storage tube NOR flash memory according to an embodiment of the present invention.

Fig. 3 is a schematic diagram of a current direction of a memory tube of the single memory tube NOR flash memory with a 3D pair structure according to the present invention during a read operation.

Fig. 4 is a schematic diagram of electron flow direction of a memory tube of a single memory tube NOR flash memory with a 3D pair structure according to the present invention during a write operation.

Fig. 5 is a schematic diagram of electron flow direction of a memory tube of a single memory tube NOR flash memory with a 3D pair structure according to the present invention during an erase operation.

FIG. 6 is a circuit diagram of a memory array of a 3D group pair structure of a single-memory-tube NOR flash memory according to an embodiment of the present invention.

Fig. 7 is a schematic cross-sectional view of a 3D pair-wise structured single-storage-tube NOR flash memory according to an embodiment of the present invention.

FIG. 8 is a circuit diagram of select transistors, global bit lines, and global source lines on a substrate according to one embodiment of the present invention.

FIG. 9 is a layout diagram of global bit lines, global source lines, word lines and openings on a substrate according to an embodiment of the invention.

Fig. 10 is a schematic plan view illustrating a gate layer of a 3D pair-wise structured single-storage-tube NOR flash memory according to another embodiment of the present invention.

FIG. 11 is a schematic diagram showing a voltage application condition when a single-memory-tube NOR flash memory with a 3D group pair structure according to an embodiment of the invention is read.

FIG. 12 is a schematic diagram showing the voltage applied to the global bit lines, the global source lines and the select gates of the single-memory-tube NOR flash memory with 3D group pair architecture according to one embodiment of the present invention.

FIG. 13 is a schematic diagram showing the voltage application during a write operation to a 3D group pair structure of a single-memory-tube NOR flash memory according to an embodiment of the present invention.

FIG. 14 is a diagram showing the voltage applied to the global bit lines, the global source lines and the select gates of the single-memory-tube NOR flash memory with 3D group pair architecture according to one embodiment of the present invention.

FIG. 15 is a schematic diagram of a voltage application state when an erase operation is performed on a 3D group pair structure of a single-memory-tube NOR flash memory according to an embodiment of the present invention.

FIG. 16 is a diagram illustrating the voltage applied to the global bit lines, the global source lines and the select gates of the single-memory-tube NOR flash memory of the 3D group pair structure according to one embodiment of the present invention.

Detailed Description

The 3D group pair structured single memory tube NOR flash memory and the operation method thereof according to the present invention are described in further detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.

Fig. 1 is a schematic plan view illustrating a gate layer of a 3D pair-wise structured single-storage-tube NOR flash memory according to an embodiment of the present invention. Fig. 2 is a cross-sectional view of a gate stack structure of a 3D paired structure single storage tube NOR flash memory according to an embodiment of the present invention. Among them, fig. 1 may be a cross-sectional view of an XY plane, and fig. 2 may be a cross-sectional view of a gate stack structure in a Z direction, which is perpendicular to the X direction and the Y direction.

Referring to fig. 1 and 2, the 3D pair-wise structured single memory tube NOR flash memory provided in this embodiment includes a gate stack structure, a plurality of first doped columns 201, a plurality of second doped columns 202, a plurality of charge trap structures 205, a plurality of local bit lines 203, and a plurality of local source lines 204. The gate stack structure includes a plurality of first spacers 102 and a plurality of gate layers 101 stacked together, one gate layer 101 is interposed between two adjacent first spacers 102, and the gate stack structure has a plurality of openings 103 therein. The first doped columns 201 are of a first conductivity type, two first doped columns 201 are in a group and stand in one opening 103 at intervals, the first doped columns 201 have opposite first and second side walls 201a and 201b and opposite third and fourth side walls 201c and 201d, and for a group of first doped columns 201, the first side wall 201a of one first doped column faces the side wall of the opening 103 and the second side wall 201b faces the other first doped column 201. The second doped columns 202 are of a second conductivity type opposite to the first conductivity type, two second doped columns 202 are of a group and are arranged in the same opening 103, and the third side wall 201c and the fourth side wall 201d of one first doped column 201 are respectively attached to the two second doped columns 202 of the same group. A charge trapping structure 205 fills the gap between a first doped column 201 and the opening sidewall facing the first sidewall 201a of the first doped column. A plurality of local bit lines 203 and a plurality of local source lines 204 stand up in the plurality of openings 103, one local bit line 203 and one local source line 204 are in a group and correspond to a group of second doped columns 202, one of the two second doped columns 202 of the same group is in contact with the corresponding local bit line 203, and the other is in contact with the corresponding local source line 204.

Specifically, in the gate stack structure, adjacent gate layers 101 are isolated by a first isolation layer 102. The material of the gate layer 101 includes, but is not limited to, metal or polysilicon. The material of the first isolation layer 102 includes, but is not limited to, silicon oxide (SiO ₂) or silicon nitride (SiN). The thicknesses of the gate layer 101 and the first isolation layer 102 may be set as needed.

Referring to fig. 1, the gate stack has a plurality of openings 103 therein, and each opening 103 may extend through the gate stack. Illustratively, the opening 103 may have a rectangular shape, such as a rectangle, but is not limited thereto. In the present application, the same opening 103 can simultaneously produce two pairs of single tube memory cell transistors that are controlled relatively independently.

The first doped column 201 may be doped polysilicon or other thin film deposition layer. The first doped column 201 is of a first conductivity type. The first conductive type is exemplified by P-type, and the first doped column 201 is exemplified by P-well, but not limited thereto.

Illustratively, referring to fig. 1, the first doped column 201 is a rectangular column, the first doped column 201 having opposing first and second sidewalls 201a and 201b and opposing third and fourth sidewalls 201c and 201d. One opening 103 is provided with a set of first doped columns 201, and for the set of first doped columns 201, a first sidewall 201a of one first doped column 201 faces a sidewall of the opening 103 and a second sidewall 201b faces another first doped column 201.

The second doped column 202 is of a second conductivity type opposite the first conductivity type. In the present embodiment, the second conductivity type is N type, but is not limited thereto. In other embodiments, the first conductivity type may be N-type and the second conductivity type may be P-type. The material of the second doped column 202 includes, but is not limited to, polysilicon.

In this embodiment, two second doped columns 202 are a group and vertically disposed in the same opening 103, and the third sidewall 201c and the fourth sidewall 201d of one first doped column 201 are respectively attached to the two second doped columns 202 of the same group, or the two second doped columns 202 of the same group are respectively connected to the third sidewall 201c and the fourth sidewall 201d of one first doped column 201. Referring to fig. 1, in the present embodiment, two sets of second doped columns 202 are disposed in one opening 103, and one set of second doped columns 202 is located at two sides of one first doped column 201.

Referring to fig. 1, a charge trapping structure 205 fills the gap between a first doped column 201 and the opening sidewall facing the first sidewall 201a of the first doped column 201.

The memory tubes of the 3D group pair structured single memory tube NOR flash memory are exemplified as charge trap type memory tubes. The charge trap structure 205 includes a first oxide layer, a nitride layer, and a second oxide layer stacked in a vertical direction (i.e., Y direction of fig. 1) of the first sidewall 201a of the first doped column 201, i.e., the charge trap structure 205 is an ONO layer. The first oxide layer is in contact with the first sidewall 201a of the corresponding first doped column 201, the second oxide layer is in contact with the opening sidewall, and the nitride layer is located between the first oxide layer and the second oxide layer. The first oxide layer and the second oxide layer may be silicon oxide layers, and the nitride layer may be a silicon nitride layer.

With continued reference to fig. 1, a plurality of local bit lines 203 and a plurality of local source lines 204 of a 3D group pair structure single memory tube NOR flash memory stand up within the plurality of openings 103, and the local bit lines 203 and the local source lines 204 are elongated in a Z direction perpendicular to the X direction and the Y direction. One local bit line 203 and one local source line 204 are a group corresponding to a group of second doped columns 202, one second doped column 202 of the group of second doped columns 202 is in contact with the corresponding local bit line 203, and the other second doped column 202 is in contact with the local source line 204.

In this embodiment, the local bit lines 203 and the local source lines 204 of the same group are equivalent and can be switched with each other. Each set of local bit lines 203 and local source lines 204 may be independently controlled, as may each first doped column 201.

For example, as shown with reference to fig. 1, the opening 103 may have a rectangular opening shape, but is not limited thereto. Each opening 103 has two local bit lines 203 and two local source lines 204 therein, and the two local bit lines 203 and the two local source lines 204 are respectively disposed near four corners of the rectangle. Referring to fig. 1, the charge trap structure 205 also extends to fill the gap between the partial source line 203 and the opening sidewall and the gap between the partial source line 204 and the opening sidewall.

In this embodiment, two first doped columns 201, four second doped columns 202, two local bit lines 203 and two local source lines 204 extending along the Z direction are disposed in one opening 103, one first doped column 201 corresponds to one charge trapping structure 205, two second doped columns 202, one local bit line 203 and one local source line 204, and two second doped columns 202, one local bit line 203 and one local source line 204 corresponding to one first doped column 201 may be aligned in the X direction.

The opening 103 is further filled with a second isolation layer 206, the second isolation layer 206 isolates the two first doped columns 201 and the second doped columns 202, the local bit lines 203 and the local source lines 204 corresponding to the two first doped columns 201, and the second isolation layer 206 also isolates the side walls of the opening and the local bit lines 203 and the local source lines 204 in the opening. Illustratively, the material of the second isolation layer 206 includes, but is not limited to, silicon dioxide.

Illustratively, the plurality of openings 103 in the gate stack structure may have equal depths, and the local bit lines 203 and the local source lines 204 within the openings 103 may have equal heights, and the first doped columns 201, the second doped columns 202, and the charge trap structures 205 may have equal heights, but are not limited thereto.

In this embodiment, the single memory tube NOR flash memory with the 3D pair structure includes a plurality of memory tubes, the channel region of one memory tube is a portion of the first doped column 201 corresponding to the sidewall of one gate layer 101 in the opening 103, and the channel of one memory tube is a planar channel. The first sidewall 201a and the second sidewall 201b of the first doped column 201 are both straight planes, and the channel of the memory tube is a straight channel.

Fig. 3 is a schematic diagram of a current direction of a memory tube of the single memory tube NOR flash memory with a 3D pair structure according to the present application during a read operation. As shown in fig. 3, in the case of performing a read operation on the flash memory according to the present application, as shown in fig. 3, a read current in the memory cell flows from the local bit line 203 to the local source line 204, i.e., the read current direction is horizontal (i.e., X direction) and perpendicular to the extension direction (i.e., Z direction) of the first doped column 201.

Fig. 4 is a schematic diagram of electron flow direction of a memory tube of a single memory tube NOR flash memory with a 3D pair structure according to the present application during a write operation. As shown in fig. 4, in writing the flash memory of the present application, electrons flow from the first doped column 201 into the charge trap structure 205, i.e., the current direction is the reverse direction of the Y direction, as shown in fig. 4.

Fig. 5 is a schematic diagram of electron flow direction of a memory tube of a single memory tube NOR flash memory with a 3D pair structure according to the present application during an erase operation. As shown in fig. 5, in the case of performing an erase operation on the flash memory according to the present application, electrons flow out from the charge trapping structure 205 to the first doped column 201, i.e., the current direction is the Y direction, as shown in fig. 5.

FIG. 6 is a circuit diagram of a memory array of a 3D group pair structure of a single-memory-tube NOR flash memory according to an embodiment of the present invention. As shown in fig. 6, one first doped column corresponds to one column of memory tubes, where the column direction in fig. 6 corresponds to the Z direction in fig. 2, the Z direction is the depth direction of the opening 103, one column of memory tubes is correspondingly connected to one Bit Line (BL) and one Source Line (SL), two memory tubes corresponding to one gate layer (GATE LAYER) in one opening 103 are two memory tubes of a group pair, such as two memory tubes of a group pair in a dashed Line frame in fig. 6, and two columns of memory tubes are formed in one opening 103.

Fig. 7 is a schematic cross-sectional view of a 3D pair-wise structured single-storage-tube NOR flash memory according to an embodiment of the present invention. Referring to fig. 7, the single storage tube NOR flash memory of the 3D pair structure further includes a substrate 100. The substrate 100 may be a silicon substrate, a germanium substrate, a silicon on insulator (Silicon On Insulator, SOI), a germanium on insulator (Germanium On Insulator, GOI), or the like, and certain doping particles may be implanted into the substrate 100 according to design requirements to change electrical parameters.

The substrate 100 may be formed thereon with a plurality of selection tubes 104 and a metal layer 105 on the selection tubes 104, and a gate stack structure is formed on the substrate 100, specifically, the gate stack structure is formed on the metal layer 105, i.e., the plurality of gate layers 101 and the plurality of first isolation layers 102 are stacked on the metal layer 105. A plurality of metal layers 105 may be formed on the substrate 100. Referring to fig. 7 and 1, the traces in metal layer 105 are perpendicular to local bit lines 203 and local source lines 204.

Illustratively, referring to fig. 7, the gate electrode of the selection tube 104 is formed on the substrate 100, and the source and drain electrodes of the selection tube 104 are formed in the substrate 100. FIG. 8 is a circuit diagram of select transistors, global bit lines, and global source lines on a substrate according to one embodiment of the present invention. Referring to fig. 7 and 8, a plurality of selection tubes 104 are arranged in an array on the substrate 100, and the plurality of selection tubes 104 include a plurality of bit line selection tubes connected to the local bit lines 203 and a plurality of source line selection tubes connected to the local source lines 204.

Referring to fig. 7 and 8, the metal layer 105 may include a plurality of Global Bit Lines (GBLs), a plurality of Global source lines (Global Source Line, GSLs), and a plurality of Word Lines (WLs). Specifically, the substrate 100 may have a first metal layer, a second metal layer, and a third metal layer, the local bit line and the local source line may be connected to a pad of the second metal layer or the third metal layer, the global bit line and the global source line may be formed in the first metal layer or the second metal layer, and a contact hole (CT) may be formed between the first metal layer, the second metal layer, and the third metal layer to implement interconnection.

Referring to fig. 7 and 8, the gates of a row of selection tubes are connected to a word line, and a column of selection tubes is correspondingly connected to two global bit lines or correspondingly connected to two global source lines, wherein the column direction of a column of selection tubes refers to the Y direction in fig. 8, and the column direction of the selection tubes is perpendicular to the column direction of the storage tubes. It should be noted that, when the single memory tube NOR flash memory of the 3D group pair structure is operated, voltages may be applied to the local bit lines and the local source lines through the global bit lines and the global source lines, and the local bit lines and the local source lines may be connected to the corresponding global bit lines and global source lines through control of the selection tube.

Specifically, two global bit lines are grouped together, and a group of global bit lines includes a first global bit line and a second global bit line, and illustratively, a group of first global bit line GBL0 and second global bit line GBL0 'and a group of first global bit line GBL1 and second global bit line GBL 1'.

The two global source lines are in a group, the group of global source lines comprises a first global source line and a second global source line, and the first global source line GSL0 and the second global source line GSL0 'are in a group and the first global source line GSL1 and the second global source line GSL1' are in a group.

The first ends of the two source line selection tubes of the same group are connected with the same local source line, and the second ends of the two source line selection tubes of the same group are connected with the same local source line.

For example, referring to fig. 8, a set of bit line selection pipes includes a first bit line selection pipe M1 and a second bit line selection pipe M2 adjacent to each other, and taking a set of bit line selection pipes in an upper left corner of fig. 8 as an example, the first ends of the first bit line selection pipe M1 and the second bit line selection pipe M2 are both connected to the local bit line BL00, the second end of the first bit line selection pipe M1 is connected to the first global bit line GBL0, the second end of the second bit line selection pipe M2 is connected to the second global bit line GBL0', and a set of source line selection pipes includes a first source line selection pipe N1 and a second source line selection pipe N2 adjacent to each other, and taking a set of source line selection pipes in an upper left corner of fig. 8 as an example, the first ends of the first source line selection pipe N1 and the second source line selection pipe N2 are both connected to the local source line SL00, the second end of the first source line selection pipe N1 is connected to the first global source line GSL0, and the second end of the second source line selection pipe N2 is connected to the second global source line GSL0'.

FIG. 9 is a layout diagram of global bit lines, global source lines, word lines and openings on a substrate according to an embodiment of the invention. Illustratively, referring to FIG. 9, a plurality of openings 103 are arranged in rows and columns on the substrate 100 in a plane parallel to the top surface of the substrate 100, the same set of local bit lines and local source lines within one opening 103 are arranged in a row, such as the same set of local bit lines BL00 and local source lines SL00 are arranged in a row, two sets of local bit lines and local source lines within one opening 103 are arranged in two rows, the local bit lines within one row of openings 103 are arranged in a column, the local source lines within one column of openings are arranged in a column, such as local bit lines BL00, BL10, BLN0 and BLN+10 are arranged in a column, and local source lines SL00, SL10, SLN0 and SLN+10 are arranged in a column.

Referring to fig. 8 and 9, a plurality of word lines are formed on a substrate 100. For the selection tubes corresponding to the local bit lines and the local source lines of a group, such as the selection tubes corresponding to the local bit lines BL00 and the local source lines SL00 of the same group, the grid electrode of the first bit line selection tube M1 and the grid electrode of the first source line selection tube N1 are commonly connected with one word line WL0, and the grid electrode of the second bit line selection tube M2 and the grid electrode of the second source line selection tube N2 are commonly connected with the other word line WL0'. For the selection tubes corresponding to the local bit lines and the local source lines in the same row, the grid electrode of the first bit line selection tube M1 and the grid electrode of the first source line selection tube N1 are commonly connected with one word line, and the grid electrode of the second bit line selection tube M2 and the grid electrode of the second source line selection tube N2 are commonly connected with the other word line. Fig. 6 exemplarily shows a circuit diagram of a memory array corresponding to the word lines WL0 and WL 1.

Referring to fig. 8 and 9, the bit line selection tubes corresponding to the local bit lines in the same column of openings 103 correspond to a group of global bit lines, among the bit line selection tubes corresponding to the local bit lines in the same column of openings 103, the second ends of all the first bit line selection tubes M1 are connected to the first global bit line, the second ends of all the second bit line selection tubes N2 are connected to the second global bit line, for example, the second ends of the first bit line selection tubes M1 corresponding to the first column of local bit lines are connected to the first global bit line GBL0 and the second ends of the second bit line selection tubes M2 corresponding to the first column of local bit lines are connected to the second global bit line GBL0', the second ends of all the first source line selection tubes N1 are connected to the first global source line, and the second ends of all the second source line selection tubes N2 are connected to the second global source line, for example, the second source line selection tubes corresponding to the local source line selection tubes M2 corresponding to the first global source line and the second source line selection tubes N1' corresponding to the second global source line of the second column of local bit line selection tubes N0.

Fig. 10 is a schematic plan view illustrating a gate layer of a 3D pair-wise structured single-storage-tube NOR flash memory according to another embodiment of the present invention. In some embodiments, referring to fig. 10, the openings 103 are arranged in a plurality of rows in the gate stack structure, the row direction is, for example, the X direction, and the openings 103 of two adjacent rows are offset in the vertical direction of the row direction, so that the space for picking the top layer or the bottom layer of the gate stack structure can be increased. When the openings 103 of two adjacent rows are arranged in a staggered manner in the vertical direction of the row direction, the openings 103 of one row are not in a straight line, but are bent columns along with the staggered bending, and the local bit line columns and the local source line columns in the openings 103 of one row are also corresponding to each other to be bent columns.

The invention provides an operation method of the single storage tube NOR flash memory with the 3D group pair structure.

The invention provides an operation method of a single storage tube NOR flash memory with a 3D group pair structure, which is used for reading the single storage tube NOR flash memory with the 3D group pair structure, and comprises the steps of respectively calling a grid layer, a local bit line and a local source line corresponding to a storage tube to be read as a selected grid layer, a selected local bit line and a selected local source line; the method comprises the steps of applying an opening positive voltage to a selected gate layer to enable a storage tube corresponding to the selected gate layer to be in an opening state, applying a closing negative voltage to an unselected gate layer to enable the storage tube corresponding to the unselected gate layer to be in a closing state, applying a first reading voltage to a selected local bit line, applying a second reading voltage to a selected local source line, suspending the unselected local bit line and the unselected local source line, and applying a well region negative voltage to all first doped columns.

When the 3D group pair structure single storage tube NOR flash memory is subjected to reading operation, a first reading voltage is applied to all global bit lines, a second reading voltage is applied to all global source lines, a selection tube starting voltage is applied to word lines connected with grid electrodes of two bit line selection tubes corresponding to the selected local bit lines, so that the selection tubes corresponding to the selected local bit lines and the selected local source lines are in an on state, the word lines connected with the grid electrodes of the two bit line selection tubes connected with the selected local bit lines are selected word lines, the rest word lines are unselected word lines, and a 0V voltage is applied to all unselected word lines, so that the selection tubes connected with the unselected word lines are in an off state.

Illustratively, referring to FIG. 11, an on positive voltage Vgread-select is applied to the selected gate layer GATE LAYER N, the corresponding memory tube of the selected gate layer is in an on state, an off negative voltage Vgread-unselect is applied to the unselected gate layers GATE LAYER 0, GATE LAYER 1, GATE LAYER N +1, etc., the corresponding memory tube of the unselected gate layer is in an off state, a first read voltage Vbread is applied to the selected local bit lines BL10, BL11, & gt, BL1N, a second read voltage Vsread is applied to the selected local source lines SL10, SL11, & gt, SL1N, the unselected local bit lines BL00, BL01, & gt, BL0N, and the unselected local source lines SL00, SL01, & gt, SL0N are all suspended (float), and a well region negative voltage Vrwell is applied to all first doped columns.

Illustratively, the on positive voltage Vgread-select is 0V or more and 3.5V or less. Illustratively, the off negative voltage Vgread-unselect is equal to or greater than-3.5V and equal to or less than 0V. Illustratively, the first read voltage Vbread is greater than or equal to 0V and less than or equal to 2.5V. The second reading voltage Vsread is, for example, 0V or more and 2.5V or less. Illustratively, the well region negative voltage Vrwell is equal to or greater than-3.5V and equal to or less than 0V.

For example, in response to the voltage application condition of fig. 11, when performing a read operation, as shown in fig. 12, a first read voltage Vbread is applied to all global bit lines GBL, a second read voltage Vsread is applied to all global source lines GSL, word lines WL1 and WL1' connected to gates of two bit line selection transistors corresponding to the selected local bit lines are selected word lines, the remaining word lines are unselected word lines, a selection transistor on voltage Vwron is applied to the selected word lines, so that the selection transistors corresponding to the selected local bit lines and the selected local source lines are in an on state, and voltages on the global bit lines and the global source lines can flow to the selected local bit lines and the selected local source lines, and a 0V voltage is applied to the unselected word lines, so that the selection transistors connected to the unselected word lines are in an off state, and voltages on the global bit lines and the global source lines cannot flow to the selected local bit lines and the selected local source lines. Illustratively, the select tube turn-on voltage Vwron is 2.5V or more and 5V or less.

In this embodiment, a reading is described taking a page of memory tubes corresponding to two word lines as a reading unit. In other embodiments, the partial memory tubes corresponding to the selected word line may be read by changing the voltages of the partial global bit line and the global source line.

The invention provides an operation method of a single storage tube NOR flash memory with a 3D group pair structure, which is used for writing operation of the single storage tube NOR flash memory with the 3D group pair structure, and comprises the steps of respectively calling a grid layer, a local bit line and a local source line corresponding to a storage tube to be written into as a selected grid layer, a selected local bit line and a selected local source line; the method includes applying a first positive voltage to a selected gate layer, applying a first negative voltage to an unselected gate layer, applying a second negative voltage to all first doped columns, and applying a third negative voltage to both a selected local bit line and a selected local source line, and applying a second positive voltage to both an unselected local bit line and an unselected local source line.

When writing operation is carried out on the single memory tube NOR flash memory with the 3D group pair structure, a third negative voltage is applied to a group of global bit lines corresponding to the selected local bit lines and a group of global source lines corresponding to the selected local source lines, a second positive voltage is applied to the first global bit lines and the second global source lines, a second positive voltage is applied to a group of global bit lines corresponding to the unselected local bit lines and a group of global source lines corresponding to the unselected local source lines, the first positive voltage is applied to the first global bit lines, the second global bit lines and the second global source lines, a third positive voltage is applied to a word line connected with a first bit line selection pipe M1 and a first source line selection pipe N1 which are connected with the selected local bit lines, the first bit line selection pipe M1 and the first source line selection pipe N1 are opened, the second negative voltage is applied to a second bit line selection pipe M2 which is connected with the unselected local bit lines, the first positive voltage is applied to the word line connected with the second bit line selection pipe N2 which is connected with the selected bit line selection pipe N2, the second positive voltage is applied to the word line connected with the second bit line selection pipe N2 which is not selected, and the word line selection pipe N2 which is connected with the selected bit line selection pipe N10 is connected with the selected bit line selection word line selection N1.

Illustratively, referring to FIG. 13, a first positive voltage Vgpro-select is applied to the selected gate layer GATE LAYER N, a first negative voltage Vgpro-unselect is applied to the unselected gate layers GATE LAYER 0, GATE LAYER 1, GATE LAYER N +1, etc., a second negative voltage Vpro-well is applied to all first doped columns, a third negative voltage Vpro is applied to both the selected local bit lines BL10, BL1N and the selected local source lines SL10, SL1N, and a second positive voltage Vinhibit is applied to both the unselected local bit lines BL00, BL01, BL11, BL0N, etc., and the unselected local source lines SL00, SL01, SL11, SL0N, etc.

For example, corresponding to the voltage applying condition of fig. 13, at the time of performing the write operation, as shown in fig. 14, the selected local bit line BL10 corresponds to the same group of the first global bit line GBL0 and the second global bit line GBL0', the selected local bit line BL1N corresponds to the same group of the first global bit line GBLN and the second global bit line GBLN', the selected local source line SL10 corresponds to the same group of the first global source line GSL0 and the second global source line GSL0', the same group of the first global source line GSLN and the second global bit line GSLN' corresponding to the selected local source line SL1N, the first global bit lines GBL0, GBLN and the second global source lines GBL0', GBLN' each apply the third negative voltage Vpro, and the second global bit lines GBL0', GBLN' and the second global source lines GSL0', GSLN' each apply the second positive voltage Vinhibit; for a group of global bit lines corresponding to an unselected local bit line and a group of global source lines corresponding to an unselected local source line, a second positive voltage Vinhibit is applied to each of the first global bit line GBL1, the first global source line GSL1, the second global bit line GBL1 'and the second global source line GSL1', a third positive voltage Vwpon is applied to the word line WL1 connected to the first bit line selection transistor M1 connected to the selected local bit line and the first source line selection transistor N1 connected to the selected local source line, a fourth negative voltage Vwpoff is applied to the word line WL1 'connected to the second source line selection transistor M2 connected to the selected local bit line, so that Vpro flows to the selected local bit line and the selected local source line, the word lines WL1, WL1' connected to the gates of the two bit line selection transistors corresponding to the selected local bit line are all referred to as selected word lines, the rest word lines are unselected word lines, a positive voltage Vwpon is applied to the second word line Vwpoff connected to the second bit line selection transistor M2 connected to the first bit line selection transistor M1, causing the Vinhibit to flow to unselected local bit lines and unselected local source lines.

Illustratively, the first positive voltage Vgpro-select is 3.6V or more and 5.4V or less. Illustratively, the first negative voltage Vgpro-unselect is equal to or greater than-4.5V and equal to or less than-2.5V. The second negative voltage Vpro-well is equal to or greater than-5.4V and equal to or less than-3.6V, and the third negative voltage Vpro is equal to or greater than-5.4V and equal to or less than-3.6V. Illustratively, the second positive voltage Vinhibit is greater than or equal to 0V and less than or equal to 2.5V. Illustratively, the third positive voltage Vwpon is equal to or greater than 3.6V and equal to or less than 5.4V. Illustratively, the fourth negative voltage Vwpoff is equal to or greater than-5.4V and equal to or less than-3.6V.

It should be noted that, for the single memory tube NOR flash memory of the 3D group pair structure of the present application, the minimum writing unit is a single memory tube. In addition, during a write operation, as shown in fig. 13, the potential of the local bit line and the local source line connected by a memory tube is equal, so that there is substantially no channel current during data writing, thus significantly reducing the write power consumption of data.

The invention provides an operation method of a single storage tube NOR flash memory with a 3D group pair structure, which is used for erasing the single storage tube NOR flash memory with the 3D group pair structure, and comprises the steps of respectively calling a grid layer, a local bit line and a local source line corresponding to a storage tube to be erased as a selected grid layer, a selected local bit line and a selected local source line; the method comprises the steps of applying an erasing negative voltage to a selected gate layer, applying a protection positive voltage to an unselected gate layer, applying a first erasing positive voltage to all local bit lines, applying a second erasing positive voltage to all local source lines, and applying a well region positive voltage to all first doped columns.

Illustratively, referring to FIG. 15, an erase negative voltage Vgerase-select is applied to the selected gate layer GATE LAYER N, a protection positive voltage Vgerase-unselect is applied to the unselected gate layers GATE LAYER 0, GATE LAYER 1, GATE LAYER N +1, etc., a first erase positive voltage Vberase is applied to all local bit lines, a second erase positive voltage Vserase is applied to all local source lines, and a well region positive voltage Verase+ is applied to all first doped columns.

For example, in the case of performing an erase operation, corresponding to the voltage application condition of fig. 15, referring to fig. 16, when performing an erase operation on the single memory cell NOR flash memory of the 3D group pair structure, a first erase positive voltage Vberase is applied to all global bit lines GBL, a second erase positive voltage Vserase is applied to all global source lines GSL, and a select cell on positive voltage Vweon is applied to all word lines.

Illustratively, the erase negative voltage Vgerase-select is equal to or greater than-5.4V and equal to or less than-3.6V. Illustratively, the protection positive voltage Vgerase-unselect is 3.6V or more and 5.4V or less. Illustratively, the well region positive voltage verase+ is 3.6V or more and 5.4V or less. Illustratively, the first erase positive voltage Vberase is 3.6V or more and 5.4V or less. Illustratively, the second erase positive voltage Vserase is 3.6V or more and 5.4V or less. Illustratively, the select tube on positive voltage Vweon V is 3.6V or greater and 5.4V or less.

In this embodiment, the minimum unit of erasing a single memory tube NOR flash memory with a 3D pair structure is all the memory tubes corresponding to one gate layer.

In the 3D group pair structure single memory tube NOR flash memory provided by the invention, the gate stack structure comprises a plurality of gate layers 101 isolated from each other, a plurality of openings 103 are formed in the gate stack structure, the first doped column 201, the second doped column 202 and the charge trap structure 205 are all erected in the openings 103, thereby forming a 3D structure NOR memory array, wherein the channel region of one memory tube is a part of one first doped column 201 corresponding to the side wall of one gate layer 101 in the openings 103, two first doped columns 201 are arranged in one opening 103, each first doped column 201 independently corresponds to two second doped columns 202 and one charge trap structure 205, two memory tubes in the vertical direction are formed in the same opening, two memory tubes in the same group are independently controlled by two groups of local source lines and bit lines, the memory structure of the 3D NOR flash memory is realized, the memory density of the 3D NOR flash memory is remarkably improved, and the voltage of one memory tube corresponding to one local source line and the bit line can be reduced equally when data writing is performed.

The foregoing description is only illustrative of the preferred embodiments of the present invention, and is not intended to limit the scope of the claims, and any person skilled in the art may make any possible variations and modifications to the technical solution of the present invention using the method and technical content disclosed above without departing from the spirit and scope of the invention, so any simple modification, equivalent variation and modification made to the above embodiments according to the technical matter of the present invention fall within the scope of the technical solution of the present invention.

Claims

1. A single storage tube NOR flash memory of a 3D paired structure, comprising:

The grid electrode stacking structure comprises a plurality of first isolation layers and a plurality of grid electrode layers which are stacked, wherein one grid electrode layer is arranged between two adjacent first isolation layers in a penetrating way, and the grid electrode stacking structure is provided with a plurality of openings;

a plurality of first doped columns of a first conductivity type, wherein two first doped columns are arranged in a group and are erected in one opening at intervals; for a group of the first doped columns, the first sidewall of one of the first doped columns faces the sidewall of the opening and the second sidewall faces the other of the first doped columns;

The first doping columns are of a first conductivity type, are of a second conductivity type opposite to the first conductivity type, are arranged in the same opening, and are respectively attached to the third side wall and the fourth side wall of one first doping column;

A plurality of charge trapping structures, one of the charge trapping structures filling a gap between one of the first doped columns and a first sidewall-facing opening sidewall of the first doped column, and

A plurality of local bit lines and a plurality of local source lines erected in the openings, wherein one local bit line and one local source line are a group and correspond to one group of second doped columns; one of the two second doped columns of the same group is in contact with the corresponding local bit line, and the other is in contact with the corresponding local source line;

The single memory tube NOR flash memory of the 3D group-pair structure comprises a plurality of memory tubes, a channel region of one memory tube is a part of one first doped column corresponding to the side wall of one gate layer in the opening, a channel of one memory tube is a plane channel, and two memory tubes corresponding to one gate layer in one opening are two memory tubes of the group-pair.

2. The 3D paired structure single memory tube NOR flash memory of claim 1, wherein a plurality of said openings are arranged in a plurality of rows in said gate stack structure, said openings of adjacent two rows being offset in a vertical direction of the row direction.

3. The 3D pair-wise structured single memory tube NOR flash memory of claim 1, wherein the first sidewall and the second sidewall of the first doped column are both straight planes, and the channel of the memory tube is a straight channel.

4. The 3D pair structure single memory tube NOR flash memory of claim 1, further comprising a substrate, the gate stack structure being formed on the substrate.

5. The single memory cell NOR flash memory of claim 4 wherein said substrate has a plurality of bit line select transistors and a plurality of source line select transistors formed thereon, said two bit line select transistors being in a group and said two source line select transistors being in a group, said substrate also has a plurality of global bit lines and a plurality of global source lines formed thereon, said two global bit lines being in a group, said two global source lines being in a group, said two bit line select transistors of a same group having first ends connected to a same local bit line and second ends connected to a same group of two global bit lines, said two source line select transistors of a same group having first ends connected to a same local source line and second ends connected to a same group of two global source lines.

6. The single memory cell NOR flash memory of claim 5 wherein said substrate has a plurality of word lines formed thereon, wherein a group of said bit line select transistors comprises a first bit line select transistor and a second bit line select transistor, wherein a group of said source line select transistors comprises a first source line select transistor and a second source line select transistor, wherein for a group of said local bit lines and corresponding select transistors of said local source lines, the gates of said first bit line select transistor and said first source line select transistor are commonly connected to one of said word lines, and wherein the gates of said second bit line select transistor and said second source line select transistor are commonly connected to the other of said word lines.

7. The single memory cell NOR flash memory of claim 6, wherein a plurality of said openings are arranged in rows and columns on said substrate, wherein a same group of said local bit lines and said local source lines in one of said openings are arranged in a row, wherein a same group of said local bit lines and said local source lines in one of said openings are arranged in two rows, wherein for select transistors corresponding to said local bit lines and said local source lines in a same row, a gate of said first bit line select transistor and a gate of said first source line select transistor are commonly connected to one of said word lines, and wherein a gate of said second bit line select transistor and a gate of said second source line select transistor are commonly connected to another of said word lines.

8. The single memory cell NOR flash memory of claim 7 wherein a group of said global bit lines includes a first global bit line and a second global bit line, a group of said global source lines includes a first global source line and a second global source line, a second end of said first bit line select tube is connected to said first global bit line in a bit line select tube corresponding to said local bit line in said opening of a column, a second end of said second bit line select tube is connected to said second global bit line, a second end of said first source line select tube is connected to said first global source line in a source line select tube corresponding to said local source line in said opening of a column, and a second end of said second source line select tube is connected to said second global source line.

9. The single memory tube NOR flash memory of claim 1, wherein said charge trapping structure comprises a first oxide layer, a nitride layer and a second oxide layer stacked vertically on a first sidewall of said first doped column, said first oxide layer being in contact with a corresponding first sidewall of said first doped column, said second oxide layer being in contact with said opening sidewall, said nitride layer being between said first oxide layer and said second oxide layer.

10. A method of operating a 3D group pair structured single memory tube NOR flash memory, for reading the 3D group pair structured single memory tube NOR flash memory as claimed in any one of claims 1 to 9, comprising:

the gate layer, the local bit line and the local source line corresponding to the memory tube to be read are respectively called a selected gate layer, a selected local bit line and a selected local source line;

Applying an opening positive voltage to the selected gate layer to enable the storage tube corresponding to the selected gate layer to be in an opening state;

Applying a first read voltage to the selected local bit line and a second read voltage to the selected local source line, suspending unselected local bit lines and unselected local source lines, and

And applying a negative well region voltage to all the first doped columns.

11. A method of operating a 3D group pair structured single memory tube NOR flash memory, for writing to a 3D group pair structured single memory tube NOR flash memory as claimed in any one of claims 1 to 9, comprising:

The method comprises the steps that a grid layer, a local bit line and a local source line which correspond to a storage tube to be written are respectively called a selected grid layer, a selected local bit line and a selected local source line;

Applying a first positive voltage to the selected gate layer and applying a first negative voltage to unselected gate layers;

applying a second negative voltage to all of the first doped columns, and

And applying a third negative voltage to the selected local bit line and the selected local source line, and applying a second positive voltage to the unselected local bit line and the unselected local source line.

12. A method of operating a 3D group pair structured single memory tube NOR flash memory, for performing an erase operation on the 3D group pair structured single memory tube NOR flash memory as claimed in any one of claims 1 to 9, comprising:

the method comprises the steps that a grid layer, a local bit line and a local source line corresponding to a storage tube to be erased are respectively called a selected grid layer, a selected local bit line and a selected local source line;

applying an erase negative voltage to the selected gate layer and a protection positive voltage to the unselected gate layer;

applying a first erase positive voltage to all of the local bit lines, applying a second erase positive voltage to all of the local source lines, and

A well region positive voltage is applied to all the first doped columns.