CN118897655A - Data request processing method, device, computer equipment and storage medium - Google Patents

Abstract

The invention relates to the technical field of computers, and discloses a data request processing method, a device, computer equipment and a storage medium, wherein the method comprises the following steps: acquiring the occupied water level of the cache; under the condition that the occupied water level of the cache is higher than a preset threshold value, determining a data block to be cleaned, and releasing the cache space occupied by the data block to be cleaned; and under the condition that the data request is received from the host, determining a target cache space from the idle cache space in the cache, storing the data corresponding to the data request into the target cache space, and responding to the data request. The problem that in the process of processing the data request, if the buffer space is full, the time delay for processing the data request is increased due to replacement of the existing data in the buffer is solved.

Description

Data request processing method, device, computer equipment and storage medium

Technical Field

The present invention relates to the field of computer technology, and in particular to a data request processing method, device, computer equipment and storage medium.

Background Art

In the process of the storage system responding to data requests, caching the IO (Input/Output) data corresponding to the data request to DRAM (Dynamic Random Access Memory) can improve the performance of the storage system. For example, for a write request, the data written to the cache can be responded to by the host. The data written to the cache is flushed to non-volatile media such as HDD (Hard Disk Drive) or SSD (Solid State Disk) that are slower than DRAM in the background, reducing the response time of the write request. For a read request, if the read data is in the cache, there is no need to read the data from storage media such as HDD or SSD. The data can be directly read from the cache and returned to the host, reducing the response time of the read request.

However, in the process of processing data requests, if the cache space is full, it is necessary to use the cache replacement algorithm to replace the existing data in the cache and then store new data in the cache. The time consumption of these processes is included in the processing time of the I/O process. The cache space is limited, and it is normal for the cache space to be full during the use of the storage system. Therefore, every data request involving cached data needs to handle the cache replacement process during the processing, which increases the delay in processing data requests. The processing delay of a large number of data requests can accumulate during the use of the storage system.

Therefore, the related art has a problem that during the process of processing a data request, if the cache space is full, replacing the existing data in the cache will cause an increase in the delay of processing the data request.

Summary of the invention

In view of this, the present invention provides a data request processing method, apparatus, computer equipment and storage medium to solve the problem that in the process of processing data requests, if the cache space is full, replacing the existing data in the cache will cause an increase in the delay in processing the data request.

In a first aspect, the present invention provides a data request processing method, comprising:

Get the cache occupancy level;

When the cache occupancy level is higher than a preset threshold, determine the data blocks to be cleaned up, and release the cache space occupied by the data blocks to be cleaned up;

When a data request is received from the host, a target cache space is determined from free cache space in the cache, data corresponding to the data request is saved in the target cache space, and the data request is responded to.

The data request processing method provided in this embodiment determines the data blocks to be cleared and releases the cache space occupied by the data blocks to be cleared when the cache occupancy level is higher than a preset threshold. The cache replacement process is not included in the process of processing data requests, and the cache replacement processing time is not included in the time of processing data requests. In addition, by timely releasing the cache space occupied by the cleared data blocks, the free cache space in the cache can be directly used in the process of processing each data request, which can reduce the response time of data request processing. The processing delay of data requests is reduced, and the read and write performance of the storage system is improved. The problem that in the process of processing data requests, if the cache space is full, replacing the existing data in the cache will increase the delay in processing data requests is solved.

In some optional implementations, before obtaining the cache occupancy watermark, the method further includes:

Get the number of threads that handle cache replacement tasks;

A first preset number of data block processing queues are generated according to the number of threads, wherein the data block processing queues are used to determine and release data blocks to be cleared.

In this embodiment, a first preset number of data block processing queues are generated according to the number of threads processing cache replacement tasks, and the data block processing queues are used to manage the data blocks, determine and release the data blocks to be cleaned, so that the free cache space in the cache can be directly used in the process of processing each data request, which can reduce the response time of data request processing.

In some optional implementations, after generating a first preset number of data block processing queues, the method further includes:

Determine the identity of the logical volume to which the data block in the cache belongs;

According to the identifier of the logical volume and the first preset number, a data block processing queue corresponding to the data block is determined, and the data block is put into the corresponding data block processing queue.

In this embodiment, the data block processing queue corresponding to the data block is determined, and the data block is placed in the corresponding data block processing queue. The data block is managed by the data block processing queue to facilitate cleaning of the data block and release of the cache space occupied by the data block.

In some optional implementations, after placing the data block into the corresponding data block processing queue, the method further includes:

Determining a first replacement priority of the data block;

According to the first replacement priority, sequence numbers of data blocks are generated in a first preset number of data block processing queues.

In this embodiment, according to the first replacement priority, the sequence numbers of the data blocks are generated in the first preset number of data block processing queues, which is convenient for managing the data blocks, and the data blocks to be cleared are determined and released according to the sequence numbers, which is accurate and efficient.

In some optional implementations, when the cache occupancy level is higher than a preset threshold, determining the data block to be cleared includes:

When the cache occupancy level is higher than a first preset threshold and lower than a second preset threshold, data blocks with sequence numbers smaller than a first preset value in a first preset number of data block processing queues are used as data blocks to be cleared;

When the cache occupancy level is higher than the second preset threshold and lower than the third preset threshold, data blocks with sequence numbers smaller than the second preset value in the first preset number of data block processing queues are used as data blocks to be cleared;

When the cache occupancy level is higher than the third preset threshold and lower than the fourth preset threshold, data blocks with sequence numbers smaller than the third preset value in the first preset number of data block processing queues are used as data blocks to be cleared;

When the cache occupancy level is higher than a fourth preset threshold, data blocks with sequence numbers less than a fourth preset value in the first preset number of data block processing queues are taken as data blocks to be cleared.

In this embodiment, the cache occupancy level is compared with the first preset threshold to the fourth preset threshold, and the number of data blocks to be cleared in the data block processing queue is determined based on the comparison results, the speed of cache replacement is modified, and the computing resources of the system are reasonably utilized to ensure that the free cache space in the cache can be directly used during the processing of each data request.

In some optional implementations, after determining the data blocks to be cleared and releasing the cache space occupied by the data blocks to be cleared, the method further includes:

Determining a second replacement priority of remaining data blocks in the first preset number of data block processing queues;

According to the second replacement priority, the sequence numbers of the remaining data blocks are updated.

In some optional implementations, when a data request is received from a host, determining a target cache space from free cache space in a cache, saving data corresponding to the data request to the target cache space, and responding to the data request include:

In the case where the data request is a read request, if the data block corresponding to the read request does not exist in the cache, the target cache space is determined from the free cache space in the cache;

Acquire data corresponding to the read request from a preset storage medium, and write the data corresponding to the read request into a target cache space to generate a read request data block corresponding to the read request;

Returns the data in the read request data block to the host.

In this embodiment, by separating the cache replacement process from the data request processing process, it is ensured that free cache space in the cache can be directly used in the process of processing each read request, thereby reducing the processing delay of the read request.

In some optional implementations, releasing the cache space occupied by the data block to be cleared includes:

In the case where the data block to be cleaned is a read request data block, the data block to be cleaned in the data block processing queue is deleted;

The positions of the remaining data blocks in the data block processing queue are swapped using a preset algorithm.

In some optional implementations, when a data request is received from a host, determining a target cache space from free cache space in a cache, saving data corresponding to the data request to the target cache space, and responding to the data request include:

In the case where the data request is a write request, determining a target cache space from free cache space in the cache;

Write the data corresponding to the write request into the target cache space, generate a write request data block corresponding to the write request, and respond to the host.

In this embodiment, by separating the cache replacement process from the data request processing process, it is ensured that the free cache space in the cache can be directly used in the process of processing each write request, thereby reducing the processing delay of the write request.

In some optional implementations, releasing the cache space occupied by the data block to be cleared includes:

In the case where the data block to be cleared is a write request data block, determining whether the data of the data block to be cleared has been written into a preset storage medium;

If it has been written, delete the data block to be cleaned up in the data block processing queue;

If not written, the data of the data block to be cleared is written into a preset storage medium, and the data block to be cleared in the data block processing queue is deleted.

In some optional implementations, obtaining the cache occupancy level includes:

Enable the preset timer, and call the timer processing function when the preset timer duration is the preset duration;

Use the timer processing function to obtain the cache occupancy level.

In this embodiment, when the preset timer duration is the preset duration, the cache occupancy level is obtained, ensuring that the cache occupancy level is obtained in time and the cache replacement process is started, while avoiding excessive computing resources from being occupied by obtaining the cache occupancy level in real time.

In some optional implementations, obtaining the cache occupancy level includes:

Get the used cache space and total cache space of the cache;

The ratio of used cache space to total cache space is used as the cache occupancy watermark.

In a second aspect, the present invention provides a data request processing device, comprising:

An acquisition module is used to obtain the cache occupancy level;

A release module is used to determine the data blocks to be cleaned up and release the cache space occupied by the data blocks to be cleaned up when the cache occupancy level is higher than a preset threshold;

The processing module is used to determine the target cache space from the free cache space in the cache when receiving a data request from the host, save the data corresponding to the data request to the target cache space, and respond to the data request.

In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the data request processing method of the first aspect or any corresponding embodiment thereof by executing the computer instructions.

In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the data request processing method of the first aspect or any corresponding embodiment thereof.

In a fifth aspect, the present invention provides a computer program product, comprising computer instructions for causing a computer to execute the data request processing method of the first aspect or any corresponding embodiment thereof.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the related technologies, the drawings required for use in the specific embodiments or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

1 is a flow chart of processing a read request using a conventional solution according to an embodiment of the present invention;

FIG2 is a schematic flow chart of a method for processing a data request according to an embodiment of the present invention;

FIG3 is a schematic diagram of a data block processing queue according to an embodiment of the present invention;

FIG4 is a schematic diagram of a flow chart of processing a read request according to an embodiment of the present invention;

5 is a structural block diagram of a data request processing device according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention.

DETAILED DESCRIPTION

In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

DRAM used as cache in storage systems is more expensive than non-volatile storage devices such as HDD and SSD. Therefore, the DRAM capacity configured in the storage system is limited, and it is impossible to cache all data requests corresponding to the data in the DRAM. Therefore, in the process of processing data requests, when the DRAM storage space is full, if new data needs to be cached, it is necessary to replace the existing data in the DRAM to cache the new data. Currently, commonly used cache replacement algorithms include FIFO (First In First Out), LRU (Least Recently Used), LFU (Least Frequently Used), etc. The process of processing data requests in the current traditional solution is shown in Figure 1. Taking a read request processing process as an example, in the process of processing a read request, the read request is sent to the cache module to check whether it can hit the cache. If it can hit, the data is read from the cache and returned to the host. If it cannot hit the cache, it is necessary to read the data from the backend data disk and return the read data to the cache module to determine whether the cache space is full. If not, the read data is placed in the cache and then returned to the host. If so, according to the replacement algorithm, some data is invalidated to release the cache space. The read data is placed in the cache and then returned to the host. Similarly, for write requests, when data is written to the cache, if the cache space is full, it is also necessary to replace the existing data with the new data through the cache replacement algorithm.

In the above-mentioned traditional scheme, in the process of processing data requests, if data needs to be put into the cache and the cache space is full, it is necessary to use the cache replacement algorithm to replace the existing data in the cache and then store the new data. This process involves the processing of the cache replacement algorithm, the release of cache resources, and the application of cache resources for data requests. The time consumption of these processing flows is included in the processing time of the cache request, and the cache space is limited. It is normal for the cache space to be full during the use of the storage system. Therefore, every data request involving cache data needs to execute the cache replacement process during the processing process, which prolongs the processing delay of each data request and causes the system performance to degrade.

Based on the above content, an embodiment of the present invention provides a data request processing method, so that the cache replacement processing process is not included in the process of processing data requests. When the cache occupancy level is higher than the preset threshold, the data block to be cleared is determined, and the cache space occupied by the data block to be cleared is released. The above cache replacement processing time is not included in the time of processing data requests; and in the process of processing each data request, the free cache space in the cache can be directly used, which can reduce the response time of data request processing. In this way, the free cache space in the cache can be directly used in the process of processing each data request, the processing delay of the data request is reduced, and the read and write performance of the storage system is improved.

According to an embodiment of the present invention, a data request processing embodiment is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer device with data processing capabilities, such as a computer, a server, etc., and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

In this embodiment, a data request processing method is provided. FIG. 2 is a flow chart of the data request processing method according to an embodiment of the present invention. As shown in FIG. 2 , the flow chart includes the following steps:

Step S201, obtaining the cache occupancy level.

Specifically, DRAM is a cache in the storage system. The cache occupancy level is obtained. The cache occupancy level is, for example, the size of the used space in the DRAM divided by the total size of the DRAM. The cache occupancy level can be used to determine the usage of the DRAM and whether the DRAM has enough free cache space for the subsequent processing of data requests.

Step S202: when the cache occupancy level is higher than a preset threshold, determine the data blocks to be cleared, and release the cache space occupied by the data blocks to be cleared.

Specifically, the preset thresholds are, for example, 70%, 80%, 90%, etc., and the specific values are set according to actual needs. If the cache occupancy level is higher than the preset threshold, it means that there is insufficient free cache space in the DRAM for subsequent processing of data requests, and cache replacement is required.

The data blocks to be cleaned are determined in the DRAM, and the cache space occupied by the data blocks to be cleaned is released. It should be noted that during the data request processing in this embodiment, the data corresponding to the data request will be stored in the DRAM in the form of data blocks, so as to efficiently respond to the host sending the data request.

In addition, multiple preset thresholds may be set, and when the cache occupancy level is higher than different preset thresholds, different cache replacement speeds may be used.

Step S203, when a data request is received from the host, a target cache space is determined from the free cache space in the cache, data corresponding to the data request is saved in the target cache space, and the data request is responded to.

Specifically, a data request is, for example, an IO request. When a data request is received from a host, including a write request and a read request, a target cache space is determined from the free cache space in the DRAM. The size of the target cache space is greater than or equal to the data size of the data request, and the target cache space is preferably a continuous space, so that when responding to the host sending the data request, only one data transmission needs to be initiated, thereby improving the response speed. The data corresponding to the data request is saved in the target cache space in the form of a data block, and the data in the data block is returned to the host to achieve the response to the data request.

The data request processing method provided in this embodiment determines the data blocks to be cleared and releases the cache space occupied by the data blocks to be cleared when the cache occupancy level is higher than a preset threshold. The cache replacement process is not included in the process of processing data requests, and the cache replacement processing time is not included in the time of processing data requests. In addition, by timely releasing the cache space occupied by the cleared data blocks, the free cache space in the cache can be directly used in the process of processing each data request, which can reduce the response time of data request processing. The processing delay of data requests is reduced, and the read and write performance of the storage system is improved. The problem that in the process of processing data requests, if the cache space is full, replacing the existing data in the cache will increase the delay in processing data requests is solved.

In some optional implementations, before obtaining the cache occupancy watermark, the method further includes:

Get the number of threads that handle cache replacement tasks;

A first preset number of data block processing queues are generated according to the number of threads, wherein the data block processing queues are used to determine and release data blocks to be cleared.

Specifically, in the process of processing a data request in this embodiment, the data corresponding to the data request is stored in the DRAM in the form of a data block, so as to efficiently respond to the host sending the data request.

This embodiment stores the data blocks in the DRAM in multiple data block processing queues to facilitate the management of the data blocks, including: determining and releasing the data blocks to be cleaned. Therefore, it is necessary to first generate a first preset number of data block processing queues, and the process includes: obtaining the number of threads m for processing cache replacement tasks. According to the number of threads, a first preset number of data block processing queues is generated. The first preset number can be equal to the number of threads m, that is, there are as many bidirectional queues as there are threads processing cache replacement tasks. In addition, if necessary during actual use, the first preset number can also be an integer multiple of the number of threads m, for example: the first preset number is m, 2m, 3m, etc.

Taking the first preset number as the number of threads m as an example, this embodiment is described in conjunction with Figure 3. There are m threads processing cache replacement tasks, and m bidirectional queues are correspondingly created as data block processing queues. As shown in Figure 3, m task queues are created, including task queue 0, task queue 1, ..., task queue m-1, and a total of m task queues are created. The task queues are data block processing queues, and each task queue stores multiple cache data blocks.

In this embodiment, a first preset number of data block processing queues are generated according to the number of threads processing cache replacement tasks, and the data block processing queues are used to manage the data blocks, determine and release the data blocks to be cleaned, so that the free cache space in the cache can be directly used in the process of processing each data request, which can reduce the response time of data request processing.

In some optional implementations, after generating a first preset number of data block processing queues, the method further includes:

Determine the identity of the logical volume to which the data block in the cache belongs;

According to the identifier of the logical volume and the first preset number, a data block processing queue corresponding to the data block is determined, and the data block is put into the corresponding data block processing queue.

Specifically, an identifier of a logical volume (Logical Unit Number, LUN) to which the data block in the cache belongs is determined, wherein LUN is a logical unit number, which is a logical volume in a storage system.

Determine the identifier (LUN ID) of the logical volume to which the data block in the cache belongs. Taking the first preset number as the number of threads m as an example, which queue the data block in the cache is placed in is determined according to the LUN (logical volume) to which the cache data block belongs, and the calculation method can be: queue ID = LUN ID % m, % represents the remainder calculation. The data block processing queue ID corresponding to the data block is determined by the above method, for example: the remainder of m according to the number of the LUN to which the data belongs is the queue number, that is, the data of LUN 0 is placed in queue 0, the data of LUN 1 is placed in queue 1, ..., the data of LUN m-1 is placed in queue m-1, the data of LUN m is placed in queue 0, and so on. As shown in Figure 3, the data block processing queue corresponding to cache data blocks 0-1, cache data blocks 0-2, ..., cache data blocks 0-n is task queue 0, and cache data blocks 0-1, cache data blocks 0-2, ..., cache data blocks 0-n are placed in task queue 0. Other task queues are shown in Figure 3 and will not be repeated here.

The data block processing queue corresponding to the data block is determined according to the data block processing queue ID, and the data block is placed in the corresponding data block processing queue.

In this embodiment, the data block processing queue corresponding to the data block is determined, and the data block is placed in the corresponding data block processing queue. The data block is managed by the data block processing queue to facilitate cleaning of the data block and release of the cache space occupied by the data block.

In some optional implementations, after placing the data block into the corresponding data block processing queue, the method further includes:

Determining a first replacement priority of the data block;

According to the first replacement priority, sequence numbers of data blocks are generated in a first preset number of data block processing queues.

Specifically, in each data block processing queue, according to the corresponding cache replacement algorithm, the data block to be replaced first is placed at the head of the data block processing queue, and other data blocks are stored in a linked list in sequence according to the replacement order.

The replacement order can be determined according to the first replacement priority of the data block. For example, the first replacement priority of the data block in each data block processing queue is determined according to the time when the data block joins the data block processing queue. The smaller the joining time, the higher the first replacement priority; the first replacement priority of the data block is determined according to the usage frequency and hit rate of the data in the data block. During the business cycle, the lower the data usage frequency and the lower the hit rate of the data block, the higher the first replacement priority.

According to the first replacement priority, serial numbers of data blocks are generated in a first preset number of data block processing queues, wherein the higher the first replacement priority, the smaller and more forward the generated serial numbers are, and the subsequent data blocks with smaller serial numbers are more likely to be determined as data blocks to be cleaned; or, conversely, the higher the first replacement priority, the larger and more forward the generated serial numbers are, and the subsequent data blocks with larger serial numbers are more likely to be determined as data blocks to be cleaned.

In this embodiment, according to the first replacement priority, the sequence numbers of the data blocks are generated in the first preset number of data block processing queues, which is convenient for managing the data blocks, and the data blocks to be cleared are determined and released according to the sequence numbers, which is accurate and efficient.

In some optional implementations, when the cache occupancy level is higher than a preset threshold, determining the data block to be cleared includes:

When the cache occupancy level is higher than a first preset threshold and lower than a second preset threshold, data blocks with sequence numbers smaller than a first preset value in a first preset number of data block processing queues are used as data blocks to be cleared;

When the cache occupancy level is higher than the second preset threshold and lower than the third preset threshold, data blocks with sequence numbers smaller than the second preset value in the first preset number of data block processing queues are used as data blocks to be cleared;

When the cache occupancy level is higher than the third preset threshold and lower than the fourth preset threshold, data blocks with sequence numbers smaller than the third preset value in the first preset number of data block processing queues are used as data blocks to be cleared;

When the cache occupancy level is higher than a fourth preset threshold, data blocks with sequence numbers less than a fourth preset value in the first preset number of data block processing queues are taken as data blocks to be cleared.

Specifically, in order to prevent the cache replacement process from being included in the process of processing data requests, the cache replacement process is placed in the background for execution. In order to prevent the foreground process of processing data requests from being blocked due to the full DRAM cache space, the background cache replacement task cannot be started when the cache space is full. Therefore, a preset threshold is set. When the cache occupancy level is higher than the preset threshold, the cache replacement process is started.

This embodiment dynamically adjusts the cache replacement speed according to the preset threshold value exceeded by the cache occupancy level by setting different preset threshold values. The different preset threshold values include: a first preset threshold value, for example, 70%; a second preset threshold value, for example, 80%; a third preset threshold value, for example, 90%; a fourth preset threshold value, for example, 95%. The specific values of the above preset values can be adjusted according to actual needs and are not limited here. Take the first preset number as the number of threads m as an example.

When the cache occupancy level is higher than the first preset threshold and lower than the second preset threshold, it indicates that the DRAM cache space is insufficient and the cache replacement process needs to be started. The m threads for handling the cache replacement task simultaneously process the cache data in the m data block processing queues, and the data blocks with sequence numbers less than the first preset value in each data block processing queue are taken as data blocks to be cleaned. For example, the first preset value is 2, that is, the data block with sequence number 1 in each queue is taken as the data block to be cleaned. Each thread invalidates a data block at the head of the corresponding data block processing queue as the data block to be cleaned from the cache, releases the cache space of the data block to be cleaned, and ends this processing.

When the cache occupancy level is higher than the second preset threshold and lower than the third preset threshold, it indicates that the DRAM cache space is insufficient and a cache replacement process needs to be performed quickly. m threads for processing cache replacement tasks simultaneously process cache data in m data block processing queues, and use data blocks with sequence numbers less than the second preset value in each data block processing queue as data blocks to be cleaned. For example, the second preset value is 3, that is, data blocks with sequence numbers 1 and 2 in each queue are used as data blocks to be cleaned. When each thread processes this, it invalidates the first two data blocks in the queue from the corresponding queue, releases the cache space for the data blocks to be cleaned, and ends this processing.

When the cache occupancy level is higher than the third preset threshold and lower than the fourth preset threshold, it means that the DRAM cache space is very insufficient and the cache replacement process needs to be performed faster. m threads for processing cache replacement tasks simultaneously process the cache data in m data block processing queues, and use the data blocks with sequence numbers less than the third preset value in each data block processing queue as data blocks to be cleaned. For example, the third preset value is 5, that is, the data blocks with sequence numbers 1 to 4 in each queue are used as data blocks to be cleaned. When each thread processes this, it invalidates the first four data blocks in the queue from the corresponding queue, releases the cache space for the data blocks to be cleaned, and ends this processing.

When the cache occupancy level is higher than the fourth preset threshold, it means that the DRAM cache space is seriously insufficient and the cache replacement process needs to be performed at the fastest speed. m threads for processing cache replacement tasks simultaneously process the cache data in m data block processing queues, and take the data blocks with sequence numbers less than the fourth preset value in each data block processing queue as data blocks to be cleaned. For example: the fourth preset value is 9, that is, the data blocks with sequence numbers 1 to 8 in each queue are taken as data blocks to be cleaned. When each thread processes this, it invalidates the first eight data blocks in the queue from the corresponding queue, releases the cache space of the data blocks to be cleaned, and ends this processing.

In this embodiment, the cache occupancy level is compared with the first preset threshold to the fourth preset threshold, and the number of data blocks to be cleared in the data block processing queue is determined based on the comparison results, the speed of cache replacement is modified, and the computing resources of the system are reasonably utilized to ensure that the free cache space in the cache can be directly used during the processing of each data request.

In some optional implementations, in the process of releasing the data blocks to be cleared, in order to avoid directly deleting the data blocks to be cleared which may affect the subsequent user's read and write service needs, the data blocks to be cleared can be temporarily locked first, and the read and write service conditions for the next period of time can be obtained. If the read and write service needs of the user are not affected, the data blocks to be cleared can be deleted and the cache space of the data blocks to be cleared can be released. The specific process includes steps A1 to A4.

Step A1: Lock the determined data block to be cleared.

Specifically, after the data block to be cleaned is locked, data cannot be read from the data block to be cleaned and data cannot be written into the data block to be cleaned.

Step A2: determine whether the transmission bandwidth corresponding to the user decreases within a preset time period.

Specifically, a 5% error is allowed for determining whether the transmission bandwidth has decreased, that is, an impact of less than 5% can be regarded as an error. If the transmission bandwidth has not decreased within the preset time period, it can be determined that deleting the data block to be cleared will not affect the subsequent user's read and write service needs, and the data block to be cleared can be deleted, and the cache space of the data block to be cleared can be released.

Step A3: if the transmission bandwidth does not decrease within the preset time period, the data to be cleared in the data block processing queue is deleted, and the cache space of the data to be cleared is released.

Specifically, the preset time period is, for example, two weeks. If the transmission bandwidth does not decrease within the preset time period, it is determined that the user's read and write service efficiency is not affected, the data to be cleared in the data block processing queue is deleted, and the cache space of the data to be cleared is released. It should be noted that the preset time period can be set according to actual needs, for example, it can be longer or shorter.

Step A4: if the transmission bandwidth decreases within a preset time period, the data blocks to be cleared are unlocked and the data blocks to be cleared are re-determined.

Specifically, if the transmission bandwidth decreases by more than a threshold within a period of time, it is determined that locking the data block to be cleared will affect the user's read and write services, and the data block to be cleared is unlocked. Other data blocks are detected cyclically and the data block to be cleared is re-determined, so as to reclaim redundant cache space and maximize the utilization of cache resources.

In this embodiment, the data block to be cleaned is temporarily locked first, and the read and write business conditions in the next period of time are obtained. If it does not affect the user's read and write business needs, the data block to be cleaned is deleted and the cache space of the data block to be cleaned is released to maximize the utilization of cache resources.

In some optional implementations, after determining the data blocks to be cleared and releasing the cache space occupied by the data blocks to be cleared, the method further includes:

Determining a second replacement priority of remaining data blocks in the first preset number of data block processing queues;

According to the second replacement priority, the sequence numbers of the remaining data blocks are updated.

Specifically, after the data blocks to be cleaned are deleted from the data block processing queue and the cache space occupied by the data blocks to be cleaned is released, the sequence numbers of the data blocks in the data block processing queue are discontinuous. For example, in task queue 1 in Figure 3, cached data block 1-1 is deleted. At this time, the sequence numbers of the data blocks in task queue 1 start from 1-2, which is not conducive to the subsequent determination of the data blocks to be cleaned.

Therefore, the second replacement priority of the remaining data blocks in the first preset number of data block processing queues is re-determined, and the sequence numbers of the remaining data blocks are updated according to the second replacement priority. For example, the second replacement priority of the data block is the same as the first replacement priority, and both are generated using the time when the data block joins the data block processing queue. As shown in FIG3 , in task queue 1, cached data block 1-1 is deleted. At this time, the sequence numbers of the data blocks in task queue 1 start from 1-2, and the sequence number 1-2 is modified to 1-1, and the sequence number 1-3 is modified to 1-2, and so on. If the second replacement priority of the data block is different from the first replacement priority, the first replacement priority is generated using the time when the data block joins the data block processing queue, and the second replacement priority is generated using the usage frequency and hit rate of the data in the data block, then the sequence numbers of the remaining data blocks are directly regenerated according to the second replacement priority. The positions of the remaining data blocks in the data block processing queue are dynamically swapped according to the updated sequence numbers.

In some optional implementations, when a data request is received from a host, determining a target cache space from free cache space in a cache, saving data corresponding to the data request to the target cache space, and responding to the data request include:

In the case where the data request is a read request, if the data block corresponding to the read request does not exist in the cache, the target cache space is determined from the free cache space in the cache;

Acquire data corresponding to the read request from a preset storage medium, and write the data corresponding to the read request into a target cache space to generate a read request data block corresponding to the read request;

Returns the data in the read request data block to the host.

Specifically, in this embodiment, there is no need to process the processing logic of cache replacement in the process of processing the read request, and the target cache space can be directly determined from the free cache space in the DRAM.

Determine whether there is a data block corresponding to the read request in DRAM, that is, determine whether the read request hits the cache. If so, it is determined that the data read by the read request is in DRAM, so there is no need to read the data corresponding to the read request from storage media such as HDD and SSD. The data corresponding to the read request can be directly read from DRAM and returned to the host, reducing the response time of the read request.

If the data block corresponding to the read request does not exist in the cache, it is determined that the data read by the read request is not in the DRAM, and the target cache space is determined from the free cache space in the DRAM. The data corresponding to the read request is obtained from a preset storage medium, such as a non-volatile storage medium such as HDD or SSD that is slower than DRAM. After obtaining the data corresponding to the read request, the read data is written to the target cache space of the DRAM, and a read request data block corresponding to the read request is generated so that subsequent requests can hit the cache. Finally, the data in the read request data block is returned to the host.

The above process is shown in Figure 4. The read request is sent to the cache module to determine whether the read request hits the cache. If so, the data is read from the cache and returned to the host. If not, the data is read from the backend data disk and returned to the cache module. The read data is placed in the cache and then returned to the host, and the process ends.

In this embodiment, by separating the cache replacement process from the data request processing process, it is ensured that free cache space in the cache can be directly used in the process of processing each read request, thereby reducing the processing delay of the read request.

In some optional implementations, releasing the cache space occupied by the data block to be cleared includes:

In the case where the data block to be cleaned is a read request data block, the data block to be cleaned in the data block processing queue is deleted;

The positions of the remaining data blocks in the data block processing queue are swapped using a preset algorithm.

Specifically, when the data block to be cleared is a read request data block, the data block to be cleared in the data block processing queue can be directly deleted.

After the data blocks to be cleared are deleted from the data block processing queue and the cache space occupied by the data blocks to be cleared is released, the sequence numbers of the data blocks in the data block processing queue are discontinuous. Therefore, a preset algorithm is used to dynamically swap the positions of the remaining data blocks in the data block processing queue, and the sequence numbers of the remaining data blocks are updated. For example, the above-mentioned second replacement priority is used to update the sequence numbers of the remaining data blocks, and the positions of the remaining data blocks in the data block processing queue are dynamically swapped according to the updated sequence numbers.

In some optional implementations, when a data request is received from a host, determining a target cache space from free cache space in a cache, saving data corresponding to the data request to the target cache space, and responding to the data request include:

In the case where the data request is a write request, determining a target cache space from free cache space in the cache;

Write the data corresponding to the write request into the target cache space, generate a write request data block corresponding to the write request, and respond to the host.

Specifically, when the data request is a write request, the target cache space is determined from the free cache space in the DRAM. The size of the target cache space is greater than or equal to the data size of the write request, and the target cache space is preferably a continuous space. In this way, when writing the data of the write request to the target cache space, only one data transfer needs to be initiated, thereby improving the processing speed of the data request.

For write requests, the data of the write request is written into DRAM and the host data request processing is completed. The data written into DRAM is flushed to non-volatile storage media such as HDD or SSD, which are slower than DRAM, in the background, reducing the system's response time to write requests. Therefore, the data corresponding to the write request is written into the target cache space, the write request data block corresponding to the write request is generated, and the host is responded to.

In this embodiment, by separating the cache replacement process from the data request processing process, it is ensured that the free cache space in the cache can be directly used in the process of processing each write request, thereby reducing the processing delay of the write request.

In some optional implementations, releasing the cache space occupied by the data block to be cleared includes:

In the case where the data block to be cleared is a write request data block, determining whether the data of the data block to be cleared has been written into a preset storage medium;

If it has been written, delete the data block to be cleaned up in the data block processing queue;

If not written, the data of the data block to be cleared is written into a preset storage medium, and the data block to be cleared in the data block processing queue is deleted.

Specifically, the data written to DRAM is flushed to a preset storage medium in the background, such as a non-volatile storage medium such as HDD or SSD that is slower than DRAM. The process of background flushing is carried out simultaneously with the process of releasing the cache space occupied by the data block to be cleared. Therefore, when a certain write request data block is confirmed as a data block to be cleared, the data of the write request data block has not been flushed to a non-volatile storage medium such as HDD or SSD. If the write request data block is directly deleted, data loss will result.

Determine whether the data of the data block to be cleaned has been written into the preset storage medium. If so, directly delete the data block to be cleaned in the data block processing queue. If not, write the data of the data block to be cleaned into the preset storage medium and then delete the data block to be cleaned in the data block processing queue.

In some optional implementations, obtaining the cache occupancy level includes:

Enable the preset timer, and call the timer processing function when the preset timer duration is the preset duration;

Use the timer processing function to obtain the cache occupancy level.

Specifically, if the cache occupancy level is obtained in real time, it will occupy too much computing resources of the system. Therefore, a timer can be set to obtain the cache occupancy level once every certain period of time to determine whether a cache replacement process is needed.

Enable the preset timer, for example, a 100ms timer. The preset duration is, for example, 100ms. When the preset timer duration is the preset duration, call the timer processing function. In the timer processing function, get the cache occupancy level and determine whether the current cache occupancy level has reached the threshold, for example, 70%. If it has not reached, do nothing. If it has reached, start replacing the data in the cache, that is, invalidate the corresponding data and release the corresponding cache space.

In this embodiment, when the preset timer duration is the preset duration, the cache occupancy level is obtained, ensuring that the cache occupancy level is obtained in time and the cache replacement process is started, while avoiding excessive computing resources from being occupied by obtaining the cache occupancy level in real time.

In some optional implementations, obtaining the cache occupancy level includes:

Get the used cache space and total cache space of the cache;

The ratio of used cache space to total cache space is used as the cache occupancy watermark.

Specifically, in order to prevent the cache replacement process from being included in the process of processing data requests, the cache replacement process is placed in the background for execution. In order to prevent the foreground process of processing data requests from being blocked due to the full DRAM cache space, the background cache replacement task cannot be started when the cache space is full. Therefore, a preset threshold is set. When the cache occupancy level is higher than the preset threshold, the cache replacement process is started.

DRAM is the cache in the storage system. Get the cache occupancy level. For example, the cache occupancy level is the used cache space of DRAM divided by the total cache space of DRAM. The used cache space is the sum of the cache spaces of all data blocks in DRAM. The cache occupancy level can be used to determine the usage of DRAM and whether DRAM has enough free cache space for the subsequent data request processing process.

In this embodiment, a data request processing device is also provided, which is used to implement the above embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and/or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

This embodiment provides a data request processing device, as shown in FIG5 , including:

Acquisition module 501, used to acquire the cache occupancy level;

A release module 502 is used to determine the data blocks to be cleared and release the cache space occupied by the data blocks to be cleared when the cache occupancy level is higher than a preset threshold;

The processing module 503 is used to determine the target cache space from the free cache space in the cache when receiving a data request from the host, save the data corresponding to the data request to the target cache space, and respond to the data request.

In some optional implementations, before obtaining the cache occupancy water level, the device is used to:

Get the number of threads that handle cache replacement tasks;

A first preset number of data block processing queues are generated according to the number of threads, wherein the data block processing queues are used to determine and release data blocks to be cleared.

In some optional implementations, after generating a first preset number of data block processing queues, the apparatus is further configured to:

Determine the identity of the logical volume to which the data block in the cache belongs;

According to the identifier of the logical volume and the first preset number, a data block processing queue corresponding to the data block is determined, and the data block is put into the corresponding data block processing queue.

In some optional implementations, after placing the data block into the corresponding data block processing queue, the device is further configured to:

Determining a first replacement priority of the data block;

According to the first replacement priority, sequence numbers of data blocks are generated in a first preset number of data block processing queues.

In some optional implementations, when the cache occupancy level is higher than a preset threshold, the release module 502 determines the data block to be cleared, including:

When the cache occupancy level is higher than a first preset threshold and lower than a second preset threshold, data blocks with sequence numbers smaller than a first preset value in a first preset number of data block processing queues are used as data blocks to be cleared;

When the cache occupancy level is higher than the second preset threshold and lower than the third preset threshold, data blocks with sequence numbers smaller than the second preset value in the first preset number of data block processing queues are used as data blocks to be cleared;

When the cache occupancy level is higher than the third preset threshold and lower than the fourth preset threshold, data blocks with sequence numbers smaller than the third preset value in the first preset number of data block processing queues are used as data blocks to be cleared;

When the cache occupancy level is higher than a fourth preset threshold, data blocks with sequence numbers less than a fourth preset value in the first preset number of data block processing queues are taken as data blocks to be cleared.

In some optional implementations, after determining the data blocks to be cleared and releasing the cache space occupied by the data blocks to be cleared, the release module 502 is further used to:

Determining a second replacement priority of remaining data blocks in the first preset number of data block processing queues;

According to the second replacement priority, the sequence numbers of the remaining data blocks are updated.

In some optional implementations, when the processing module 503 receives a data request from the host, it determines the target cache space from the free cache space in the cache, saves the data corresponding to the data request to the target cache space, and responds to the data request, including:

In the case where the data request is a read request, if the data block corresponding to the read request does not exist in the cache, the target cache space is determined from the free cache space in the cache;

Acquire data corresponding to the read request from a preset storage medium, and write the data corresponding to the read request into a target cache space to generate a read request data block corresponding to the read request;

Returns the data in the read request data block to the host.

In some optional implementations, the processing module 503 releases the cache space occupied by the data block to be cleared, including:

In the case where the data block to be cleaned is a read request data block, the data block to be cleaned in the data block processing queue is deleted;

The positions of the remaining data blocks in the data block processing queue are swapped using a preset algorithm.

In some optional implementations, when the processing module 503 receives a data request from the host, it determines the target cache space from the free cache space in the cache, saves the data corresponding to the data request to the target cache space, and responds to the data request, including:

In the case where the data request is a write request, determining a target cache space from free cache space in the cache;

Write the data corresponding to the write request into the target cache space, generate a write request data block corresponding to the write request, and respond to the host.

In some optional implementations, the processing module 503 releases the cache space occupied by the data block to be cleared, including:

In the case where the data block to be cleared is a write request data block, determining whether the data of the data block to be cleared has been written into a preset storage medium;

If it has been written, delete the data block to be cleaned up in the data block processing queue;

If not written, the data of the data block to be cleared is written into a preset storage medium, and the data block to be cleared in the data block processing queue is deleted.

In some optional implementations, the acquisition module 501 acquires the cache occupancy level, including:

Enable the preset timer, and call the timer processing function when the preset timer duration is the preset duration;

Use the timer processing function to obtain the cache occupancy level.

In some optional implementations, the acquisition module 501 acquires the cache occupancy level, including:

Get the used cache space and total cache space of the cache;

The ratio of used cache space to total cache space is used as the cache occupancy watermark.

The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

The data request processing device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and/or other devices that can provide the above functions.

An embodiment of the present invention further provides a computer device having the data request processing device shown in FIG. 5 .

Please refer to Figure 6, which is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention. As shown in Figure 6, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. The various components are connected to each other using different buses for communication, and can be installed on a common motherboard or installed in other ways as needed. The processor can process instructions executed in the computer device, including instructions stored in or on the memory to display graphical information of the GUI on an external input/output device (such as a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and/or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). In Figure 6, a processor 10 is taken as an example.

The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include an integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

The memory 20 stores instructions executable by at least one processor 10, so that at least one processor 10 executes the method shown in the above embodiment.

The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

The computer device further comprises a communication interface 30 for the computer device to communicate with other devices or a communication network.

The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and/or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of the computer program instruction in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined in this application.

Claims (15)

1. A data request processing method, characterized in that the method comprises: Get the cache occupancy level; When the cache occupancy level is higher than a preset threshold, determining a data block to be cleared, and releasing the cache space occupied by the data block to be cleared; In case of receiving a data request from the host, a target cache space is determined from free cache space in the cache, data corresponding to the data request is saved in the target cache space, and the data request is responded to. 2. The method according to claim 1, characterized in that before obtaining the cache occupancy watermark, the method further comprises: Get the number of threads that handle cache replacement tasks; A first preset number of data block processing queues are generated according to the number of threads, wherein the data block processing queues are used to determine and release the data blocks to be cleared. 3. The method according to claim 2, characterized in that after generating the first preset number of data block processing queues, the method further comprises: Determining an identifier of a logical volume to which the data block in the cache belongs; According to the identifier of the logical volume and the first preset number, a data block processing queue corresponding to the data block is determined, and the data block is put into the corresponding data block processing queue. 4. The method according to claim 3, characterized in that after placing the data block into the corresponding data block processing queue, the method further comprises: determining a first replacement priority of the data block; According to the first replacement priority, sequence numbers of the data blocks are generated in the first preset number of data block processing queues. 5. The method according to claim 4, characterized in that when the cache occupancy level is higher than a preset threshold, determining the data block to be cleared comprises: When the cache occupancy level is higher than a first preset threshold and lower than a second preset threshold, data blocks with sequence numbers smaller than a first preset value in the first preset number of data block processing queues are used as the data blocks to be cleared; When the cache occupancy level is higher than the second preset threshold and lower than the third preset threshold, the data blocks with sequence numbers smaller than the second preset value in the first preset number of data block processing queues are used as the data blocks to be cleared; When the cache occupancy level is higher than a third preset threshold and lower than a fourth preset threshold, the data blocks with sequence numbers smaller than the third preset value in the first preset number of data block processing queues are used as the data blocks to be cleared; When the cache occupancy level is higher than the fourth preset threshold, data blocks with sequence numbers less than a fourth preset value in the first preset number of data block processing queues are used as the data blocks to be cleared. 6. The method according to claim 4, characterized in that after determining the data blocks to be cleared and releasing the cache space occupied by the data blocks to be cleared, the method further comprises: Determining a second replacement priority of remaining data blocks in the first preset number of data block processing queues; According to the second replacement priority, the sequence numbers of the remaining data blocks are updated. 7. The method according to claim 2, wherein when a data request is received from a host, determining a target cache space from free cache space in a cache, saving data corresponding to the data request to the target cache space, and responding to the data request comprises: In the case where the data request is a read request, if the data block corresponding to the read request does not exist in the cache, determining the target cache space from free cache space in the cache; Acquire data corresponding to the read request from a preset storage medium, and write the data corresponding to the read request into the target cache space to generate a read request data block corresponding to the read request; The data in the read request data block is returned to the host. 8. The method according to claim 7, wherein releasing the cache space occupied by the data block to be cleared comprises: In the case where the data block to be cleared is the read request data block, deleting the data block to be cleared in the data block processing queue; The positions of the remaining data blocks in the data block processing queue are swapped using a preset algorithm. 9. The method according to claim 2, wherein when a data request is received from a host, determining a target cache space from free cache space in a cache, saving data corresponding to the data request to the target cache space, and responding to the data request comprises: In the case where the data request is a write request, determining a target cache space from free cache space in the cache; The data corresponding to the write request is written into the target cache space, a write request data block corresponding to the write request is generated, and the host is responded to. 10. The method according to claim 9, wherein releasing the cache space occupied by the data block to be cleared comprises: In the case where the data block to be cleared is the write request data block, determining whether the data of the data block to be cleared has been written into a preset storage medium; If it has been written, deleting the data block to be cleared in the data block processing queue; If not written, the data of the data block to be cleared is written into a preset storage medium, and the data block to be cleared in the data block processing queue is deleted. 11. The method according to claim 1, wherein obtaining the cache occupancy level comprises: Enable a preset timer, and when the duration of the preset timer is the preset duration, call a timer processing function; The timer processing function is used to obtain the cache occupancy level. 12. The method according to claim 1 or 11, characterized in that the obtaining of the cache occupancy level comprises: Obtaining the used cache space and the total cache space of the cache; The ratio of the used cache space to the total cache space is used as the cache occupancy watermark. 13. A data request processing device, characterized in that the device comprises: An acquisition module is used to obtain the cache occupancy level; A release module, used to determine the data blocks to be cleared and release the cache space occupied by the data blocks to be cleared when the cache occupancy level is higher than a preset threshold; The processing module is used to determine the target cache space from the free cache space in the cache when receiving a data request from the host, save the data corresponding to the data request to the target cache space, and respond to the data request. 14. A computer device, comprising: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the data request processing method according to any one of claims 1 to 12 by executing the computer instructions. 15. A computer-readable storage medium, characterized in that computer instructions are stored on the computer-readable storage medium, and the computer instructions are used to enable a computer to execute the data request processing method according to any one of claims 1 to 12.