CN118897182A - Clock fault detection method, clock fault detection circuit and integrated circuit system - Google Patents

Abstract

The invention discloses a clock fault detection method, a clock fault detection circuit and an integrated circuit system, wherein the clock fault detection method comprises the following steps: acquiring a first clock signal and a second clock signal; counting the periods of the first clock signal to obtain a first clock count value, and counting the periods of the second clock signal to obtain a second clock count value; when the first clock count value or the second clock count value reaches a handshake count threshold, the first clock signal and the second clock signal are controlled to handshake; if the handshake between the first clock signal and the second clock signal fails, determining that at least one of the first clock signal and the second clock signal has a fault. The method judges whether the clock signals are normal or not by adopting a mode of handshaking the first clock signals and the second clock signals, so that mutual detection of the first clock signals and the second clock signals is realized, and the accuracy of the first clock signals and the second clock signals is ensured.

Description

Clock fault detection method, clock fault detection circuit and integrated circuit system

Technical Field

The present invention relates to the field of clock technology, and in particular to a clock fault detection method, a clock fault detection circuit and an integrated circuit system.

Background Art

In the related art, for an integrated circuit system, the clock signal is the benchmark for many logic signals. Confirming whether the clock signal works correctly directly determines the performance of the entire hardware system. Therefore, how to detect whether the clock is faulty is an urgent problem to be solved.

Summary of the invention

The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one object of the present invention is to provide a clock failure detection method, which determines whether the clock signal is normal by handshaking the first clock signal with the second clock signal, thereby realizing mutual inspection of the first clock signal and the second clock signal, and ensuring the accuracy of the first clock signal and the second clock signal.

A second objective of the present invention is to provide a clock failure detection circuit.

A third objective of the present invention is to provide an integrated circuit system.

In order to solve the above problems, an embodiment of the first aspect of the present invention provides a clock fault detection method, including: acquiring a first clock signal and a second clock signal; counting the period of the first clock signal to obtain a first clock count value, and counting the period of the second clock signal to obtain a second clock count value; when the first clock count value or the second clock count value reaches a handshake count threshold, controlling the first clock signal to handshake with the second clock signal; if the handshake between the first clock signal and the second clock signal fails, determining that at least one of the first clock signal and the second clock signal has a fault.

According to the clock failure detection method of the embodiment of the present invention, when the first clock count value or the second clock count value reaches the handshake count threshold, the first clock signal and the second clock signal are triggered to perform a handshake operation. Since the handshake failure will occur when any clock signal fails, if it is detected that the handshake failure between the first clock signal and the second clock signal occurs, it can be determined that at least one of the first clock signal and the second clock signal has a fault. Therefore, by using the method of handshaking between the first clock signal and the second clock signal, it is possible to determine whether the two clock signals are normal, thereby realizing mutual inspection of the first clock signal and the second clock signal, thereby ensuring the accuracy of the first clock signal and the second clock signal.

In some embodiments, controlling the first clock signal to handshake with the second clock signal includes: obtaining a handshake signal of a first clock domain to which the first clock signal belongs; synchronizing the handshake signal to a second clock domain to which the second clock signal belongs, and generating a first signal; synchronizing the first signal to the first clock domain, and generating a second signal to clear the first clock count value and the second clock count value.

In some embodiments, if the handshake between the first clock signal and the second clock signal fails, it is determined that at least one of the first clock signal and the second clock signal has a fault, including: if the first clock count value and the second clock count value are not cleared, the handshake between the first clock signal and the second clock signal fails; it is determined that at least one of the first clock signal and the second clock signal has a stop fault.

In some embodiments, a first counter is used to count the period of the first clock signal to obtain a first clock count value, and a second counter is used to count the period of the second clock signal to obtain a second clock count value; the first clock count value and the second clock count value are not cleared to zero, including: the first clock count value is greater than an overflow threshold of the first counter and/or the second clock count value is greater than an overflow threshold of the second counter.

In some embodiments, the clock fault detection method further includes: if the first clock count value is greater than an overflow threshold of the first counter, determining that the second clock signal has a stop fault.

In some embodiments, the clock fault detection method further includes: if the second clock count value is greater than an overflow threshold of the second counter, determining that the first clock signal has a stop fault.

In some embodiments, the clock fault detection method also includes: obtaining a first clock count theoretical value range; latching the first clock count value in response to the first signal; if the first clock count value exceeds the first clock count theoretical value range, determining that the first clock signal has a clock deviation fault.

In some embodiments, the first clock domain and the second clock domain are different clock domains, and obtaining the first clock count theoretical value range includes: obtaining a first clock cycle corresponding to the first clock signal and a second clock cycle corresponding to the second clock signal; obtaining an upper limit value of the first clock count theoretical value range according to the handshake count threshold, the first clock cycle, the second clock cycle, the first allowable count deviation value corresponding to the first clock signal, the second allowable count deviation value corresponding to the second clock signal, and the upper limit value of the cross-time domain deviation range; obtaining a lower limit value of the first clock count theoretical value range according to the handshake count threshold, the first clock cycle, the second clock cycle, the first allowable count deviation value corresponding to the first clock signal, the second allowable count deviation value corresponding to the second clock signal, and the lower limit value of the cross-time domain deviation range.

In some embodiments, the clock fault detection method also includes: obtaining a second clock count theoretical value range; latching the second clock count value in response to the first signal; if the second clock count value exceeds the second clock count theoretical value range, determining that the second clock signal has a clock deviation fault.

In some embodiments, the first clock domain and the second clock domain are different clock domains, and obtaining the second clock count theoretical value range includes: obtaining a first clock cycle corresponding to the first clock signal and a second clock cycle corresponding to the second clock signal; obtaining an upper limit value of the second clock count theoretical value range according to the handshake count threshold, the first clock cycle, the second clock cycle, the first allowable count deviation value corresponding to the first clock signal, the second allowable count deviation value corresponding to the second clock signal, and the upper limit value of the cross-time domain deviation range; obtaining a lower limit value of the second clock count theoretical value range according to the handshake count threshold, the first clock cycle, the second clock cycle, the first allowable count deviation value corresponding to the first clock signal, the second allowable count deviation value corresponding to the second clock signal, and the lower limit value of the cross-time domain deviation range.

In some embodiments, the upper limit value of the first clock count theoretical value range or the second clock count theoretical value range is obtained by the following formula:

ρ1＝3*T _detected

Wherein, ρ1 is the upper limit value of the cross-time domain deviation range, MAX is the upper limit value of the first clock count theoretical value range or the second clock count theoretical value range, N _ref is the handshake count threshold, T _ref is the first clock cycle, T _detected is the second clock cycle, p _ref % is the first allowable count deviation value, and p _detected % is the second allowable count deviation value;

In some embodiments, the lower limit value of the first clock count theoretical value range is obtained by the following formula:

ρ2＝2*T _detected

Among them, ρ2 is the upper limit value of the cross-time domain deviation range, and MIN is the lower limit value of the first clock count theoretical value range or the second clock count theoretical value range.

A second aspect of the present invention provides a clock fault detection circuit, comprising: a first counter, the first counter being used to count with a period of a first clock signal to obtain a first clock count value; a second counter, the second counter being used to count with a period of a second clock signal to obtain a second clock count value; a handshake module, the handshake module being connected to the first counter and the second counter, the handshake module being used to control the first clock signal to handshake with the second clock signal when the first clock count value or the second clock count value reaches a handshake count threshold; and a signal processing module being used to determine that at least one of the first clock signal and the second clock signal has a fault when the handshake between the first clock signal and the second clock signal fails.

According to the clock fault detection circuit of the embodiment of the present invention, when the first clock count value or the second clock count value reaches the handshake count threshold, the first clock signal and the second clock signal are triggered to perform a handshake operation. Since the handshake failure will occur when any clock signal fails, if it is detected that the handshake failure between the first clock signal and the second clock signal occurs, it can be determined that at least one of the first clock signal and the second clock signal has a fault. Therefore, by using the method of handshaking between the first clock signal and the second clock signal, it is determined whether the two clock signals are normal, thereby realizing mutual inspection of the first clock signal and the second clock signal, and ensuring the accuracy of the first clock signal and the second clock signal.

In some embodiments, the first counter is also used to output a handshake signal when the first clock count value reaches a handshake count threshold; the handshake module includes: a first handshake unit, the first handshake unit is connected to the first counter, the first handshake unit is used to obtain a handshake signal of a first clock domain to which the first clock signal belongs, and synchronize the handshake signal to a second clock domain to which the second clock signal belongs, and generate a first signal; a second handshake unit, the second handshake unit is connected to the first handshake unit, the first counter, and the second counter, the second handshake unit is used to synchronize the first signal to the first clock domain, and generate a second signal to clear the first clock count value and the second clock count value.

In some embodiments, the signal processing mold body is used to determine that at least one of the first clock signal and the second clock signal has an oscillation stop failure if the first clock count value and the second clock count value are not cleared, and the handshake between the first clock signal and the second clock signal fails.

In some embodiments, it also includes: a first watchdog, which is connected to the first counter and the signal processing module, and the first watchdog is used to determine whether the first clock count value is greater than the overflow threshold of the first counter; the signal processing module is also used to determine that the second clock signal has a stop fault when the first clock count value is greater than the overflow threshold of the first counter.

In some embodiments, it also includes: a second watchdog, which is connected to the second counter and the signal processing module, and the second watchdog is used to determine whether the second clock count value is greater than the overflow threshold of the second counter; the signal processing module is also used to determine that the first clock signal has a stop fault when the second clock count value is greater than the overflow threshold of the second counter.

In some embodiments, it also includes: a first latch module, which is connected to the first timer and the first handshake unit, and is used to latch the first clock count value in response to the first signal; a first comparison module, which is connected to the first latch module and the signal processing module, and is used to determine whether the first clock count value meets the first clock count theoretical value range and output a first comparison result; the signal processing module is also used to determine that when the second clock count value exceeds the first clock count theoretical value range based on the first comparison result, it is determined that the first clock signal has a clock deviation fault.

In some embodiments, it also includes: a second latch module, which is connected to the second timer and the first handshake unit, and is used to latch the second clock count value in response to the first signal; a second comparison module, which is connected to the second latch module and the signal processing module, and is used to determine whether the second clock count value meets the second clock count theoretical value range and output a second comparison result; the signal processing module is also used to determine that when the second count value exceeds the second clock count theoretical value range according to the second comparison result, it is determined that there is a clock deviation fault in the second clock signal.

An embodiment of the third aspect of the present invention provides an integrated circuit system, comprising: a first clock circuit, used to generate a first clock signal; a second clock circuit, used to generate a second clock signal; the clock fault detection circuit described in the above embodiment, wherein the clock fault detection circuit is connected to the first clock circuit and the second clock circuit, and is used to perform fault detection on the first clock signal or the second clock signal.

According to the integrated circuit system of the embodiment of the present invention, by adopting the clock fault detection circuit of the above embodiment, the first clock signal and the second clock signal are handshaked to determine whether the clock signal is normal, thereby realizing the mutual inspection of the first clock signal and the second clock signal, and ensuring the accuracy of the first clock signal and the second clock signal. Additional aspects and advantages of the present invention will be partially given in the following description, and part will become obvious from the following description, or be understood through the practice of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and/or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

FIG1 is a flow chart of a clock failure detection method according to an embodiment of the present invention;

FIG2 is a timing diagram of a second clock having a oscillation stop failure according to an embodiment of the present invention;

FIG3 is a timing diagram of a first clock having an oscillation stop failure according to an embodiment of the present invention;

FIG4 is a timing diagram of a second clock having a deviation fault according to an embodiment of the present invention;

FIG5 is a schematic diagram of a clock failure detection circuit according to an embodiment of the present invention;

FIG. 6 is a structural block diagram of an integrated circuit system according to an embodiment of the present invention.

Reference numerals:

Clock failure detection circuit 100; integrated circuit system 200;

First counter 1; second counter 2; handshake module 3; second latch module 5; second comparison module 6; signal processing module 7;

The first handshake unit 31 ; the second handshake unit 32 ; the first watchdog 41 ; the second watchdog 42 .

DETAILED DESCRIPTION

Embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention are described in detail below.

In order to solve the above problems, an embodiment of the first aspect of the present invention provides a clock fault detection method, which uses the method to determine whether the clock signal is normal by handshaking the first clock signal with the second clock signal, thereby realizing mutual checking of the first clock signal and the second clock signal, and ensuring the accuracy of the first clock signal and the second clock signal.

As shown in FIG. 1 , the clock failure detection method according to the embodiment of the present invention includes steps S1 to S3 .

Step S1, obtaining a first clock signal and a second clock signal.

Specifically, the first counter obtains a first clock signal generated by a first clock, and the second counter obtains a second clock signal generated by a second clock.

Step S2: using a first counter to count the period of the first clock signal to obtain a first clock count value, and using a second counter to count the period of the second clock signal to obtain a second clock count value.

Exemplarily, the first counter performs free cycle counting on the period of the first clock signal generated by the first clock to obtain a first clock count value, and the second counter performs free cycle counting on the period of the second clock signal generated by the second clock to obtain a second clock count value. As shown in FIG2 , the space interval between two adjacent rising edges of the first clock signal is taken as a period to count the number of periods of the first clock signal to obtain the first clock count value; the space interval between two adjacent rising edges of the second clock signal is taken as a period to count the number of periods of the second clock signal to obtain the second clock count value.

Step S3, when the first clock count value or the second clock count value reaches the handshake count threshold, control the first clock signal to handshake with the second clock signal.

Step S4: if the handshake between the first clock signal and the second clock signal fails, it is determined that at least one of the first clock signal and the second clock signal has a fault.

Specifically, the clock fault detection method of the present application introduces two clocks, namely a first clock and a second clock. When the second clock is fault-detected, the second clock is used as the clock to be detected, and the first clock is used as the reference clock. Conversely, when the first clock is fault-detected, the first clock is used as the clock to be detected, and the second clock is used as the reference clock. There is no limitation on this. The first clock and the second clock can be in the same clock domain or in different clock domains. There is no limitation on this.

The following takes the second clock as the clock to be detected, the first clock as the reference clock, and the first clock and the second clock in different clock domains as an example for explanation, and performs a cross-time domain handshake between the time domain where the first clock is located and the time domain where the second clock is located. In this regard, it can be understood that, when the first clock signal and the second clock signal are both working normally, the two clock signals can successfully complete the cross-time domain handshake action, and if at least one of the first clock signal and the second clock signal has a stop failure, the faulty clock cannot output the clock signal, and the two clock signals cannot complete the cross-time domain handshake action, that is, the cross-time domain handshake between the two clock signals fails. Based on this, in this application, whether the first clock signal or the second clock signal is faulty is determined by the handshake result of the first clock signal and the second clock signal.

According to the clock failure detection method of the embodiment of the present invention, when the first clock count value or the second clock count value reaches the handshake count threshold, the first clock signal and the second clock signal are triggered to perform a handshake operation. Since the handshake failure will occur when any clock signal fails, if it is detected that the handshake failure between the first clock signal and the second clock signal occurs, it can be determined that at least one of the first clock signal and the second clock signal has a fault. Therefore, by using the method of handshaking between the first clock signal and the second clock signal, it is possible to determine whether the two clock signals are normal, thereby realizing mutual inspection of the first clock signal and the second clock signal, thereby ensuring the accuracy of the first clock signal and the second clock signal.

In some embodiments, controlling the first clock signal to handshake with the second clock signal includes: obtaining a handshake signal of a first clock domain to which the first clock signal belongs; synchronizing the handshake signal to a second clock domain to which the second clock signal belongs, and generating a first signal; synchronizing the first signal to the first clock domain, and generating a second signal to clear the first clock count value and the second clock count value. In this way, the handshake action is completed between the first clock domain where the first clock is located and the second clock domain where the second clock is located, triggering the first clock to clear the first clock count value, and the second clock to clear the second clock count value, so as to clear the first clock count value and the second clock count value.

In some embodiments, if the handshake between the first clock signal and the second clock signal fails, it is determined that at least one of the first clock signal and the second clock signal has a fault, including: if the first clock count value and the second clock count value are not cleared, the handshake between the first clock signal and the second clock signal fails; and it is determined that at least one of the first clock signal and the second clock signal has a stop fault. That is to say, only when both the first clock signal and the second clock signal do not have a stop fault, can the first counter and the second counter be cleared at the same time. Therefore, if the first clock count value and the second clock count value are not cleared, the handshake between the first clock signal and the second clock signal fails, and it is determined that at least one of the first clock signal and the second clock signal has a stop fault. If the first clock signal has a stop oscillation fault, the first counter cannot count, and the first counter cannot output the handshake signal, and then after a chain reaction, the second signal will become invalid, and the second counter will not perform the reset action, which means that the handshake of the first clock signal and the second clock signal has failed. For example, if the second clock signal has a stop oscillation fault, the second counter cannot count, and the first counter will not perform the reset action, and then after a chain reaction, the second signal will become invalid, which means that the handshake of the first clock signal and the second clock signal has failed. Based on this, when it is determined that the first clock count value and the second clock count value are not reset, it can be determined that the handshake of the first clock signal and the second clock signal has failed.

In some embodiments, the first clock count value and the second clock count value are not cleared, including: the first clock count value is greater than the overflow threshold of the first counter and/or the second clock count value is greater than the overflow threshold of the second counter. That is to say, when the first clock signal and the second clock signal are both normal, the first counter and the second counter can complete the clearing action, and then the first clock count value and/or the second clock count value will not exceed the count overflow threshold. However, as shown in FIG2, when the second clock signal has a fault, the handshake between the first clock signal and the second clock signal will fail, and the second counter will not have a count value at this time, and the first counter will not perform the clearing action, so the first counter will continue to count until the first clock count value is greater than the overflow threshold of the first counter; and/or, when the first clock signal has a fault, the handshake between the first clock signal and the second clock signal will fail, and the first counter will not have a count value at this time, and the second counter will not perform the clearing action, so the second counter will continue to count until the second clock count value is greater than the overflow threshold of the second counter.

In some embodiments, the clock fault detection method further includes: if the first clock count value is greater than the overflow threshold of the first counter, it is determined that the second clock signal has a stop oscillation fault. That is to say, when the first clock signal and the second clock signal are both normal, the handshake can be successfully performed, and the first counter and the second counter can complete the reset action, and then the first clock count value will not exceed the overflow threshold. However, as shown in FIG2, when the second clock signal has a stop oscillation fault, the handshake of the two clock signals will fail, and at this time the second counter will not have a clock count value, and the first counter will not perform the reset action. Therefore, the first counter will continue to count until it exceeds the overflow threshold. Therefore, when it is determined that the first clock count value is greater than the overflow threshold of the first counter, it can be known that the second clock signal has a stop oscillation fault.

Among them, because two clocks are used to perform cross-time domain handshake to initiate the clearing operation, there is a deviation between the clearing work and the latching action of the second counter. Therefore, in this application, the overflow threshold of the first counter is set to NUMB _ovf *T _ref , wherein NUMB _ovf is the theoretical overflow threshold of the first counter, T _ref is the first clock cycle of the first clock, and the first count value can be expressed as N _ref *T _ref +3*T _ref +3*T _detected , wherein N _ref is the first count value, and T _detected is the second clock cycle. Therefore, if N _ref *T _ref +3*T _ref +3*T _detected <NUMB _ovf *T _ref , it is determined that the second clock does not have a stop fault.

In some embodiments, the clock fault detection method further includes: if the second clock count value is greater than the overflow threshold of the second counter, it is determined that the first clock signal has a stop oscillation fault. That is to say, when the first clock signal and the second clock signal are both normal, the handshake can be successful, the first counter and the second counter can complete the reset action, and then the second clock count value will not exceed the overflow threshold. However, as shown in FIG3, when the first clock signal has a stop oscillation fault, the handshake of the two clock signals will fail, and at this time the first counter will not have a clock count value, and the second counter will not perform the reset action. Therefore, the second counter will continue to count until it exceeds the overflow threshold. Therefore, when it is determined that the second clock count value is greater than the overflow threshold of the second counter, it can be known that the first clock signal has a stop oscillation fault.

Among them, because two clock signals are used to perform cross-time domain handshake to initiate a clearing operation, there is a deviation between the clearing work and the latching action of the second counter. Therefore, in this application, the overflow threshold of the second counter is set to NUMD _ovf *T _ref , wherein NUMD _ovf is the theoretical overflow threshold of the second counter, T _ref is the first clock cycle of the first clock, and the second count value can be expressed as N _ref *T _ref +3*T _ref +3*T _detected . Therefore, if N _ref *T _ref +3*T _ref +3*T _detected <NUMB _ovf *T _ref , it is determined that the second clock signal does not have a stop failure.

Therefore, based on the action of clearing the first counter and the second counter after the cross-time domain handshake action of the two clock signals is successful, the first clock count value or the second clock count value is judged in the above manner, so as to effectively realize the mutual check between the two clock signals.

In some embodiments, the clock fault detection method further includes: obtaining a first clock count theoretical value range; latching the first clock count value in response to a first signal; and determining that a clock deviation fault exists in the first clock signal if the first clock count value exceeds the first clock count theoretical value range.

Exemplarily, as shown in reference Figure 4, when the frequency of the first clock signal of the first clock is low, that is, the period becomes larger, it will cause the first clock count value to exceed the upper limit value of the first clock count theoretical value range; when the frequency of the first clock signal of the first clock is high, that is, the period becomes smaller, it will cause the first clock count value to be lower than the lower limit value of the first clock count theoretical value range. Based on this, in order to detect the clock deviation fault, the first clock count value is judged by the first clock count theoretical value range in the present application, that is, if it is determined that the first clock count value is not within the first clock count theoretical value range, it is determined that the first clock signal has a clock deviation fault, and if it is determined that the first clock count value is within the first clock count theoretical value range, it is determined that the first clock signal is normal.

In some embodiments, the first clock domain and the second clock domain are different clock domains, and the theoretical value range of the first clock count is obtained in the following manner.

Specifically, a first clock cycle corresponding to the first clock signal and a second clock cycle corresponding to the second clock signal are obtained; an upper limit value of the first clock count theoretical value range is obtained according to the handshake count threshold, the first clock cycle, the second clock cycle, the first allowable count deviation value corresponding to the first clock signal, the second allowable count deviation value corresponding to the second clock signal, and the upper limit value of the cross-time domain deviation range; a lower limit value of the first clock count theoretical value range is obtained according to the handshake count threshold, the first clock cycle, the second clock cycle, the first allowable count deviation value corresponding to the first clock signal, the second allowable count deviation value corresponding to the second clock signal, and the lower limit value of the cross-time domain deviation range.

Among them, because two clock signals are used to perform cross-time domain handshake to initiate the clearing operation, there is a deviation between the clearing work and the latching action of the first counter. Therefore, in this application, a cross-time domain deviation range is also introduced when obtaining the theoretical value range of the first clock count, thereby improving the accuracy of deviation fault judgment on the first clock signal.

In some embodiments, the clock fault detection method further includes: obtaining a second clock count theoretical value range; latching the second clock count value in response to the first signal; and determining that a clock deviation fault exists in the second clock signal if the second clock count value exceeds the second clock count theoretical value range.

Exemplarily, as shown in reference Figure 4, when the frequency of the second clock signal of the second clock is low, that is, the period becomes longer, it will cause the second clock count value to exceed the upper limit value of the second clock count theoretical value range; when the frequency of the second clock signal of the second clock is high, that is, the period becomes smaller, it will cause the second clock count value to be lower than the lower limit value of the second clock count theoretical value range. Based on this, in order to detect clock deviation faults, the second clock count value is judged by the second clock count theoretical value range in the present application, that is, if it is determined that the second clock count value is not within the second clock count theoretical value range, it is determined that the second clock signal has a clock deviation fault, and if it is determined that the second clock count value is within the second clock count theoretical value range, it is determined that the second clock signal is normal.

In some embodiments, the first clock domain and the second clock domain are different clock domains, and the theoretical value range of the second clock count is obtained in the following manner.

Specifically, a first clock cycle corresponding to the first clock signal and a second clock cycle corresponding to the second clock signal are obtained; an upper limit value of the second clock count theoretical value range is obtained according to the handshake count threshold, the first clock cycle, the second clock cycle, the first allowable count deviation value corresponding to the first clock signal, the second allowable count deviation value corresponding to the second clock signal, and the upper limit value of the cross-time domain deviation range; a lower limit value of the second clock count theoretical value range is obtained according to the handshake count threshold, the first clock cycle, the second clock cycle, the first allowable count deviation value corresponding to the first clock signal, the second allowable count deviation value corresponding to the second clock signal, and the lower limit value of the cross-time domain deviation range.

Among them, since two clock signals are used to perform cross-time domain handshake to initiate the clearing operation, there is a deviation between the clearing work and the latching action of the second counter. Therefore, in this application, a cross-time domain deviation range is also introduced when obtaining the second clock count theoretical value range, thereby improving the accuracy of deviation fault judgment on the second clock signal.

In some embodiments, the upper limit value of the first clock count theoretical value range or the second clock count theoretical value range is obtained by the following formula:

ρ1＝3*T _detected

Among them, ρ1 is the upper limit value of the cross-time domain deviation range, MAX is the upper limit value of the first clock count theoretical value range or the second clock count theoretical value range, N _ref is the handshake count threshold, T _ref is the first clock cycle, T _detected is the second clock cycle, p _ref % is the first allowable count deviation value, and p _detected % is the second allowable count deviation value.

And, the lower limit value of the first clock count theoretical value range or the second clock count theoretical value range is obtained by the following formula:

ρ2＝2*T _detected

Among them, ρ2 is the upper limit value of the cross-time domain deviation range, and MIN is the lower limit value of the first clock counting theoretical value range or the second clock counting theoretical value range.

A second aspect of the present invention provides a clock fault detection circuit 100 , as shown in FIG5 . The clock fault detection circuit 100 includes a first counter 1 , a second counter 2 , a handshake module 3 and a signal processing module 7 .

Among them, the first counter 1 is used to count with the period of the first clock signal to obtain the first clock count value; the second counter 2 is used to count with the period of the second clock signal to obtain the second clock count value; the handshake module 3 is connected to the first counter 1 and the second counter 2, and the handshake module 3 is used to control the first clock signal to handshake with the second clock signal when the first clock count value or the second clock count value reaches the handshake count threshold; the signal processing module 7 is used to determine that at least one of the first clock signal and the second clock signal has a fault when the handshake between the first clock signal and the second clock signal fails.

According to the clock fault detection circuit 100 of the embodiment of the present invention, when the first clock count value or the second clock count value reaches the handshake count threshold, the first clock signal and the second clock signal are triggered to perform a handshake operation. Since the handshake failure will occur when any clock signal fails, if the handshake failure between the first clock signal and the second clock signal is detected, it can be determined that at least one of the first clock signal and the second clock signal has a fault. Therefore, by using the method of handshaking between the first clock signal and the second clock signal, it is determined whether the two clock signals are normal, thereby realizing mutual inspection of the first clock signal and the second clock signal, and ensuring the accuracy of the first clock signal and the second clock signal.

In some embodiments, the first counter 1 is further configured to output a handshake signal when the first clock count value reaches a handshake count threshold.

The handshake module 2 includes a first handshake unit 31 and a second handshake unit 32 .

Among them, the first handshake unit 31 is connected to the first counter 1, and the first handshake unit 31 is used to obtain the handshake signal b of the first clock domain to which the first clock signal belongs, and synchronize the handshake signal b to the second clock domain to which the second clock signal belongs, and generate a first signal c; the second handshake unit 31 is connected to the first handshake unit 31, the first counter 1, and the second counter 2, and the second handshake unit 31 is used to synchronize the first signal c to the first clock domain, and generate a second signal a to clear the first clock count value and the second clock count value.

Specifically, under normal conditions, the first counter 1 outputs a handshake signal b when it counts to the handshake count threshold. The first handshake unit 31 caches the handshake signal b received from the first clock domain to which the first clock signal belongs, and then synchronizes the handshake signal b to the second clock domain to which the second clock signal belongs, and generates a first signal c, i.e., triggers the handshake signal b in the first clock domain to which the first clock signal belongs to flip once to generate the first signal c. The first handshake unit 31 can also receive the second clock signal of the second clock at the same time. The second handshake unit 32 caches the first signal c. The second handshake unit 32 can also receive the first clock signal of the first clock at the same time. The second handshake unit 32 synchronizes the first signal c to the first clock domain and generates a second signal a. The first clock counts the first clock according to the second signal a, and clears the second clock count value according to the second signal a.

For the handshake signal b and the second clock output according to the first clock domain to which the first clock signal belongs, if the port D of the first handshake unit 31 is triggered, that is, the true value is 1, it means that the handshake signal b is normal, and the port CK of the first handshake unit 31 is triggered, that is, the true value is 1, it means that the second clock signal is normal, so the first signal c output by the first handshake unit 31 is valid, that is, the true value is 1; if the port D of the first handshake unit 31 is not triggered, that is, the true value is 0, it means that the handshake signal b is invalid, and the port CK of the first handshake unit 31 is triggered, that is, the true value is 1, it means that the second clock signal is normal, so the first signal c output by the first handshake unit 31 is invalid, that is, the true value is 0; if the port D of the first handshake unit 31 is triggered, that is, the true value is 1, it means that the handshake signal b is normal, and the port CK of the first handshake unit 31 is not triggered, that is, the true value is 0, it means that the second clock signal is normal, so the first signal c output by the first handshake unit 31 is invalid, that is, the true value is 0;

Similarly, for the second signal a output according to the first signal c generated by the first handshake unit and the first clock signal, if the port D of the second handshake unit 32 is triggered, that is, the true value is 1, it means that the first signal c is normal, and the port CK of the second handshake unit 32 is triggered, that is, the true value is 1, which means that the first clock signal is normal, and therefore the second signal a output by the second handshake unit 32 is valid, that is, the second signal is normal; if the port D of the second handshake unit 32 is triggered, that is, the true value is 1, it means that the first signal c is normal, and the port CK of the second handshake unit 32 is not triggered, that is, the true value is 0, which means that the first clock signal is abnormal, and therefore the second signal a output by the second handshake unit 32 is invalid, that is, the second signal is abnormal; if the port D of the second handshake unit 32 is not triggered, that is, the true value is 0, it means that the first signal c is invalid, and the port CK of the second handshake unit 32 is triggered, that is, the true value is 1, which means that the first clock signal is normal, and therefore the second signal a output by the second handshake unit 32 is invalid, that is, the second signal is abnormal.

Based on this, when port D of the first handshake unit 31 is triggered, that is, the true value is 1, and port CK of the first handshake unit 31 is triggered, that is, the true value is 1, at this time, since the handshake signal and the second clock signal are normal, the first signal c output by the first handshake unit 31 is valid, that is, port D of the second handshake unit 32 is triggered, that is, the true value is 1, and port CK of the second handshake unit 32 is triggered, that is, the true value is 1, at this time, since the first signal and the first clock signal are normal, the second signal a output by the second handshake unit 32 is valid, the first counter 1 clears the first clock count value according to the received second signal a, and at the same time the second counter 2 also clears the second clock count value.

In addition, when the port CK of the first handshake unit 31 is not triggered, that is, the true value is 0, the second clock signal fails, that is, the second clock signal is faulty, which will cause the first signal c output by the first handshake unit 31 to fail, and then the second signal a output by the second handshake unit 32 is also invalid, and the operation of clearing the first clock count value and the second clock count value cannot be triggered; when the first clock signal is faulty, the first counter 1 cannot count, and the first counter 1 cannot output the handshake signal. Therefore, the port D of the first handshake unit 31 is not triggered, that is, the true value is 0, which will cause the first signal c output by the first handshake unit 31 to fail, and then the second signal a output by the second handshake unit 32 is also invalid, and the operation of clearing the first clock count value and the second clock count value cannot be triggered.

In some embodiments, the signal processing module 7 is specifically used to determine that at least one of the first clock signal and the second clock signal has a stop failure if the first clock count value and the second clock count value are not cleared and the handshake of the first clock signal and the second clock signal fails.

That is to say, only when both the first clock signal and the second clock signal have no oscillation stop failure, the first counter 1 and the second counter 2 can be cleared at the same time. Therefore, if the first clock count value and the second clock count value are not cleared, the handshake between the first clock signal and the second clock signal fails, and it is determined that at least one of the first clock signal and the second clock signal has a oscillation stop failure. If the first clock signal has a oscillation stop failure, the first counter 1 cannot count, and the first counter cannot output a handshake signal, and then after a chain reaction, the second signal will fail. At this time, the second counter 2 will not perform the clearing action, which means that the handshake between the first clock signal and the second clock signal fails. For example, if the second clock signal has a oscillation stop failure, the second counter 2 cannot count, and the first counter will not perform the clearing action, and then after a chain reaction, the second signal will fail, which means that the handshake between the first clock signal and the second clock signal fails. Based on this, when it is determined that the first clock count value and the second clock count value are not cleared, it can be determined that the handshake between the first clock signal and the second clock signal fails.

In some embodiments, as shown in FIG. 5 , the clock failure detection circuit 100 further includes a first watchdog 41 .

Among them, the first watchdog 41 is connected to the first counter 1 and the signal processing module 7, and the first watchdog 41 is used to determine whether the first clock count value is greater than the overflow threshold of the first counter 1; the signal processing module 7 is also used to determine that the second clock signal has a stop oscillation fault when the first clock count value is greater than the overflow threshold of the first counter. That is to say, when the first clock and the second clock are working normally, the handshake result signal is normal, the first counter 1 and the second counter 2 can complete the zeroing action, and then the first clock count value will not exceed the overflow threshold. However, as shown in FIG2, when the second clock signal has a stop oscillation fault, the handshake result signal will be abnormal, and at this time, the second counter 2 will not have a clock count value, and the first counter 1 will not perform the zeroing action. Therefore, the first counter 1 will continue to count until it exceeds the overflow threshold. Therefore, when it is determined that the first clock count value is greater than the overflow threshold of the first counter, it can be known that the second clock signal has a stop oscillation fault.

In some embodiments, as shown in FIG. 5 , the clock failure detection circuit 100 further includes a second watchdog 42 .

Among them, the second watchdog 42 is connected to the second counter 2 and the signal processing module 7, and the second watchdog 42 is used to determine whether the second clock count value is greater than the overflow threshold of the second counter 2; the signal processing module 7 is also used to determine that the first clock signal has a stop oscillation fault when the second clock count value is greater than the overflow threshold of the second counter 2. That is to say, when the first clock and the second clock are both working normally, the handshake result signal is normal, the first counter 1 and the second counter 2 can complete the zeroing action, and then the second clock count value will not exceed the overflow threshold. However, as shown in FIG3, when the first clock signal has a stop oscillation fault, the handshake result signal will be abnormal, and at this time, the first counter 1 will not have a clock count value, and the second counter 2 will not perform the zeroing action. Therefore, the second counter 2 will continue to count until it exceeds the overflow threshold. Therefore, when it is determined that the second clock count value is greater than the overflow threshold of the second counter, it can be known that the first clock signal has a stop oscillation fault.

In some embodiments, the clock failure detection circuit further includes: a first latch module and a first comparison module.

Among them, the first latch module is connected to the first timer and the first handshake unit 31, and is used to latch the first clock count value in response to the first signal; the first comparison module is connected to the first latch module and the signal processing module, and is used to determine whether the first clock count value meets the first clock count theoretical value range and output a first comparison result; the signal processing module is also used to determine that when the second clock count value exceeds the first clock count theoretical value range based on the first comparison result, it is determined that there is a clock deviation fault in the first clock signal.

Exemplarily, as shown in reference Figure 4, when the frequency of the first clock signal of the first clock is low, that is, the period becomes larger, it will cause the first clock count value to exceed the upper limit value of the first clock count theoretical value range; when the frequency of the first clock signal of the first clock is high, that is, the period becomes smaller, it will cause the first clock count value to be lower than the lower limit value of the first clock count theoretical value range. Based on this, in order to detect the clock deviation fault, the first latch module latches the first clock count value in response to the first signal, and sends the first clock count value to the first comparison module. The first comparison module outputs the first comparison result to the signal processing module by judging whether the first clock count value meets the first clock count theoretical value range. The signal processing module judges the first clock count value through the first clock count theoretical value range. If it is determined that the second clock count value exceeds the first clock count theoretical value range, it is determined that the first clock signal has a clock deviation fault.

In some embodiments, as shown in FIG. 5 , the clock failure detection circuit further includes: a second latch module 5 and a second comparison module 6 .

Among them, the second latch module 5 is connected to the second timer and the first handshake unit 31, and is used to latch the second clock count value in response to the first signal; the second comparison module 6 is connected to the second latch module 5 and the signal processing module 7, and is used to determine whether the second clock count value meets the second clock count theoretical value range, and output a second comparison result; the signal processing module is also used to determine that when the second count value exceeds the second clock count theoretical value range according to the second comparison result, it is determined that there is a clock deviation fault in the second clock signal; if it is determined that the second clock count value does not exceed the second clock count theoretical value range, it is determined that the second clock signal is normal.

Exemplarily, as shown in reference Figure 4, when the frequency of the second clock signal of the second clock is low, that is, the period becomes longer, the second count value will exceed the upper limit of the second clock count theoretical value range; when the frequency of the second clock signal of the second clock is high, that is, the period becomes smaller, the second count value will be lower than the lower limit of the second clock count theoretical value range. Based on this, in order to detect the clock deviation fault, the second latch module 5 latches the second clock count value in response to the first signal, and sends the second clock count value to the second comparison module 6. The second comparison module 6 outputs the second comparison result to the signal processing module by judging whether the second clock count value meets the second clock count theoretical value range. The signal processing module judges the second clock count value according to the second clock count theoretical value range. If it is determined that the second clock count value exceeds the second clock count theoretical value range, it is determined that the second clock signal has a clock deviation fault. If it is determined that the second clock count value does not exceed the second clock count theoretical value range, it is determined that the second clock signal is normal.

In some embodiments, after the signal processing module 7 identifies a vibration stop fault or a deviation fault, the fault situation may also be reported so that relevant personnel can perform corresponding safety processing on the fault problem.

A third aspect of the present invention provides an integrated circuit system. As shown in FIG6 , the integrated circuit system 200 includes a first clock circuit 10 , a second clock circuit 20 , and the clock fault detection circuit 100 of the above embodiment.

The clock fault detection circuit 100 is connected to the first clock circuit 10 and the second clock circuit 20, and is used to perform fault detection on the first clock signal or the second clock signal.

The integrated circuit system 200 according to the embodiment of the present invention can implement fault detection of the first clock signal and the second clock signal by adopting the clock fault detection circuit 100 of the above embodiment.

In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims (20)

1. A clock failure detection method, comprising: Acquire a first clock signal and a second clock signal; Counting the period of the first clock signal to obtain a first clock count value, and counting the period of the second clock signal to obtain a second clock count value; When the first clock count value or the second clock count value reaches a handshake count threshold, controlling the first clock signal to handshake with the second clock signal; If the handshake between the first clock signal and the second clock signal fails, it is determined that at least one of the first clock signal and the second clock signal has a fault. 2. The clock failure detection method according to claim 1, wherein controlling the first clock signal to handshake with the second clock signal comprises: Obtaining a handshake signal of a first clock domain to which the first clock signal belongs; Synchronize the handshake signal to a second clock domain to which the second clock signal belongs, and generate a first signal; The first signal is synchronized to the first clock domain, and a second signal is generated to clear the first clock count value and the second clock count value to zero. 3. The clock fault detection method according to claim 2, wherein if the handshake between the first clock signal and the second clock signal fails, determining that at least one of the first clock signal and the second clock signal has a fault comprises: If the first clock count value and the second clock count value are not cleared, the handshake between the first clock signal and the second clock signal fails; It is determined that at least one of the first clock signal and the second clock signal has an oscillation stop fault. 4. The clock failure detection method according to claim 3, characterized in that a first counter is used to count the period of the first clock signal to obtain a first clock count value, and a second counter is used to count the period of the second clock signal to obtain a second clock count value; The first clock count value and the second clock count value are not cleared to zero, including: The first clock count value is greater than an overflow threshold of the first counter and/or the second clock count value is greater than an overflow threshold of the second counter. 5. The clock failure detection method according to claim 4, characterized in that the clock failure detection method further comprises: If the first clock count value is greater than the overflow threshold of the first counter, it is determined that the second clock signal has an oscillation stop fault. 6. The clock failure detection method according to claim 4, characterized in that the clock failure detection method further comprises: If the second clock count value is greater than the overflow threshold of the second counter, it is determined that the first clock signal has an oscillation stop fault. 7. The clock failure detection method according to claim 2, characterized in that the clock failure detection method further comprises: Obtaining a first clock count theoretical value range; In response to the first signal, latching the first clock count value; If the first clock count value exceeds the first clock count theoretical value range, it is determined that a clock deviation fault exists in the first clock signal. 8. The clock fault detection method according to claim 7, wherein the first clock domain and the second clock domain are different clock domains, and obtaining the theoretical value range of the first clock count comprises: Obtaining a first clock cycle corresponding to the first clock signal and a second clock cycle corresponding to the second clock signal; Obtaining an upper limit value of the first clock count theoretical value range according to the handshake count threshold, the first clock cycle, the second clock cycle, a first allowable count deviation value corresponding to the first clock signal, a second allowable count deviation value corresponding to the second clock signal, and an upper limit value of the cross-time domain deviation range; The lower limit value of the first clock count theoretical value range is obtained according to the handshake count threshold, the first clock cycle, the second clock cycle, the first allowable count deviation value corresponding to the first clock signal, the second allowable count deviation value corresponding to the second clock signal and the lower limit value of the cross-time domain deviation range. 9. The clock failure detection method according to claim 2, characterized in that the clock failure detection method further comprises: Obtaining a second clock counting theoretical value range; In response to the first signal, latching the second clock count value; If the second clock count value exceeds the second clock count theoretical value range, it is determined that a clock deviation fault exists in the second clock signal. 10. The clock fault detection method according to claim 9, wherein the first clock domain and the second clock domain are different clock domains, and obtaining the second clock count theoretical value range comprises: Obtaining a first clock cycle corresponding to the first clock signal and a second clock cycle corresponding to the second clock signal; Obtaining an upper limit value of the second clock count theoretical value range according to the handshake count threshold, the first clock cycle, the second clock cycle, a first allowable count deviation value corresponding to the first clock signal, a second allowable count deviation value corresponding to the second clock signal, and an upper limit value of the cross-time domain deviation range; The lower limit value of the second clock count theoretical value range is obtained according to the handshake count threshold, the first clock cycle, the second clock cycle, the first allowable count deviation value corresponding to the first clock signal, the second allowable count deviation value corresponding to the second clock signal and the lower limit value of the cross-time domain deviation range. 11. The clock failure detection method according to claim 8 or 10, characterized in that: The upper limit value of the first clock count theoretical value range or the second clock count theoretical value range is obtained by the following formula: ρ1＝3*T _detected Among them, ρ1 is the upper limit value of the cross-time domain deviation range, MAX is the upper limit value of the first clock count theoretical value range or the second clock count theoretical value range, N _ref is the handshake count threshold, T _ref is the first clock cycle, T _detected is the second clock cycle, p _ref % is the first allowable count deviation value, and p _detected % is the second allowable count deviation value. 12. The clock failure detection method according to claim 11, characterized in that the lower limit of the first clock count theoretical value range is obtained by the following formula: ρ2＝2*T _detected Among them, ρ2 is the upper limit value of the cross-time domain deviation range, and MIN is the lower limit value of the first clock count theoretical value range or the second clock count theoretical value range. 13. A clock failure detection circuit, comprising: a first counter, the first counter being used to count a period of a first clock signal to obtain a first clock count value; a second counter, the second counter being used to count a period of the second clock signal to obtain a second clock count value; A handshake module, the handshake module is connected to the first counter and the second counter, and the handshake module is used to control the first clock signal to handshake with the second clock signal when the first clock count value or the second clock count value reaches a handshake count threshold; The signal processing module is used to determine that at least one of the first clock signal and the second clock signal has a fault when the handshake between the first clock signal and the second clock signal fails. 14. The clock failure detection circuit according to claim 13, characterized in that: The first counter is further configured to output a handshake signal when the first clock count value reaches a handshake count threshold; The handshake module comprises: a first handshake unit, wherein the first handshake unit is connected to the first counter, and is used to obtain a handshake signal of a first clock domain to which the first clock signal belongs, synchronize the handshake signal to a second clock domain to which the second clock signal belongs, and generate a first signal; A second handshake unit, wherein the second handshake unit is connected to the first handshake unit, the first counter, and the second counter, and the second handshake unit is used to synchronize the first signal to the first clock domain and generate a second signal to clear the first clock count value and the second clock count value. 15. The clock fault detection circuit according to claim 14 is characterized in that the signal processing module is specifically used to determine that at least one of the first clock signal and the second clock signal has an oscillation stop fault if the first clock count value and the second clock count value are not cleared to zero and the handshake between the first clock signal and the second clock signal fails. 16. The clock failure detection circuit according to claim 15, further comprising: a first watchdog, the first watchdog being connected to the first counter and the signal processing module, and the first watchdog being used to determine whether the first clock count value is greater than an overflow threshold of the first counter; The signal processing module is further configured to determine that the second clock signal has an oscillation stop fault when the first clock count value is greater than an overflow threshold of the first counter. 17. The clock failure detection circuit according to claim 15, further comprising: a second watchdog, the second watchdog being connected to the second counter and the signal processing module, and the second watchdog being used for determining whether the second clock count value is greater than an overflow threshold of the second counter; The signal processing module is further configured to determine that the first clock signal has an oscillation stop fault when the second clock count value is greater than an overflow threshold of the second counter. 18. The clock failure detection circuit according to claim 14, further comprising: A first latch module, connected to the first timer and the first handshake unit, and configured to latch the first clock count value in response to the first signal; a first comparison module, the first comparison module being connected to the first latch module and the signal processing module, and being used for judging whether the first clock count value satisfies a first clock count theoretical value range, and outputting a first comparison result; The signal processing module is further used to determine that a clock deviation fault exists in the first clock signal when it is determined according to the first comparison result that the second clock count value exceeds the first clock count theoretical value range. 19. The clock failure detection circuit according to claim 14, further comprising: A second latch module, the second latch module is connected to the second timer and the first handshake unit, and is used for latching the second clock count value in response to the first signal; a second comparison module, the second comparison module being connected to the second latch module and the signal processing module, and being used for judging whether the second clock count value satisfies a second clock count theoretical value range, and outputting a second comparison result; The signal processing module is further configured to determine that a clock deviation fault exists in the second clock signal when it is determined according to the second comparison result that the second count value exceeds a second clock count theoretical value range. 20. An integrated circuit system, comprising: A first clock circuit, used to generate a first clock signal; A second clock circuit, used for generating a second clock signal; The clock fault detection circuit according to any one of claims 13 to 20, wherein the clock fault detection circuit is connected to the first clock circuit and the second clock circuit, and is used to perform fault detection on the first clock signal or the second clock signal.