CN1188947C - Logic circuit and carry lookahead circuit - Google Patents

Abstract

The logic circuit for checking the initial 1 in the binary data string includes: inputting the "not" logic circuit of the highest bit; The bits of the system data string and the NOR circuit of the higher bit than the bit position; the bit setting corresponding to the data string of the binary number respectively, inputting the above-mentioned "not" logic circuit and the above-mentioned NOR circuit an output inverter; respectively corresponding to the 2-input circuit of the bit setting of the data string of the binary number; one input of the 2-input circuit is the output of the inverter corresponding to the bit position, and The other input, when the 2-input circuit is set corresponding to a bit other than the highest bit, is the output of the NOR circuit located one bit higher than the bit position, and the output of the NOR circuit set corresponding to the highest bit is In the above 2-input circuit, the value is fixed at 0 or 1. The logic circuit and lookahead carry circuit are simple in configuration and can perform high-speed processing.

Description

Logic circuit and look-ahead carry circuit

This application is based on the contents described in the patent application No. 62346 filed in Japan on March 9, 1999, and the priority is claimed under the Paris Convention, and the contents thereof are made a part of the present application.

This application is also a patent application based on the contents described in Patent Application No. 186956 filed in Japan on June 30, 1999, and claims priority under the Paris Convention, and makes the contents thereof a part of the present application.

The present invention relates to logic circuits, and more particularly to logic circuits for retrieving the first occurrence of a 0 or 1 in a multi-bit data string.

In addition, the present invention relates to a carry-lookahead (CLA) circuit necessary for constituting a multi-bit arithmetic unit.

One of the logical circuits constituting the hardware of a computer is a circuit called a 0 search circuit or a 1 search circuit. This circuit is a circuit that retrieves the first 0 or 1 that appears when checking the bits of a binary number data string sequentially from the upper bit, and is used as a comparison circuit that compares the size of the data string or inputs 0 or 1, for example. A basic circuit such as a priority encoder that generates an output code representing the highest priority input line when two or more input lines are reached.

However, in the conventional 0 or 1 search circuit, a plurality of logic gates are connected in a matrix or dendritic structure, so the circuit configuration is complicated. Also, there are multiple routes to go from input to output, so processing takes a lot of time.

In addition, input signal A (a<N-1>, a<N-2>), ..., a<0>, hereinafter expressed as a<N-1:0>) and input signal B of N-bit length (b<N-1>, b<N-2>), . Among the original CLA circuits is the circuit disclosed in Japanese Laid-Open Patent JP-3-150630. The CLA circuit performs operations in parallel when the carry signal input is "0" and when the input is "1", and selects and outputs either operation result according to the lower carry signal value. This circuit is usually called an advanced carry circuit. .

In this document, the circuit shown in FIG. 2 is shown as an original 4-bit CLA circuit. When adding each bit of the input signal A(a<3:0>= and input signal B(b<3:0>=, the transmitted signal P<3:0>(a<3:0 >Exclusive-OR operation=per bit with b<3:0>, and AND operation=per bit of generated signal G<3:0>(a<3:0> and b<3:0>. And put The signal P<3:0>, the signal G<3:0> and the carry Cin from the previous stage are input to the CLA circuit, and then the carry signal C<3:0> is output.

FIG. 3 shows the configuration of a CLA circuit having a configuration to select an output according to one operation result, and this configuration is provided with CLA1 and the operation carry Cin of the carry signal C<3:0> when the carry Cin from the previous stage is 1. When CLA2 of the carry signal C<3:0> is 0, one of them is selected and output as the carry signal C<3:0> according to the value of the carry Cin.

The 4-bit CLA circuit shown in FIG. 2 is configured as group 0 of the 1st to 4th bits, and the CLA circuit shown in FIG. The CLA circuit is shown in Figure 1. From group 0 to group 1, 2, ... generate carry signals C<0>～C<3>, C<4>～C<7>, C<8>～C<11>, ... in sequence, And transmit it to the subsequent stage, and finally output the carry signal C<28>~C<31>.

However, the above-mentioned conventional CLA circuit has the following problems. The calculation delay time required from the generation of the carry signal C<0> of the 1st bit to the generation of the carry signal C<31> of the 32nd bit is as shown in FIG. 4 . The time T1 required for the operation of the circuit CLA1 and the circuit CLA2 respectively provided in groups 0 to 7 among the CLA circuits is the same. However, the carry signal C<3> output from group 0 is sent to the CLA circuit of group 1, and then a delay time T2 is generated in the multiplexer MUX that selects the output according to the carry signal C<3>. Since the delay time T2 is accumulated from group 1 to group 7, the delay time T1+T2*7 is finally generated. Therefore, the original problem is that as the number of bits increases, the time required for the carry operation increases.

In order to solve the above-mentioned original problems, an object of the present invention is to provide a logic circuit having a simple circuit configuration and capable of high-speed processing.

Another object of the present invention is to provide a logic circuit that can shorten the time period for sending signals P, G, and K of every m bits to a group consisting of m bits and obtain the signals PG, GG in units of groups. , KG calculation delay time.

In order to achieve the above-mentioned purpose, the logic circuit according to the present invention is a logic circuit for retrieving the initial 1 when checking the bits of the data string of the binary number in order from the most significant bit, comprising: inputting the binary system The "NON" logic circuit of the uppermost bit of the data string of the number; one-to-one correspondence with the bits other than the uppermost bit of the data string of the binary number respectively, input the said binary number corresponding to the bit position The bits of the data string and the NOR circuit of the higher bit than the bit position; respectively corresponding to the bit setting of the data string of the binary number, inputting the above-mentioned "NO" logic circuit and the above-mentioned NOR circuit an output inverter; respectively corresponding to the 2-input circuit of the bit setting of the data string of the binary number; one input of the 2-input circuit is the output of the inverter corresponding to the bit position, and The other input, when the 2-input circuit is set corresponding to a bit other than the highest bit, is the output of the NOR circuit located one bit higher than the bit position, and the output of the NOR circuit set corresponding to the highest bit is In the above 2-input circuit, the value is fixed at 0 or 1.

According to a preferred embodiment, said "NOT" logic circuit and NOR circuit is formed by an N-channel metal-oxide-semiconductor field-effect transistor connected in parallel between the ground potential and the output line of said "NOT" logic circuit and NOR circuit .

In addition, according to a preferred embodiment, an inverter is inserted in a preceding stage of the 2-input NOR circuit.

According to other embodiments of the present invention, the logic circuit is composed of a timing circuit, a quasi-NMOS circuit and a logic gate circuit; The first combined circuit cuts off the ground potential from the output line, supplies power to the output line, and raises the output line to "H" level. During the output determination period, the When the input signal is sent to the first combination circuit, the power supply to the output line is stopped, and the ground potential is selectively connected to the output line according to the logic operation value, and output through the output line determined logical value; the quasi-NMOS circuit is formed by a second combination circuit connected between the output line and ground potential, during said precharging period, said second combination circuit is controlled to connect said ground potential to said ground potential The output line is lowered to "L" level, and the input signal to be evaluated is sent to the first combination circuit while the power is supplied to the output line during the output determination period, according to The logic operation value selectively cuts the ground potential away from the output line, and outputs the determined logic value through the output line; the logic gate circuit is connected to the timing circuit, and according to the output of the timing circuit The signal of the line controls the power supply to the output line of the quasi-NMOS circuit. The logic values determined by the timing circuit and the quasi-NMOS circuit are the same or complementary, and during the output determination period, the output line of the quasi-NMOS circuit is connected to the ground potential, and is lowered to " In the case of L" level, in response to the change of the output line corresponding to the quasi-NMOS circuit, the logic gate circuit stops the power supply to the output line of the timing circuit.

In addition, according to a preferred embodiment, the first combined circuit and the second combined circuit are composed of NMOS FETs constructed with the same logic.

According to other embodiments of the present invention, the quasi-NMOS logic circuit is composed of a second quasi-NMOS circuit, a first quasi-NMOS circuit, a first logic gate circuit, and a second logic gate circuit; the second quasi-NMOS circuit is composed of A second combination circuit between the output line and ground potential is formed, during said pre-charging, said second combination circuit is controlled to connect said ground potential to said output line, causing said output line to drop to "L "level, during the output determination period, while the input signal to be evaluated is sent to the first combination circuit, power is supplied to the output line, and the ground potential is selectively cut according to the logic operation value. From the output line, the determined logic value is output through the output line; the first quasi-NMOS circuit is composed of a first combination circuit connected between the output line and the ground potential, during the pre-charging period, the control of the first a combination circuit that connects said ground potential to said output line, lowers said output line to "L" level, and simultaneously supplies an input signal to be evaluated to said first combination circuit during output determination , supply power to the output line, selectively cut the ground potential away from the output line according to the logic operation value, and output the determined logic value through the output line; the first logic gate circuit is based on the The signal of the output line of the second quasi-NMOS circuit controls the power supply to the output line of the first quasi-NMOS circuit; the second logic gate circuit is based on the signal from the first quasi-NMOS circuit The signal of the output line controls the power supply to the output line of the second quasi-NMOS circuit. The first quasi-NMOS circuit and the second quasi-NMOS circuit are complementary, and the ground potential is connected to the first quasi-NMOS circuit and the second quasi-NMOS circuit during the output determination. When one of the output lines of the NMOS circuit is pulled down to "L" level, according to the change of the "H" level of the other output line, the first or second logic gate circuit stops The power supply of the output line of the other side of the quasi-NMOS circuit.

The look-ahead carry circuit according to another embodiment of the present invention inputs at least one of the propagation signal P, the generation signal G, and the cancellation signal K of every m (m is an integer greater than 1) bits, and generates a signal consisting of m bits as At least one of the group propagation signal PG, the group generation signal GG and the group elimination signal KG of the corresponding group; value or in the case of inverted values of the inverted set of propagation signals PB all having one logical value, the logic circuit outputs said set of propagated signals PG having said one logical value and/or having said one logical value The inversion group propagation signal PGB of the inversion value of ; the propagation signal P and/or the inversion group propagation signal PB are retrieved in order from the most significant bit to the bottom bit, and corresponding to the propagation signal P The inverse value of said one logic value in PB or the bit of the signal in which said one logic value first appears in said inversion group propagation signal PB generates an effective m-bit selection signal, and said propagation signal When the inversion value of the one logic value does not appear in any bit of P, or in the case that the one logic value does not appear in any bit of the inversion group propagation signal PB, the priority encoder outputs Any bit does not become an effective selection signal; when the selection signal is input and a valid bit is input to the selection signal, the selector selects the generation signal G and/or the elimination signal K corresponding to the The generation signal G and/or the elimination signal K of the effective bits of the selection signal are output as the group generation signal GG and/or the group elimination signal KG respectively, and any bit of the selection signal does not become effective In this case, the selector outputs the group generating signal GG and/or the group canceling signal KG having an inverted value of the one logic value.

According to the advance carry circuit of another embodiment of the present invention, at least one of the carry signal C, the propagation signal P of every m (m is an integer greater than 1), the generation signal G, and the cancellation signal K is input to generate a signal represented by m At least one of the group propagation signal PG, the group carry signal CG, the group generation signal GG and the group elimination signal KG composed of bits as the corresponding group; the advanced carry circuit is composed of a logic circuit, a priority encoder and a selection circuit. In the case where the propagation signals P all have a logical value or in the case where the inverted group propagation signals PB all have an inverted value of a logical value, a logic circuit outputs the group propagation signal PG having the one logical value and/or the inverted group propagation signal PGB having an inverted value of the one logical value; after retrieving the propagation signal P and/or the inverted group propagation signal PB in order from the highest bit to the lower bit, and A bit corresponding to the inverted value of the first occurrence of the one logic value in the propagated signal P or the signal of the first occurrence of the one logic value in the inversion group propagation signal PB generates an effective m-bit selection signal, and the inversion value of the one logic value does not appear in any bit of the propagation signal P, or the one logic value does not appear in any bit of the inversion group propagation signal PB In the case of , the priority encoder outputs a selection signal in which any bit does not become valid; when the selection signal is input and valid bits are input to the selection signal, the selector selects the generation signal G and the elimination signal K Among them, the generation signal G and the elimination signal K corresponding to the effective bits of the selection signal are output as the group carry signal CG and the inverted group carry signal CGB respectively, and any bit of the selection signal does not become When it is valid, the selector outputs the carry signal C as the group carry signal CG according to the group propagation signal PG or the inverted group propagation signal PGB.

According to another embodiment of the present invention, the carry-ahead circuit is composed of a plurality of first carry-ahead circuit groups, a plurality of second carry-ahead circuit groups and a third carry-ahead circuit; the first carry-ahead circuit group is composed of a plurality of first carry-ahead circuits Carry circuits are formed; the second advanced carry circuit group is composed of a plurality of second advanced carry circuits, and each second advanced carry circuit is connected to the first advanced carry circuit belonging to each group of the first advanced carry circuit group; Three advanced carry circuits are connected to the second advanced carry circuit group; the first advanced carry circuit inputs every m (m is an integer greater than 1) bit propagation signal, at least one of the generation signal and the cancellation signal , to generate at least one of the first group of propagating signals, the first group of generation signals and the first group of cancellation signals consisting of m bits; the first advanced carry circuit is composed of a logic circuit, a priority encoder and The selection circuit is configured such that a logic circuit outputs said first one having said one logic value in a case where said propagating signals all have a logic value or in a case where an inverted group of propagation signals all have an inversion value of a logic value. a group of propagated signals and/or said first inverted group of propagated signals having an inverted value of said one logical value; upon retrieving said propagated signals and/or said inverted group of propagating a signal, and corresponding to the inverse value of the first occurrence of the one logic value in the propagation signal or the bit of the signal in the inversion set of propagation signals in which the one logic value first occurs generates an effective m bit selection signal, and the inversion value of the one logic value does not appear in any bit of the propagation signal, or the one logic value does not appear in any bit of the inversion group propagation signal In the case of , the priority encoder outputs a selection signal in which any bit does not become valid; when the selection signal is input and a valid bit is input to the selection signal, the selector selects the generation signal and/or the cancellation signal Among them, the generation signal and/or elimination signal corresponding to the effective bits of the selection signal are output as the first group generation signal and the first group elimination signal respectively, and any bit in the selection signal is When not valid, the selector outputs the first group generation signal and/or the first group cancellation signal having an inverted value of the one logic value.

The second carry-ahead circuit inputs at least one of the first group of propagation signals, the first group of generation signals, and the first group of cancellation signals to generate a second group of the corresponding first group of carry-ahead circuits at least one of a propagated signal, a second set of generated signals, and a second set of canceled signals; said second lookahead carry circuit is composed of a logic circuit, a priority encoder, and a selection circuit, all of said first set of propagated signals having a logic value or in the case where the first inverted set of propagated signals all have an inverted value of a logic value, the logic circuit outputs the second set of propagated signals having the one logic value and/or having the said second inverted group propagation signal of the inversion value of said one logic value; said first group propagation signal and/or said first inverted group propagation signal are retrieved in order from the most significant bit to the bottom bit, and generating valid multi-bit selection signal, and the inversion value of the one logic value does not appear in any bit of the first group of propagation signals, or does not appear in any bit of the first inversion group of propagation signals In the case of said one logic value, the priority encoder outputs any bit that does not become an effective selection signal; when the selection signal is input and a valid bit is input to the selection signal, the selector selects the first group The first group of generated signals and/or the first group of eliminated signals corresponding to the effective bits of the selection signal among the generated signals and/or the first group of eliminated signals are used as the second group generated signals and/or Or the second group of elimination signals is output, and when any bit of the selection signal does not become valid, the selector outputs the second group of generation signals having the inversion value of the one logic value and/or or the second set of cancellation signals.

The third carry-ahead circuit inputs at least one of the carry signal, the second group of propagation signals, the second group of generation signals, and the second group of cancellation signals to generate the corresponding second group of carry-ahead circuits At least one of a third group of propagation signals, a group of carry signals, a third group of generation signals and a third group of cancellation signals; the third advanced carry circuit is composed of a logic circuit, a priority encoder and a selection circuit, and in the second In the case where the group propagated signals all have a logic value or in the case where the second inverted group propagated signals all have an inverse value of a logic value, the logic circuit outputs the third group with the one logic value propagating signals and/or a second group of propagating signals of said second inverted group having an inverted value of said one logic value; upon retrieving said second group of propagating signals and/or The second inverted set of propagated signals corresponds to the first occurrence of the inverted value of the one logic value in the second set of propagated signals or the first occurrence of the first occurrence in the second inverted set of propagated signals A valid multi-bit selection signal is generated from a bit of a signal of a logical value, and the inversion of the one logical value does not appear in any bit of the second set of propagated signals, or the second Under the situation that described a logical value does not appear in any bit of the inverted group propagation signal, any bit output by the priority encoder does not become an effective selection signal; input the selection signal, and input valid bits to the selection signal, the selector selects the second group of generation signals and the second group of elimination signals corresponding to the valid bits of the selection signal among the second group of generation signals and the second group of elimination signals, and serves as the The group carry signal and the inverted group carry signal are output, and when any bit of the selection signal does not become valid, the selector uses the third group generation signal and the third group cancellation signal to convert The carry signal is output as the set of carry signals.

FIG. 1 is a circuit diagram of a conventional 32-bit CLA circuit.

FIG. 2 is a configuration circuit diagram of a CLA circuit of group 0 among the CLA circuits.

FIG. 3 is a configuration diagram of a CLA circuit having a configuration for selecting and outputting one calculation result according to a carry value.

4 is an explanatory diagram showing the calculation delay time required from the generation of the 1st-bit carry signal C<0> to the generation of the 32nd-bit carry signal C<31> in the CLA circuit.

Fig. 5 is a circuit configuration diagram in the case of applying the logic circuit according to the present invention to a 4-bit priority encoder.

FIG. 6 is a circuit configuration diagram in the case where a timer circuit constitutes a non-circuit or a non-circuit of one search circuit shown in FIG. 5 .

FIG. 7 is a circuit configuration diagram in which an NMOS·FET is added to the timing circuit of FIG. 6 .

FIG. 8 is a circuit configuration diagram in a case where a static circuit is added to the timer circuit in FIG. 7 .

FIG. 9 is a circuit configuration diagram in which a clock control function is removed from the timer circuit 5 shown in FIG. 7 and a circuit for statically operating logic is added.

FIG. 10 is a circuit configuration diagram in the case where the single search circuit in FIG. 5 is configured by a NAND circuit.

FIG. 11 is a circuit configuration diagram in the case where a plurality of one search circuit of FIG. 5 is connected to further configure a multi-bit priority encoder.

FIG. 12 is a circuit configuration diagram in a case where a CLA circuit used in an adder is configured using the priority encoder of FIG. 5 .

FIG. 13( a ) is a circuit diagram showing an example of the circuit configuration of the AND circuit AN1 in the first and second CLA circuits. Fig. 13(b) is an explanatory diagram of a quasi-NMOS type.

Fig. 14 is the circuit configuration under the situation of the NOR circuit NR11, NR21, NR31 of the priority encoder PE of the first CLA circuit CLA (1) of Fig. 12 and the second CLA circuit CLA (2) of Fig. 17 constituted by the timing circuit picture.

FIG. 15 is a circuit configuration diagram in the case where a selector SEL1 is constituted by PMOS·FETs, NMOS·FETs, and a neutral circuit.

FIG. 16 is a timing chart showing the timing of input and output of the CLA circuit shown in FIG. 12 .

FIG. 17 is a circuit configuration diagram in the case where an AND circuit is connected to the circuit in FIG. 12 .

FIG. 18 is a timing chart showing the timing of input and output of the CLA circuit shown in FIG. 17 .

FIG. 19 is a circuit configuration diagram in a case where a 32-bit CLA circuit is configured using the first CLA circuit CLA(1) of FIG. 12 and the second CLA circuit CLA(2) of FIG. 17 .

FIG. 20 is an explanatory diagram showing calculation delay times in the CLA circuit shown in FIG. 19 .

Fig. 21(a) shows a circuit that inputs two signals A and B (/A and /B), performs a logical sum operation between A and B, and generates an output signal P.

Fig. 21(b) shows a circuit for outputting a signal PB inverted to a logical sum between two input signals A and B.

FIG. 22( a ) shows a circuit for generating the waveform CB of the carry signal Cin per bit in synchronization with the clock CLK.

FIG. 22(b) shows a circuit for generating a waveform CB of an inverted carry signal /Cin per bit in synchronization with the clock CLK.

FIG. 23 is a circuit configuration diagram in the case where a search circuit 2-7 is connected to the quasi-NMOS NAND circuit 42 shown in FIG. 17, and the same parts as those in FIG. 17 are denoted by the same symbols.

Fig. 24 shows a quasi-NMOS NAND circuit 42 connected to a dynamic circuit 46 composed of the same logic.

FIG. 26 is a circuit configuration diagram showing a configuration example of a combination of an output-synchronized dynamic circuit and a quasi-NMOS circuit.

FIG. 27 is a timing chart showing the timing of input and output of the quasi-NMOS NAND circuit 61 shown in FIG. 26 .

Fig. 28 is a circuit configuration diagram showing an example of the configuration of a logic circuit configured by a complementary quasi-NMOS NAND circuit according to the present invention.

FIG. 29 is a timing chart showing the timing of input and output of the complementary quasi-NMOS NAND circuit shown in FIG. 28 .

30 is a circuit configuration diagram showing a configuration example of a complementary logic circuit according to the present invention using a quasi-NMOS NAND circuit as an application example of the circuit shown in FIG. 28 .

FIG. 31 is a timing chart showing the timing of input and output of the complementary quasi-NMOS NAND circuit shown in FIG. 30 .

Embodiments of the present invention will be described below with reference to the drawings.

Fig. 5 is a circuit configuration diagram in the case of applying the logic circuit according to the present invention to a 4-bit priority encoder. FIG. 1 is a circuit diagram of a conventional 32-bit CLA circuit.

The priority encoder 1 is to generate a 2-bit output code corresponding to the highest input row of the highest priority rank among the 4-bit input data (IN<0>, IN<1>, IN<2>, IN<3>) circuit, which consists of a retrieval circuit 2 and an encoder 3 for encoding the output of the retrieval circuit 2. Here, it is assumed that an input row with a small index has a high priority.

Next, the configuration of the search circuit 2 will be described. Since the encoder 3 is constituted by an existing encoder circuit, description thereof is omitted.

1 The search circuit 2 checks the bit values of the input data IN<0>, IN<1>, IN<2>, IN<3> in the order of IN<0>, IN<1>... with high priority, IN< When 1 appears initially in i>(0≤i≤3), only 1 is output to S<i>(0≤i ≤3), output 0 to other S<j>(j≠i), and output 1 to Y. When all IN<i>(0≤i≤3) are 0, 1 is output to all S<i>(0≤i≤3), and 0 is output to Y.

The 1 retrieval circuit 2 shown in FIG. 5 is provided with a non-logic circuit 11 for inputting input data IN<0>, a 2-input NOR circuit 12 for inputting IN<1> and IN<0>, and a non-logic circuit 12 for inputting IN<2> and IN<0>. 3-input NOR circuit 13 for 0> and IN<1>, 4-input NOR circuit 14 for inputs IN<3>, IN<0>, IN<1>, and IN<2>.

The outputs of the non-logic circuit 11 and the non-logic circuits 12-14 are reversed by the following non-logic circuits 15-18, further inverted by the non-logic circuits 19-22, and then input to the 2-input NOR circuits 23-26. Input lines A0-A3. At the same time, the bit signal "0" is input to the input line B0 of the NOR circuit 23, the inversion signal of the non-logic circuit 15 is input to the input line B1 of the NOR circuit 24, and the inversion signal of the non-logic circuit 16 is input to the input line B1 of the NOR circuit 24. The input line B2 of the NOR circuit 25 inputs the inverted signal of the NOR circuit 17 to the input line B3 of the NOR circuit 26 . The operation results of the NOR circuits 23-26 are taken out as output data S<0>, S<1>, S<2>, S<3>; the signal inverted by the non-logic circuit 18 is taken out as output data Y.

In the search circuit 2 configured as described above, for example, when the input data IN<3:0> of the input bit string "0101" is observed, in the non-logic circuit 11 and the NOR circuits 12 to 14, the bit string is When it becomes "1000", the bit string in the following non-logic circuits 15 to 18 becomes "0111". In the operation up to this point, the bits of the input data are checked in order from the upper order, the position where the bit string becomes "0, 1" is detected, and the subsequent bit values are all set to 1. Therefore, when IN<3:0>="0101", all the bits after IN<2> become 1 ("0111") regardless of their value. Then, the bit string of the output data S<3:0> is output as “0100” through the NOR circuits 19-22 and the NOR circuits 23-26.

Similarly, when the input data (X can be 0 or 1) of the bit strings "1XXX", "001X", and "0001" is input, "1000", "0010", and "0001" are respectively output. In the case where at least one "1" is contained in the input data IN<3:0>, 1 is output as the output data Y.

On the other hand, when the input data IN<3:0> of the bit string "0000" is input, the bit string becomes "1111" in the NOR circuit 11 and the NOR circuits 12 to 14, and the next NOR circuit The bit strings in the circuits 15 to 18 are "0000". Here, since the bit string of no input data is a combination of "0, 1", the bit string of the output data S<3:0> via the NOR circuits 19-22 and the NOR circuits 23-25 is "0000". When "1" is not included in the input data IN<3:0>, 0 is output as the output data Y.

Next, the output data S<3:0> is input to the encoder 3 to generate 2-bit output codes Q0 and Q1 indicating the high input line with the highest priority. By the way, if the output data S<3:0> is "1000", "00" indicating input line 0 is output; if it is "0100", "01" indicating input line 1 is output; if it is "0010 ", output "10" representing input line 2; if it is "0001", output "11" representing input line 3. When the output data Y is 0, the output data S<3:0> is recognized as "0000".

Thus, in the search circuit according to this embodiment, the circuit configuration is simpler than conventional circuits in which logic gates are connected in a matrix or a dendrite. Furthermore, since there are few routes to be searched from input to output, the time required for processing can be shortened. Therefore, a logic circuit capable of high-speed processing can be realized with a simple circuit configuration.

In this embodiment, a 1 search circuit is described, however, the logic circuit according to the present invention can also be configured as a 0 search circuit.

Next, a specific circuit configuration of the search circuit 1 according to this embodiment will be described.

FIG. 6 is a circuit configuration diagram in the case where the negation circuit 11 and the negation circuits 12 to 14 of the search circuit 2 shown in FIG. 5 are constituted by timer circuits. In FIG. 6, PC0-PC3 respectively represent PMOS·FETs controlled by a clock signal (CLK), and N00-N33 represent NMOS·FETs respectively. When viewed corresponding to FIG. 5 , N00 corresponds to the non-logic circuit 11, N10 and N11 correspond to the 2-input NOR circuit 12, N20-N22 correspond to the 3-input NOR circuit 13, and N30-N33 correspond to the 4-input NOR circuit 13. 14.

FIG. 7 is a circuit configuration diagram in the case where an NMOS·FET for controlling activation of the timer circuit by a clock signal is added to the timer circuit 4 of FIG. 6 . In the case of configuring the timer circuit 5 as shown in FIG. 7 , although the operation speed is slightly slower than that of the example of FIG. 6 , it is possible to prevent the through current flowing into the circuit when the clock signal is precharged.

FIG. 8 is a circuit configuration diagram in a case where a static circuit for statically operating logic is further added to the timer circuit 5 shown in FIG. 7 . In a general timer circuit, it is difficult to maintain the H level by precharging, but when the timer circuit 6 is configured as shown in FIG. 8, since the logic is determined to be static, the operation of the circuit can be stabilized. Furthermore, the processing speed of the circuit of FIG. 8 can be made substantially the same as that of the circuit of FIG. 6 .

FIG. 9 is a circuit configuration diagram in which a clock control function is removed from the timer circuit 5 shown in FIG. 7 and a circuit for statically operating logic is added. In the case of configuring the timer circuit 7 as shown in FIG. 9 , since the logic is determined to be static once the circuit is enabled by the precharge, the operation of the circuit can be stabilized. Furthermore, the processing speed of the circuit can be made substantially the same as that of the circuit of FIG. 6 .

In FIG. 5 , an example is shown in which the logic circuit of the retrieval circuit 2 is constituted by a NOR circuit and a NOR circuit, but it may also be constituted by a NAND circuit as in FIG. 10 , for example.

FIG. 11 is a circuit configuration diagram in the case where a plurality of 1 search circuits in FIG. 5 are connected to further constitute a multi-bit priority encoder. This priority encoder 31 is composed of one search circuit 32 and encoders 33a and 33b for encoding the output of one search circuit 32 .

Next, the configuration of the search circuit 32 shown in FIG. 11 will be described.

The 1 search circuit 32 is composed of 4-bit 1 search circuits 2-1 to 2-4, the same 4-bit 1 search circuit 2-5, AND logic circuits 34 to 37, and a multiplexer 38.

16-bit input data IN<15:0> is input to 1 search circuit 2-1～2-4 arranged in parallel every 4 bits, here, output Y0<3:0 from 1 search circuit 2-1～2-4 >, S0<15:0> as intermediate output. Among them, Y0<3:0> is input to the 1 search circuit 2-5, and S0<15:0> is input to one input line of the AND logic circuits 34-37 and the input line of the multiplexer 38, respectively. On the other hand, output data Y and intermediate output Y1<3:0> are fetched from 1 search circuit 2-5. Among them, the intermediate output Y1 <3:0> is input to the other input line of the AND logic circuits 34 to 37 and the selection signal line of the multiplexer 38 .

For example, the AND logic circuit 36 outputs the signal S0<11:8> when the intermediate output Y1<2> is “1”, and outputs the signal “0000” when the intermediate output Y1 <2> is “0”. The multiplexer 38 uses the output SO<i+3:i> (i=0, 4, 8, 12) from any one of the 1 search circuits 2-1 to 2-4 as an intermediate output according to the signal of the selection signal line. T<3:0> output goes to. Let the output data S<15:0> of the AND logic circuits 34 to 37 be data connected to a 16-bit encoder not shown.

In the priority encoder 31 configured as above, the output data S<15:0> and Y<3:0> of the AND logic circuits 34 to 37 for the input data IN<15:0> become ANDed with the 1 Search circuit 2 The same data as the case of 16-bit input.

On the other hand, when the output data S<15:0> is preferentially encoded, the lower and upper 2 bits are respectively output to the intermediate output T<3:0> from the multiplexer 38 and from the 1 search circuit 2- 5 in the middle of output Y1<3:0>. Furthermore, the upper 2 bits are generated from Y1<3:0> in the encoder 33a, and the lower 2 bits are generated from T<3:0> in the encoder 33b.

For example: Assume that the bit string of the input data IN<15:0> is "0000001XXXXXXXX", in Y1<3:0>, the upper 2 bits "01" are used as the output code Q2, Q3 output, in T<3:0 > The lower 2 bits "10" are output as output codes Q0 and Q1, thereby generating a 4-bit output code "0110" indicating the highest priority input line ("6" in this case) . When the output data Y is 0 in any case, S<15:0> is recognized as "0000000000000000".

In the circuit shown in Figure 11, output data S<15:0>, intermediate data T<3:0>, and intermediate data Y1<3:0> are generated, but only S<15:0> can be generated Or T<3:0>, Y1<3:0>.

Thus, since the priority encoder is multi-staged using the single search circuit shown in FIG. 5, even in the case of multi-bit input, a logic circuit with simple circuit configuration and high-speed processing can be realized.

FIG. 12 is a circuit configuration diagram in a case where a CLA (carry-ahead) circuit for an adder is configured using the priority encoder of FIG. 5 . Here, since a 4-1 encoder is not used, only 1 search circuit is used. The CLA circuit is a circuit that generates PG/PGB/GG/KG groups from the P (propagation)/G (generation)/K (deletion) signal of each bit in charge. It is composed of 4-bit quasi-NMOS NAND circuit AN1, the same A 4-bit priority encoder PE and a 4×1 selector SEL1 are formed.

The quasi-NMOS NAND circuit AN1 generates a group PG signal from the P signal of each bit.

The priority encoder PE is a circuit that generates and outputs S<3:0> and PGB signals from the PB signals of each bit.

The selector SEL1 is a dual-rail timing multiplexer composed of a 4×1 multiplexer MUX1 and a multiplexer MUX2. The selector SEL1 generates group GG and KG signals from the G and K signals of each bit. FIG. 14 is a circuit configuration diagram in which a selector SEL1 is constituted by PMOS·FETs, NMOS·FETs and non-logic circuits.

FIG. 16 is a timing chart showing input and output timings of the CLA circuit shown in FIG. 12 .

The input P (solid line in the figure) and PG (dotted line in the figure) are precharged during CLK is "L" level, and P and PB are shifted to different states when CLK is "H" level , that is: when P is "1", PB is "0"; when P is "0", PB is "1". When P is "1", both G (solid line in the figure) and K (dotted line in the figure) are "0", and only when PB is "1", either G or K is "0". 0". Group PG/PGB/GG/KG signals are output at the same timing as the P, PB, G, and K signals described above.

In the CLA circuit shown in FIG. 12, since logic elements are not formed in a dendritic form, a high-speed CLA circuit can be formed.

FIG. 17 is a circuit configuration diagram in the case where a logical circuit is connected to the output stage of the circuit in FIG. 12, and the same parts as those in FIG. 12 are denoted by the same symbols. The CLA circuit is a circuit that generates the group PG/PBG/GG/KG signal and the group carry output signal from the P/G/K signal of each bit and the group carry input signal C, and is connected to the PGB from the priority encoder PE and 2-input AND logic circuits AN11 and AN12 with the output from the selector SEL1 as input. FIG. 18 is a timing chart showing input and output timings of the CLA circuit shown in FIG. 17 .

In this way, even when the CLA circuit is configured as shown in FIG. 17, the calculation of CG (group carry) can be accelerated.

Since the CLA circuits shown in FIGS. 12 and 17 are connected in a plurality of dendrites, a larger CLA circuit can be constructed. In this case, the CLA circuit shown in FIG. 17 is used for the output stage.

Hereinafter, a CLA circuit used for multi-bit addition will be described in detail as a specific example.

The CLA circuit according to the present embodiment is characterized in that the entire number of bits N (N is an integer greater than 1) is classified into groups of a plurality of bits m (m is an integer smaller than N), and the propagation of each bit is used in each group. signal P<i>, generate signal G<i>, and eliminate signal K<i> to generate group propagation signal PG, group generation signal GG, and group elimination signal KG in units of groups composed of multiple bits, and use these signals to The carry signal CN-1 of the last necessary most significant bit is obtained.

For example: set N=16, m=4, then, the input signals A and B are classified into 4 groups:

A＝(a15～a12, a11～a8, a7～a4, a3～a0)...(1)

B=(b15～b12, b11～b8, b7～b4, b3～b0)...(2)

Then calculate the carry signals C3, C7, C11, C15 of each group.

C3 = f (A3 ～ A0, B3 ～ B0) ... (3)

C7＝f(a7～a4, b7～b4)+C3 ……(4)

C11＝f(a11～a7, b11～b7)+C7 ……(5)

C15＝f(a15～a11, b15～b11)+C11 ... (6)

In order to obtain each such group carry signal, it is necessary to generate a group-based signal PG/GG/KG from the signal P/G/K of each bit in the group. Referring to FIG. A circuit configuration of a CLA circuit CLA(1).

The first CLA circuit CLA(1) is a circuit that outputs signals PG/GG/KG that are groups of 4 bits, and a signal P for each bit in the corresponding group is generated in advance by a circuit not shown in the following formula. <3:0>(=P<3>～P<0>)/G<3:0>(=G<3>～G<0>)/K<3:0>(=K<3>～ K<0>).

P<i>＝/a<i>*/b<i>

G<i>＝a<i>ExORb<i>

K<i>＝a<i>*b<i>

The first CLA circuit CLA(1) is provided with an AND logic circuit AN1 for generating a signal PG, a priority encoder PE for generating a selection signal S<3:0>, a selection signal for generating the signals GG, KG according to the selection signal S<3:0> device SEL1.

The AND logic circuit AN1 inputs all P<3:0> signals, performs AND logic operation as shown in FIG. 7 , and then outputs the result as a PG signal and/or as a PGB signal inverting PG.

PG＝P<3>*P<2>*P<1>*P<0> …(7)

PGB＝/(P<3>*P<2>*P<1>*P<0>)

＝/P<3>+/P<2>+/P<1>+/P<0>

＝PB<3>+/PB<2>+/PB<1>+/PB<0>  …(8)

This corresponds to taking the carry signal Cin withdrawn from the group of the previous stage as its corresponding group when all conduction from the 0th bit to the 3rd bit, that is, only when P<3:0>=“1” The carry signal CG inside is transmitted to the subsequent stage. At this time, the signals GG and KG become "0" at the same time.

When at least one of all P<3:0> signals is “0”, the operation of the priority encoder PE must be performed. The priority encoder PE is provided with a NOR circuit NR11 to which the inverted propagation signal PB<3:0> is input, inverters IN11 and IN12 to which the output of the circuit NR11 is input, a NOR circuit to which the outputs of the inverters IN11 and IN12 are input. Circuit NR12, NOR circuit NR21 for input inversion group propagation signal PB<3:1>, inverters IN21 and IN22 for output of input circuit NR21, NOR circuit NR22 for output of input inverters IN21 and IN22, input The NOR circuit NR31 of the signal PB<3:2>, the inverters IN31 and IN32 of the output of the input circuit NR31, the NOR circuit NR32 of the output of the input inverters IN31 and IN42, the NOR circuit NR32 of the input signal PB<3> Circuit NR41, inverters IN41, IN42 and IN43 inputting the output of circuit NR21, and NOR circuit NR41 inputting the output of inverter IN43 and ground potential "0". Selection signals S<0> to S<3> are output from NOR circuits NR12, NR22, NR32, and NR41, respectively.

When at least one signal P<3:0> is "0" (or at least one signal PB<3:0> is "1"), the priority encoder PE decides to turn the signal G<3:0 One of >, K<3:0> is taken as a group signal GG, KG. Here, searching in order from the signal PB<3>, when the signal PB<3> is "1", the signal S<3> = "1", and all others are "0". When the signal PB<3> is “0” and the signal PB<2> is “1”, the signal S<2>=“1”, and all others are “0”. In this way, a certain signal S<3:0> becomes "1", and all others are "0".

Such a selection signal S<3:0> is input to the selector SEL1. The selector SEL1 has multiplexers MUX1 and MUX2, and selects the signal S<3:0> to input each multiplexer MUX1 and MUX2, and then selects the signals G<3:0>, K with the bit "1". <3:0>, and output as group signals GG and KG respectively.

Here, the signals GG and KG are represented by the following equations.

GG＝P<3>*P<2>*P<1>*G<0>+P<3>*P<2>*G<1>

+P<3>*G<2>*G<3> ...(9)

KG＝P<3>*P<2>*P<1>*K<0>+P<3>*P<2>*K<1>

+P <3>*K <2>*K <3>… (10)

When such signals GG and KG are represented by selection signals S<3:0>, they are represented as follows. First, import the following logical formula.

Q<0>＝PG＝P<3>*P<2>*P<1>*P<0>

＝/(PB<3>+PB<2>+PB<1>+PB<0>)  …(11)

Q<1>＝P<3>*P<2>*P<1>

＝/(PB<3>+PB<2>+PB<1>)……(12)

Q<2>＝P<3>*P<2>

＝/(PB<3>+PB<2>)                           ...

Q<3>=P<3>

＝/PB<3> ...(14)

/Q<0>＝PGB＝/(P<3>*P<2>*P<1>*P<0>)

＝PB<3>+PB<2>+PB<1>+PB<0>  …(15)

/Q<1>＝/(P<3>*P<2>*P<1>)

＝PB<3>+PB<2>+PB<1>                                                                                                                                                   ... (16)

/Q<2>＝/(P<3>*P<2>)

＝PB<3>+PB<2>                                                                                                                                                                                    ... (17)

/Q<3>＝/P<3>

＝PB<3>                                                                                                                                                                                                                                                   ... (18)

S<0>＝Q<1>*/Q<0> ...(19)

S<1>＝Q<2>*/Q<1> ...(20)

S<2>＝Q<3>*/Q<2> ...(21)

S<3>＝1*/Q<3> ...(22)

in

P<3>*PB<3>＝P<2>*PB<2>＝P<1>*PB<1>

＝P<0>*PB<0>＝「0」                                                                                                                                                                                                                                  =

Therefore, the above expressions (11) to (18) become the following expressions.

S<0>＝P<3>*P<2>*P<1>*(PB<3>+PB<2>+PB<1>+PB<0>)＝P<3>*P<2 >*P<1>*PB<0> ...(24)

S<1>＝P<3>*P<2>*(PB<3>+PB<2>+PB<1>)

= P <3>*P <2>*PB <1>… (25)

S<2>＝P<3>*(PB<3>+PB<2>)

= P <3>*PB <2>… (26)

S<3>＝1*PB<3>

= Pb <3> ... (27)

By PB<3>*G<3>=G<3>, PB<2>*G<2>=G<2>,

PB<1>*G<1>＝G<1>, PB<0>*G<0>＝G<0>, get the following relationship:

S<0>*G<0>+S<1>*G<1>+S<2>*G<2>+S<3>*G<3>

＝P<3>*P<2>*P<1>*PB<0>*G<0>+P<3>*P<2>*

PB<1>*G<1>+P<3>*PB<2>*G<2>+PB<3>*G<3>

＝P<3>*P<2>*P<1>*G<0>+P<3>*P<2>*G<1>+P<3

>*G<2>+G<3>

= GG ... (28)

S<0>*G<0>+S<1>*G<1>+S<2>*G<2>+S<3>*K<3>

＝P<3>*P<2>*P<1>*PB<0>*K<0>+P<3>*P<2>*

PB<1>*K<1>+P<3>*PB<2>*K<2>+PB<3>*K<3>

＝P<3>*P<2>*P<1>*K<0>+P<3>*P<2>*K<1>+P<3

>*K<2>+K<3>

= KG ... (29)

Thus, the following formulas (30), (31) are obtained:

GG＝S<0>*G<0>+S<1>*G<1>+S<2>*G<2>

+S <3>*g <3> ... (30)

GG＝S<0>*K<0>+S<1>*K<1>+S<2>*K<2>

                                                                                                                ... (31)

First import the following logic equations:

Q<0>＝PG＝P<3>*P<2>*P<1>*P<0>

＝/(PB<3>+PB<2>+PB<1>+PB<0>) ... (11)

Q<1>＝P<3>*P<2>*P<1>

＝/(PB<3>+PB<2>+PB<1>)  …(12)

Q<2>＝P<3>*P<2>

＝＝/(PB<3>+PB<2>)                                                                                                                                                                        ... (13)

Q<3>=P<3>

＝/PB<3>                                                                                                                                                                                                                            ... (14)

/Q<0>＝PGB＝/(P<3>*P<2>*P<1>*P<0>)

=PB<3>+PB<2>+PB<1>+PB<0>...(15)

/Q<1>＝/(P<3>*P<2>*P<1>)

＝PB<3>+PB<2>+PB<1>  …(16)

/Q<2>＝/(P<3>*P<2>)

＝PB<3>+PB<2>                                                                                                                              ... (17)

/Q<3>＝/P<3>

＝PB<3>                                                                                                                                                                                                                                                                     ... (18)

S<0>＝Q<1>*/Q<0> ... (19)

S<1>＝Q<2>*/Q<1> ...(20)

S <2> = q <3>*/Q <2>… (21)

S<3>＝1*/Q<3> ...(22)

As shown in equations (8), (24) to (27) and FIG. 12 above, the selection signal S<3:0> is a logic called a priority encoder that takes PB<3:0> as an input.

That is: as mentioned above, when arranged in the order of PB<3>, PB<2>, PB<1>, PB<0>, when PB<i>="1" (where i=3~0), S <i>=“1”, other S<j> is “0” (where j is 3 to 0 other than i), and PBG=“1”.

When all of PB<3>, PB<2>, PB<1>, and PB<0> are "0", all S<i>=PBG="0".

Therefore, formulas (30) and (31) mean that each logic for generating signal GG/KG is selected from each of the four signals G<3:0>, K<3:0> according to the selection signal S<3:0> Selected multiplexer (4-1MUX).

As described above, the first CLA circuit CLA(1) has an AND logic circuit AN1, a priority encoder PE, and a selector SEL1 in units of groups of 4 bits, and generates propagation signals PG and generation signals in units of groups. GG and cancellation signal KG.

Here, the first CLA circuit CLA(1) is configured to completely generate the signals PG, GG, and KG, but it is also possible to generate the signals PG and GG or the signals PG and KG. In the case of generating the signals PG and GG, the selector SEL1 has only the multiplexer MUX1, and in the case of generating the signals PG and KG, the selector SEL1 has only the multiplexer MUX2.

Next, the second CLA circuit CLA(2) will be described.

The second CLA circuit CLA(2), unlike the first CLA circuit CLA(1) described above, not only generates the group propagation signal PG, the group generation signal GG and the group cancellation signal KG within the corresponding group, but also uses these signals PG, GG , KG to obtain and output the group carry signal CG. As a specific structure, as shown in FIG. 17, the AND logic circuit AN1 and the priority encoder PE are the same as the above-mentioned embodiment, but the selector SEL11 is different, and it further has AND logic circuits AN11 and AN12.

The selector SEL11 has multiple converters MUX11 and MUX12, and the multiplexer MUX11 inputs the selection signal S<3:0> output from the priority encoder PE, the G<3:0> of each bit, and the carry signal from the lower group C. Signal PG output from AND logic circuit AN1. The multiplexer MUX12 inputs the selection signal S<3:0>, K<3:0> per bit, the reverse carry signal CB from the lower group, and the signal PG.

As described above, when all the signals P<3:0> are “1”, the signal PG of “1” and the signal PGB of “0” are output. In this case, the carry signal C and inverted carry signal CB from the lower group are output as the group carry signal CG and inverted group carry signal CGB of the corresponding group. At this time, the signal PGB is all "0". Therefore, the signals GG and KG of "0" are respectively output from the AND logic circuits AN11 and AN12 to which the signal PGB is input.

When at least one signal P<i> is "0", the signal PG is "0", and the signal PGB is "1". The generation of the signals CG and CGB in this case first selects the signal G<i> corresponding to the selection signal S<i> having a value of "1" among the signals G<3:0>, K<3:0> respectively , K<i>, and then output them respectively as signals CG and CGB in units of groups. Furthermore, input PGB and signal CGB of "1" signal to AND logic circuit AN11, and output signal GG; input PGB and signal CGB of "1" signal to AND logic circuit AN12, and output signal KG.

However, the signal CG is expressed as a logical expression as follows.

                                                                ...

CGB＝/CG＝PG*/Cin+KG  …(33)

Using the above formulas (30) and (31), we get:

CG＝PG*Cin+S<0>*G<0>+S<1>*G<1>+S<2>*G<2>

+S <3>*g <3> ... (34)

CGB＝PG*/Cin+S<0>*K<0>+S<1>*K<1>+S<2>*K<2>

+S <3>*k <3> ... (35)

Here, according to the above formulas (7), (24)˜(27), only one of the signals PG, S<3:0> is “1”, and all other signals are “0”.

Therefore, the logic of generating group carry signals CG and CGB from the above formulas (34) and (35) is to select 5 signals Cin and G<3:0> from 5 selection signals PG and S<3:0>, and Select 5-1 multiplexer for 5 signals/Cin and K<3:0>.

And by formula (9), (10), (32), (33):

Cg*pgb = gg ... (36)

                                                                                                                                                                                                                                                             ... (37)

Therefore, as mentioned above, when PG = "0" (PGB = "1"), from (36) formula

CG=GG, KG=CGB.

In FIG. 18 , timings of input and output signals in the second CLA circuit CLA( 2 ) are shown. Here, the solid lines indicate the levels of the signals P, G, and K, and the dotted lines indicate the levels of the inverted signals PB, GB, and KB.

The signals P<3:0>, G<3:0>, K<3:0> and the group carry signal C from the lower group are input synchronously with the clock signal CLK, and the operation delay time is propagated according to the same timing output group Signal PG, group generation signal GG, group carry signal CG.

Here, the second CLA circuit CLA( 2 ) has a configuration for generating all the signals PG, GG, KG, CG, and CGB. However, a configuration for generating signals PG, GG, and CG or a configuration for generating signals PG, KG, and CGB may also be provided. In the case of generating signals PG, GG and CG, the selector SEL11 has only the multiplexer MUX1, and generates the signal CG with the accompanying AND logic circuit AN11; in the case of generating the signals PG, KG and CGB, the selector SEL11 There is only the multiplexer MUX2, and the signal KG is generated with the AND logic circuit AN12.

Next, FIG. 19 shows a circuit configuration in a case where a 32-bit CLA circuit is constituted by the above-mentioned first CLA circuit CLA(1) and second CLA circuit CLA(2). This CLA circuit is divided into three group levels "0-2", the group level "0-1" uses the first CLA circuit CLA(1), and the group level "2" uses the second CLA circuit CLA(2).

In group level "0", each CLA circuit of groups 7 to 0 generates signals PG(7), GG(7), KG(7), PG(6), GG(6), KG(6) ,..., PG(0), GG(0), KG(0).

In the group level "1", each of the four groups 7~4 and groups 3~0 are collected into one group, and each 16-bit signal PGG<1>, GGG<1>, KGG<1>, PGG< 0>, GGG<0>, KGG<0>.

In the group level "2", the second CLA circuit CLA(2) generates signals PGGG, GGGG, and KGGG that collect all 32 bits into one group, and further generates the final carry signal CGGG. This signal GGGG corresponds to a 32-bit carry signal C<31>.

When the time required for calculation in the CLA circuit configured in this way is the same as T11 for each delay time in the group levels "0", "1" and "2" shown in Fig. 20, the overall delay time is T11*3 . This calculation delay time T11*3 means that only the delay times of three levels are accumulated. Therefore, compared with the case of accumulating the delay times of each group like the original CLA circuit shown in FIG. 4, according to this embodiment, The calculation time is shortened.

FIG. 13(b) shows an example of the AND logic circuit AN1. Like the circuit symbol shown in FIG. 13(a), this AND logic circuit AN1 is generally a quasi-NMOS type and is formed by combining inverters into a known NAND circuit. When the clock signal CLK is at a low level, the NMOS·FET N1 connected between the ground terminal and the node ND1 is turned on, and the node ND1 is discharged. When the clock signal CLK becomes high level, the PMOS·FET P1 is turned on, and the NMOS·FET N1 connected between the ground terminal and the node ND1 is turned off.

Signals P<3:0> are respectively inverted by inverters IN104-IN101, and then input to NMOS·FETs N14-N11 connected between nodes ND1 and ND2. Only when the signals in the signal P<3:0> are all "1", the NMOS·FETs N14～N11 are all turned on, the node ND1 is discharged by the PMOS·FET P1, and the signal PG of "1" is output. When at least one of the signals P<3:0> is “0”, the FET inputting the signal is turned on, the node ND1 is connected to the connection terminal, and the signal PG of “0” is output. When a small-sized PMOS FET is used in the PMOS FET P1, even when the PMOS FET P1 is turned on, at least one of the NMOS FETs N14 to N11 is turned on and approximately close to the ground terminal connected to the node ND1. Voltage.

By using such a quasi-NMOS type AND logic circuit AN1 which operates in synchronization with the clock signal CLK, it is possible to increase the speed of the circuit operation.

FIG. 14 shows an example of the circuit configuration of the priority encoder PE. Fig. 14 is the circuit configuration under the situation of the NOR circuit NR11, NR12, NR13 of the priority encoder PE of the first CLA circuit CLA (1) of Fig. 12 and the second CLA circuit CLA (2) of Fig. 17 constituted by the timing circuit picture. The priority encoder PE also performs timing operations synchronously with the clock signal CLK. The NOR circuit of the input signal PB<3:0> is composed of PMOS·FET P11～P14, NMOS·FET N21～N32, and PMOS·FET P11～P14 It is connected between the power supply terminal and the nodes ND11 to ND14, and inputs the clock signal CLK to the gate circuit. While the clock signal CLK is at the low level, the nodes ND11 to ND14 are charged.

The NMOS·FETs N21 to N24 are connected in parallel between the nodes ND11 to ND21, and the NMOS·FET N25 is connected between the node ND21 and the ground terminal. The NMOS·FETs N26-N28 are connected in parallel between the nodes ND12-ND22, and the NMOS·FET N29 is connected between the node ND22 and the ground terminal. The NMOS·FETs N30 to N31 are connected in parallel between the nodes ND13 to ND23, and the NMOS·FET N32 is connected between the node ND23 and the ground terminal. The NMOS·FET N33 is connected between the nodes ND14 to ND24, and the NMOS·FET N34 is connected between the node ND24 and the ground terminal.

The clock signal CLK is input to the gate circuits of NMOS FET N25, N29, N32, and N34, the signal P<0> is input to the gate circuit of NMOS FET N21, and the signal P<1> is input to the gate circuits of NMOS FET N22 and N26 , the signal P<2> is input to the gate circuits of NMOS·FET N23, N27, N30, and the signal P<3> is input to the gate circuits of NMOS·FET N24, N28, N31, N33.

When the clock CLK is at a low level, the PMOS FETs P11~P14 are turned on, and the nodes ND11~ND14 are fully charged. When the clock CLK becomes a high level, the NMOS FETs N25, N29, N32, and N34 are turned on, and the nodes ND21~ND24 are discharged. .

Only when all the signals of the signal PB<3:0> are "0", a high-level signal is output from the node ND11, and when at least one signal is "1", a low-level signal is output, and output The signal PGB inverted by the inverter IN111. Only when all the signals of the signal PB<3:1> are "0", a high-level signal is output from the node ND12, and when at least one signal is "1", a low-level signal is output, and the After the inversion of the inverter IN113, the output of the inverter IN112 is input to the NOR circuit NR101, and then the signal S<0> is output. Only when all the signals of the signal PB<3:2> are "0", the node ND13 outputs a high-level signal, and when at least one of the signals is "1", a low-level signal is output, and the After the inversion of the inverter IN115, the output of the inverter IN114 is input to the NOR circuit NR102, and then the signal S<1> is output. Only when the signal PB<3> is "0", a high-level signal is output from the node ND14, and when the signal is "1", a low-level signal is output, and after being inverted by the inverter IN117, Together with the output of the inverter IN116, it is input to the NOR circuit NR103, and then the signal S<2> is output. After inverter IN118 inverts the output of inverter IN117, it is further inverted by NOR circuit NR104, and then output as signal S<3>.

FIG. 15 is a circuit configuration diagram in the case where the selector SEL1 is constituted by PMOS·FETs, NMOS·FETs and non-logic circuits.

The multiplexers MUX1 and MUX2 having the selector SEL1 have, for example, the circuit configurations shown in FIG. NMOS FETs N41 and N42 are connected in series between the node ND31 and the ground terminal; NMOS FETs N43 and N44 are connected in series and connected in parallel; NMOS FETs N45 and N46 are connected in series and connected in parallel; NMOS FETs N47 and N48 are connected in series and connected in parallel in parallel. The signal S<0:3> is input to the gate circuits of NMOS·FET N41, N43, N45, N47, and the signal G<0:3> is input to the gate circuits of NMOS·FET N42, N44, N46, N48.

When the clock signal CLK is at a low level, the PMOS·FET P21 is turned on, and the node ND31 is charged. When the clock signal CLK becomes high level, at least one signal S<0> and G<0>, signal S<1> and G<1>, signal S<2> and G<2>, signal S<3> and When both of G<3> are combined with “1”, the node ND31 becomes low level. After the level of the node ND31 is inverted by the inverter IN21, the signal GG is output.

The multiplexer MUX2 has the same configuration as the multiplexer MUX1, and corresponds to the signal G<3:0> in the multiplexer MUX1 being replaced by the signal KG<3:0>. PMOS FET P22 is connected between the power supply terminal and node ND32; NMOS FETs N51 and N52 are connected in series between node ND32 and the ground terminal; NMOS FETs N53 and N54 are connected in series and then in parallel; NMOS FETs N55 and N56 are connected in series and then It is connected in parallel with this; NMOS·FET N57 and N58 are connected in series and then connected in parallel with this. The signal S<0:3> is input to the gate circuits of NMOS·FET N51, N53, N55, and N57, and the signal K<0:3> is input to the gate circuits of NMOS·FET N52, N54, N56, and N58.

When the clock signal CLK is at a low level, the PMOS·FET P22 is turned on, and the node ND31 is charged. When the clock signal CLK becomes high level, at least one signal S<0> and K<0>, signal S<1> and K<1>, signal S<2> and K<2>, signal S<3> and When both of K<3> are combined with “1”, the node ND32 becomes low level. After the level of the node ND32 is inverted by the inverter IN22, the signal KG is output.

As a circuit for generating P, G, and K signals for each bit, for example, circuits shown in Figs. 21(a) to (d) may be used. The circuit shown in FIG. 21(a) inputs two input signals A and B (/A and /B), and then performs a logical sum operation between A and B to generate and output a signal P. The clock signal CLK is input to the gate circuit of the PMOS·FET P31, and the node ND41 is charged during the low level period. When the clock signal CLK becomes high level, the gate circuit of NMOS·FET N63 receives the level and turns on. The gate circuits of NMOS FETs N61, N62, N64, and N65 input signals A, /B, /A, and B respectively, and maintain the charging state or discharge of the charged node ND41 according to the combination of these levels. The level of the node ND41 is inverted by the inverter IN131 and output as a signal P.

The circuit shown in FIG. 21(b) outputs the signal PB to which the logical sum is inverted, between the two input signals A and B. This circuit is equivalent to replacing the combinations A, /B, /A, B of signals input to the gate circuits of NMOS·FET N61, N62, N64, N65 in the circuit of FIG. 21(a) with A, B, /A, /B circuit.

The circuit shown in FIG. 21(c) performs a logical product operation between A and B and outputs a signal G. The clock signal CLK is input to the gate circuit of the PMOS·FET P33, and the node ND43 is charged during the low level period. Signals A and B are input to NMOS·FETs N81 and N82, respectively, and the charged state of the charged node ND43 is maintained or discharged according to a combination of these levels. When the clock signal CLK becomes high level, the gate circuit of NMOS·FET N33 receives the level and turns on. The level of the node ND43 is inverted by the inverter IN133 and output as a signal G.

The circuit shown in Figure 21(d) performs an exclusive logical sum operation between A and B and outputs a signal K, which is equivalent to the gate circuit of the NMOS FET N81 and N82 input to the circuit in Figure 21(c) The combination of signals A and B is replaced by /A and /B.

22( a ) and ( b ) show an example of a circuit for generating waveforms C and CB of the carry signal Cin and inverted carry signal /Cin per bit synchronized with the clock signal CLK, respectively.

As explained above, the CLA circuit of the present invention sends the signals P, G, and K of every m bits to a group consisting of m bits, and obtains the signals PG, GG, and KG in units of groups. Therefore, Even when calculating the carry of a calculation with a large number of bits, the signals PG, GG, and KG obtained for each group are used in multiple groups, thereby shortening the calculation delay time.

For example, in the circuit configuration shown in Figure 19, the overall 32-bit operation is divided into groups of 4 bits, and the signals PG, GG, and KG of each group are obtained using the group hierarchy of 3 groups, and finally the carry signal CGGG is obtained . The specific circuit configuration of logic circuit AN1, priority encoder PE, and selector SE is an example, and various modifications are possible.

FIG. 23 is a circuit configuration diagram in the case where the quasi-NMOS NAND circuit 42 shown in FIG. 17 is connected to a search circuit 2-7, and parts equivalent to those in FIG. 17 are denoted by the same reference numerals. The quasi-NMOS NAND circuit 42 is shown in FIG. 24. The quasi-NMOS circuit 62 is connected to a timing circuit 46 composed of the same logic. The timing circuit 46 is a part of the search circuit 2-7. The quasi-NMOS circuit 62 is connected in parallel between the ground potential and the signal line X, and the NMOS FET receiving the inversion signal of the P signal of each bit, and the PMOS gate circuit 47 connecting the power supply to the signal line X send the control signal to The NAND circuit 48 to the PMOS gate circuit 47 is constituted. Similarly, the timing circuit 46 is connected in parallel between the ground potential and the signal line X, and is composed of an NMOS·FET for receiving the PB signal of each bit, and a PMOS gate circuit 49 for connecting the power supply to the signal line X ^* .

FIG. 25 is a timing chart showing the timing of input and output of the quasi-NMOS NAND circuit 42 shown in FIG. 24 .

The input signal to the quasi-NMOS circuit 62 is raised to "H" level during the precharge period, and therefore, the signal line X is pulled down to "L" level.

The input signal to the timing circuit 46 is raised to "H" level during the precharge period, and therefore, the signal line X ^* is pulled down to "H" level at the same time. On the other hand, during the output determination period, as the input signal to the quasi-NMOS circuit 62 and the input signal to the timing circuit 46, the signal P<3:0> of each bit P and the signal PB<3:0 of each bit P are input. 0>.

During the precharge period, because the output signal OUTPUT* (the inversion of OUTPUT) of the timing circuit 46 is precharged to "H" level, the enable signal En makes the output of the control signal 48 become "1", and the PMOS gate circuit 47 conduction. During the subsequent output determination period, the logic values of all the input signals are determined, but in the case where the logic is false (that is, the signal line X is not connected to the ground potential), the signal line X of the quasi-NMOS circuit 62 is not pulled down. In the current path to the "L" level, the PMOS gate circuit 47 fixes the signal line X at the "H" level, so that no consumption current flows. On the other hand, when the logic is established, since there is a current path that pulls down the signal line X to "L" level, the PMOS gate circuit 47 is turned on to consume useless current. However, in the timer circuit 46, the signal line X ^* changes to "L" level because the logic is established, and the output signal OUTPUT* also changes to "L" level. In this way, the PMOS gate circuit 47 is turned off by the control circuit 48, so that no consumption current flows.

The above configuration is generally applied to a combination of a timing circuit such as a motion output and a quasi-NMOS circuit, that is, FIG. 26 is a circuit configuration diagram of a configuration example of a combination of a timing circuit such as an output synchronization and a quasi-NMOS circuit. The quasi-NMOS circuit 62 and the timer circuit 46 are composed of NMOS·FETs having the same logic configuration. However, if the signal line X and the signal line X ^* output the same logic value during the output determination period, it is not necessary to be particularly constituted by the same logic, such a quasi-NMOS circuit is arranged in parallel between the ground potential and the signal line X, and It consists of an NMOS·FET receiving the P signal of each bit, a PMOS gate circuit 47 connecting the power supply to the signal line X, and a NAND circuit 48 supplying a control signal to the PMOS gate circuit 47 . Similarly, the timing circuit 46 is connected in parallel between the ground potential and the signal line X, and is composed of an NMOS·FET for receiving the PB signal of each bit, and a PMOS gate circuit 49 for connecting the power supply to the signal line X ^* .

FIG. 27 is a timing chart showing the timing of input and output of the quasi-NMOS NAND circuit 61 shown in FIG. 26 .

The input signal INPUT[N:0] to the quasi-NMOS NAND circuit 62 and the input signal INPUT*[N:0] to the timer circuit 63 are signals that take equal logical values during input determination.

The input signal INPUT[N:0] to the quasi-NMOS NAND circuit 62 is raised to "H" level during the precharge period, and therefore, the signal line X is pulled down to "L" level.

The input signal INPUT*[N:0] to the timer circuit 46 is raised to "H" level during the precharge period, and therefore, the signal line X ^* is pulled down to "H" level at the same time. On the other hand, during output determination, an input signal to the quasi-NMOS NAND circuit 62 and an input signal to be evaluated to the timing circuit 46 are input as INPUT[N:0] and INPUT*[N:0].

Since the output signal OUTPUT* (the inversion of OTPUT) of the timer circuit 46 is charged to "H" level, the enable signal En makes the output of the control circuit 48 "1", and the PMOS gate circuit 47 is turned on. During the subsequent output determination period, the logical values of all the input signals are determined, but in the case where the logic is false (that is, the signal line X is not connected to the ground potential), since the signal line X of the quasi-NMOS circuit 62 is not pulled down In the current path to the "L" level, the PMOS gate circuit 47 fixes the signal line X at the "H" level, so that no consumption current flows. On the other hand, when the logic is established, since there is a current path that pulls down the signal line X to "L" level, the PMOS gate circuit 47 is turned on to consume useless current. However, in the timer circuit 46, the signal line X ^* changes to "L" level because the logic is established, and the output signal OUTPUT* also changes to "L" level. In this way, the PMOS gate circuit 47 is turned off by the control circuit 48, so that no consumption current flows.

Fig. 28 is a circuit configuration diagram of a logic circuit composed of a complementary quasi-quasi-NMOS NAND circuit according to the present invention. The logic circuit 71 includes a first quasi-NMOS circuit 72 and a second quasi-PMOS circuit 73 complementary to the first quasi-NMOS circuit 72 . The first quasi-NMOS circuit 72 is made up of a combined circuit 72n of NMOS FETs powered by a PMOS gate circuit 74, and the second quasi-PMOS circuit 73 is also made up of a combined circuit 73n of NMOS FETs powered by a PMOS gate circuit 75. In addition, the NAND circuits 76, 77 are connected in two quasi-NMOS circuits, and the NAND circuits 76, 77 are used to make the PMOS gate circuit 74 of the quasi-NMOS circuit by the logic value when the output signals of these two circuits are precharged. , 75 cut off, the PMOS gate circuits 74 and 75 are opposite to each other when the logic is established and reversed.

FIG. 29 is a timing chart showing the timing of input and output of the complementary quasi-quasi-NMOS NAND circuit shown in FIG. 28 .

The combination of the input signal to the first quasi-NMOS circuit 72 and the input signal to the second quasi-PMOS circuit 73, that is, the gate signal to the NMOS FET element, may be any signal if complementary outputs are generated. For example: as the input signal to the first quasi-NMOS circuit 72 and the input signal to the second quasi-PMOS circuit 73, input signals INPUT[N:0] and INPUT* that take mutually inverted logic values are input during the output determination period (Inversion of INPUT)[N:0].

During the precharge period, the input signal INPUT[N:0] to the first quasi-NMOS circuit 72 and the input signal INPUT*[N:0] to the second quasi-PMOS circuit 73 are raised to "H" level, so , the signal line X and the signal line X ^* are pulled down to "L" level.

Because the output signal OUTPUT of the first quasi-NMOS circuit 72 is precharged to "H" level, so, during the output determination period, the enable signal En makes the output of the NAND circuit 76 "1", and the PMOS gate circuit 74 is turned on. .

Likewise, since the output signal OUTPUT* of the second quasi-NMOS circuit 73 is precharged to "H" level, the enable signal En makes the output of the NAND circuit 77 "1" during the output determination period, and the PMOS gate circuit 75 is turned on. Thereafter, during the output determination period, the logical values of all the input signals are determined, and here, either one of the combination circuit 72n and the combination circuit 73n is established, and the other is not established. Therefore, there is no current path for pulling down the signal line X or X ^* in the quasi-NMOS circuit whose logic is not established to "L" level, and the PMOS gate circuit 74 or 75 fixes the signal line X or X ^* at "H". level, so no consumption current flows. On the other hand, in the quasi-NMOS circuit where the logic holds, since there is a current path that pulls down the signal line X or X ^* to "L" level, the PMOS gate circuit 73 or 74 is turned on to consume useless current. However, since the output signal OUTPUT or OUTPUT* of the quasi-NMOS circuit whose logic is not established changes to "L" level, the NAND circuit 76 or 77 is turned on, and the PMOS gate circuit 74 or 75 is turned off, and no consumption current flows. .

FIG. 30 is a circuit configuration diagram of a complementary logic circuit of the present invention using a quasi-NMOS NAND circuit as an application example of the circuit shown in FIG. 28 . This logic circuit 81 includes a first quasi-NMOS circuit 82 and a second quasi-PMOS circuit 83 having an output complementary to that of the first quasi-NMOS circuit 82 . The first quasi-NMOS circuit 82 is composed of a combined circuit 82n of NMOS FETs powered by a PMOS gate circuit 84, and the second quasi-PMOS circuit 83 is also composed of a combined circuit 83n of NMOS FETs powered by a PMOS gate circuit 85. As an input signal to the first quasi-NMOS circuit 82 and an input signal to the second quasi-PMOS circuit 83, an input signal INPUT[N:0] and an input signal INPUT taking mutually inverted logical values are input during the output determination period. *(invert of INPUT)[N:0]. Here, N=2, according to the formula of De Morgan's theorem, the combined circuit 82n of NMOS FET and the combined circuit 83n of NMOS FET are set as:

/(([0]*[1]+[2]-(/[0]+/[1])*/[2]

FIG. 31 is a timing chart of input and output timings of the complementary quasi-quasi-NMOS NAND circuit shown in FIG. 30 .

The combination of the input signal to the first quasi-NMOS circuit 82 and the input signal to the second quasi-PMOS circuit 83, that is, the gate signal to the NMOS FET element, may be any combination if complementary outputs are generated. For example: as the input signal to the first quasi-NMOS circuit 82 and the input signal to the second quasi-PMOS circuit 83, input signals INPUT[2:0] and INPUT* that take mutually inverted logic values are input during the output determination period (Inversion of INPUT)[2:0].

During the precharge period, the input signal INPUT[2:0] to the first quasi-NMOS circuit 82 and the input signal INPUT*[2:0] to the second quasi-PMOS circuit 83 are raised to "H" level, so , the signal line X and the signal line X ^* are pulled down to "L" level.

Because the output signal OUTPUT of the first quasi-NMOS circuit 82 is precharged to "H" level, so, during the output determination period, the enable signal En makes the output of the NAND circuit 86 "1", and the PMOS gate circuit 84 is turned on. .

Likewise, since the output signal OUTPUT* of the second quasi-NMOS circuit 83 is precharged to "H" level, the enable signal En makes the output of the NAND circuit 87 "1" during the output determination period, and the PMOS gate circuit 85 conduction. Thereafter, during the output determination period, the logical values of all the input signals are determined, and here, either one of the combination circuit 82n and the combination circuit 83n is established, and the other is not established. Therefore, there is no current path for pulling down the signal line X or X ^* in the quasi-NMOS circuit whose logic is not established to "L" level, and the PMOS gate circuit 84 or 85 fixes the signal line X or X ^* at "H". level, so no consumption current flows. On the other hand, in the quasi-NMOS circuit where the logic holds, since there is a current path that pulls down the signal line X or X ^* to "L" level, the PMOS gate circuit 83 or 84 is turned on to consume useless current. However, since the output signal OUTPUT or OUTPUT* of the quasi-NMOS circuit whose logic is not established changes to "L" level, the NAND circuit 86 or 87 is turned on, and the PMOS gate circuit 84 or 85 is turned off, and no consumption current flows. .

In addition, the NAND circuits 86, 87 are connected in two quasi-NMOS circuits, and the NAND circuits 86, 87 are used to make the PMOS gate circuit 84 of the quasi-NMOS circuit by the logical value when the output signals of these two circuits are precharged. , 85, when the logic is established and reversed, the PMOS gate circuits 84 and 85 of the quasi-NMOS circuit are opposite to each other.

Claims (2)

1. initial logical circuit of 1 that occurs of retrieval when the upper bit begins to check in order the bit of serial data of 2 system numbers comprises:

Import the NOT logic of upper bit of the serial data of described 2 system numbers;

Respectively with the upper bit of the serial data of described 2 system numbers beyond bit corresponding one by one, input is corresponding to the bit of the serial data of the described 2 system numbers of this bit position and be in the NOR circuit of the bit more upper than this bit position;

Correspond respectively to the bit phase inverter that be provided with, that import the output of above-mentioned NOT logic and above-mentioned NOR circuit of the serial data of described 2 system numbers;

Correspond respectively to 2 input circuits that the bit of the serial data of described 2 system numbers is provided with;

An input of described 2 input circuits is the output corresponding to the described phase inverter of this bit position, and another input, with the upper bit beyond described 2 input circuits of the corresponding setting of bit the time, be the output that is positioned at the described NOR circuit last than this bit position, when corresponding described 2 input circuits that are provided with, be to be fixed in 0 or 1 value with the upper bit.

2. according to the logical circuit of claim 1, it is characterized in that described NOT logic and NOR circuit are made of the n channel metal oxide semiconductor field effect transistor that is connected in parallel between the output line that is connected in parallel on earthing potential and described NOT logic and NOR circuit.

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