CN118888577B - Double heterojunction bipolar transistor - Google Patents
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- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 115
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims abstract description 13
- 239000000463 material Substances 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 8
- 239000000969 carrier Substances 0.000 claims description 3
- 230000006798 recombination Effects 0.000 abstract description 6
- 238000005215 recombination Methods 0.000 abstract description 6
- 238000000926 separation method Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 109
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 20
- 239000013078 crystal Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000012360 testing method Methods 0.000 description 3
- 230000001419 dependent effect Effects 0.000 description 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000013590 bulk material Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000002346 layers by function Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 125000002524 organometallic group Chemical group 0.000 description 1
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Abstract
The application provides a double heterojunction bipolar transistor. The double heterojunction bipolar transistor comprises an N-type GaAs subcollector layer, an N-type GaAs collector layer, a P-type base layer, an N-type GaInP emitter layer and an N-type InGaAs contact layer which are sequentially stacked, wherein the P-type base layer is of a multi-cycle repeated structure of four layers of P-type GaAs（1‑x）Sbx,A,d1/GaAs,B,d2/GaAs（1‑y）Sby,C,d3/GaAs,B,d2 lattice layers. The structure can be adopted to bind electrons of the base layer in the GaAs （1‑x）Sbx layer, bind holes of the base layer in the GaAs （1‑y）Sby layer, and the middle is provided with a GaAs layer interval, so that separation of electrons and holes in physical space is effectively realized, and the recombination probability of the electrons and the holes in the base region is reduced, thereby effectively improving the collector current I c and further improving the current gain beta value.
Description
Technical Field
The invention belongs to the technical field of transistors, and particularly relates to a double heterojunction bipolar transistor.
Background
Compared with the traditional Si-based bipolar transistor, the Heterojunction Bipolar Transistor (HBT) is characterized in that different semiconductor materials are used for an emitter and a base, the emitter and the base have different energy band structures, and the current gain is not dependent on the doping concentration difference of the emitter and the base, but is exponentially dependent on the valence band difference value and the conduction band difference value of the emitter and the base. Therefore, the method has higher current gain cut-off frequency, lower base resistance, lower BE junction capacitance and higher early voltage. Of these, inGaP/GaAs HBTs based on GaAs and InGaP materials are typically representative.
Double Heterojunction Bipolar Transistor (DHBT) is a structure of HBT, which is typically characterized by emitter, base and collector all made of different semiconductor materials, and by using their different energy band structures, to further improve HBT performance, for example, gaInP/GaAsSb/GaAs DHBT is currently of great interest compared to conventional InGaP/GaAs HBT, analyzed from Emitter-base junction theory, using GaInP/GaAsSb/junction instead of GaInP/GaAs junction, and GaAsSb/GaInP junction has a larger energy band difference, in particular, a significantly reduced conduction band energy difference (Δec), from the energy band structure. Therefore, the method can effectively reduce the starting Voltage Von of the emitter and the base, reduce the offset Voltage (Voff) of the emitter-collector, and the like.
However, the GaInP/GaAsSb/GaAs DHBT structure has a problem in practical production that, since the lattice constant of GaAsSb is larger than that of GaAs and GaInP, for growing a DHBT epitaxial structure by using an organometallic chemical vapor deposition (MOCVD) method, a GaAsSb base region is grown on a GaAs substrate, stress or lattice mismatch occurs, a defect occurs in the base material, the recombination probability of electrons and holes in the base region increases, resulting in an increase in base current I b, and thus a decrease in current gain β (β=i c/Ib). Therefore, how to increase the current gain β value of GaInP/GaAsSb/GaAs DHBT transistor becomes a problem to be solved.
Disclosure of Invention
The invention solves the technical problem of how to improve the current gain beta value of the double heterojunction bipolar transistor.
The application provides a double-heterojunction bipolar transistor which comprises an N-type GaAs subcollector layer, an N-type GaAs collector layer, a P-type base layer, an N-type GaInP emitter layer and an N-type InGaAs contact layer which are sequentially stacked, wherein the P-type base layer is of a multi-period repeated structure of four crystal lattice layers of P type GaAs（1-x）Sbx,A,d1/GaAs,B,d2/GaAs（1-y）Sby,C,d3/GaAs,B,d2, x and y represent the percentage of Sb components in a GaAsSb layer, the relation between x and y satisfies x not less than y, A, B, C represents the concentration value of P-type carriers, and A < B < C, and d 1、d2、d3 is the thickness of each layer.
Optionally, the percentages x, y of the Sb component in the GaAs （1-x）Sbx、GaAs（1-y）Sby layer are each less than 15%.
Optionally, the number of periods of the four crystal lattice layers of the P-type GaAs（1-x）Sbx,A,d1/GaAs,B,d2/GaAs（1-y）Sby,C,d3/GaAs,B,d2 is 15-20.
Optionally, the multicycle repeating structure of the P-type GaAs（1-x）Sbx,A,d1/GaAs,B,d2/GaAs（1-y）Sby,C,d3/GaAs,B,d2 four lattice layers satisfies the following weighted doping concentration relation:
D=(A×d1+2×B×d2+C×d3）/（d1+2d2+d3)
wherein D represents the value of the concentration of the P-type carrier of the P-type GaAsSb base layer in the conventional double-heterojunction bipolar transistor, and the value of D ranges from 2.5E19/cm 3 to 5E19/cm 3.
Optionally, the multicycle repeating structure of the P-type GaAs（1-x）Sbx,A,d1/GaAs,B,d2/GaAs（1-y）Sby,C,d3/GaAs,B,d2 four lattice layers satisfies the following weighted average interplanar spacing relation:
（6.0954 -0.4420×（1-z））=[（6.0954 -0.4420×（1-x））× d1+（6.0954 -0.4420×（1-y））×d3+5.6533×2×d2]/（d1+2d2+d3）
Where z represents the percentage of Sb component of the P-type GaAsSb base layer in a conventional double heterojunction bipolar transistor, the value of z ranges from 3% to 6%.
Optionally, the doping source of the P-type base layer is CCl 4 or CBr 4.
Optionally, the N-type GaAs subcollector layer is a Si-doped N-type GaAs material layer, the N-type GaAs collector layer is a Si-doped N-type GaAs material layer, the N-type GaInP emitter layer is a Si-doped N-type GaInP material layer, and the N-type InGaAs contact layer is a Si-doped N-type InGaAs material layer.
Optionally, the double heterojunction bipolar transistor further comprises a GaAs substrate layer, and the N-type GaAs subcollector layer is disposed on the GaAs substrate layer.
The double heterojunction bipolar transistor provided by the application has the following technical effects:
The base material is replaced by a multicycle repeated structure of P type GaAs （1-z）Sbz and D body material with P type GaAs（1-x）Sbx,A,d1/GaAs,B,d2/GaAs（1-y）Sby,C,d3/GaAs,B,d2 four-layer lattice layers, and the energy bands of the GaAs （1-x）Sbx,A/GaAs,B/GaAs（1-y）Sby, C/GaAs and B four-layer lattice layers are expressed as valence bands Ec (GaAs （1-x）Sbx,A)<Ec(GaAs（1-x）Sbx, C) < Ec (GaAs, B) and conduction bands Ev (GaAs （1-x）Sbx,A)<Ev(GaAs,B)<Ev(GaAs（1-x）Sbx, C) due to the fact that the concentration of P type carriers A < B < C. The energy band structure can bind electrons of the base layer in the GaAs （1-x）Sbx and the A layer, bind holes of the base layer in the GaAs （1-y）Sby and the C layer, and have the GaAs and the B layer at intervals, and can more effectively separate electrons from holes in physical space and reduce the recombination probability of the electrons and the holes in the base region, so that the collector current I c can be effectively improved, and the current gain beta value is further improved.
Drawings
FIG. 1 is a schematic diagram of a prior art double heterojunction bipolar transistor;
fig. 2 is a schematic diagram of a double heterojunction bipolar transistor according to a first embodiment of the present invention;
FIG. 3 is a schematic diagram of a multi-period repeating structure of four lattice layers of the P-type GaAs（1-x）Sbx,A,d1/GaAs,B,d2/GaAs（1-y）Sby,C,d3/GaAs,B,d2 in accordance with a first embodiment of the present invention;
fig. 4 is an energy band diagram of a multicycle repeating structure of four lattice layers of P-type GaAs（1-x）Sbx,A,d1/GaAs,B,d2/GaAs（1-y）Sby,C,d3/GaAs,B,d2 in a first embodiment of the invention.
The correspondence of reference numerals and component names is as follows:
10-N type GaAs subcollector layer, 20-N type GaAs collector layer, 30-P type base layer, 40-N type GaInP emitter layer, 50-N type InGaAs contact layer, and 60-GaAs substrate layer.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Before describing the embodiments of the present application in detail, the technical concept of the present application will be briefly described, in which electron and hole recombination easily occurs in the base of the current GaInP/GaAsSb/GaAs DHBT transistor, resulting in a problem of reduced current gain. Therefore, the application provides a double heterojunction bipolar transistor, the base region material of the DHBT transistor is replaced by a multi-period repeated structure of four crystal lattice layers of P type GaAs（1-x）Sbx,A,d1/GaAs,B,d2/GaAs（1-y）Sby,C,d3/GaAs,B,d2 by P type GaAs （1-z）Sbz and D body material, the energy band structure can realize separation of electrons and holes in physical space, and the recombination probability of the electrons and the holes in the base region is reduced, so that the collector current I c can be effectively improved, and the current gain beta value is further improved. The specific principles of the double heterojunction bipolar transistor of the present application will be described in connection with further embodiments.
Specifically, as shown in fig. 2, the double heterojunction bipolar transistor of the first embodiment includes an N-type GaAs subcollector layer 10, an N-type GaAs collector layer 20, a P-type base layer 30, an N-type GaInP emitter layer 40, and an N-type InGaAs contact layer 50, which are sequentially stacked, wherein the P-type base layer 30 is a multicycle repeating structure of four lattice layers of P-type GaAs（1-x）Sbx,A,d1/GaAs,B,d2/GaAs（1-y）Sby,C,d3/GaAs,B,d2, x and y represent percentages of Sb components in GaAsSb layers, a relationship between x and y satisfies x being greater than or equal to y, A, B, C represents a P-type carrier concentration value, a < B < C is satisfied, and d 1、d2、d3 is a thickness of each layer.
Illustratively, as shown in fig. 3, gaAs （1-x）Sbx layer 31, gaAs layer 32, gaAs （1-y）Sby layer 33, gaAs layer 34 in P-type base layer 30 are alternately laminated with a plurality of cycles. In one or more embodiments, the percentage x of the Sb component in the GaAs （1-x）Sbx layer and the percentage y of the Sb component in the GaAs （1-y）Sby layer are each less than 15%, and the number of cycles of the multicycle repeating structure is 15-20. By adjusting the percentages x and y of the Sb components in the above ranges, the thicknesses of the GaAs （1-x）Sbx layer and the GaAs （1-y）Sby layer are enabled to be the same as the average interplanar spacing of the conventional GaAsSb base layer.
As shown in fig. 4, the energy band of GaAs （1-x）Sbx,A/GaAs,B/GaAs（1-y）Sby, C/GaAs, B four lattice layers is expressed as valence band Ec (GaAs （1-x）Sbx,A)<Ec(GaAs（1-x）Sbx, C) < Ec (GaAs, B), conduction band Ev (GaAs （1-x）Sbx,A)<Ev(GaAs,B)<Ev(GaAs（1-x）Sbx, C) due to the p-type carrier concentration a < B < C. The multi-period repeated structure of the four-layer lattice layer can be adopted to bind electrons of the base layer in the GaAs （1-x）Sbx,A,d1 layer, holes of the base layer in the GaAs （1-y）Sby,C,d3 layer, and GaAs and B layers are arranged in the middle, so that separation of electrons and holes in physical space can be more effectively realized, the recombination probability of the electrons and the holes in a base region is reduced, the collector current I c can be effectively improved, and the current gain beta value is further improved.
By adjusting the relative thicknesses of the GaAs （1-x）Sbx layer, the GaAs （1-y）Sby layer and the GaAs layer in the multicycle repeating structure and the percentages x and y of the Sb components, the crystal face spacing of the superlattice material is the same as that of a conventional base region GaAsSb bulk material, and a required energy band structure is obtained, as shown in fig. 4, the energy band structure is a II-type energy band structure, and the starting voltage of a BE junction can BE ensured to BE consistent with that of a conventional double-heterojunction bipolar transistor.
Illustratively, the multicycle repeating structure of the P-type GaAs（1-x）Sbx,A,d1/GaAs,B,d2/GaAs（1-y）Sby,C,d3/GaAs,B,d2 four lattice layers satisfies the following weighted doping concentration relation:
D=(A×d1+2×B×d2+C×d3）/（d1+2d2+d3)
wherein D represents the value of the concentration of the P-type carrier of the P-type GaAsSb base layer in the conventional double-heterojunction bipolar transistor, and the value of D ranges from 2.5E19/cm 3 to 5E19/cm 3.
Illustratively, the multicycle repeating structure of the P-type GaAs（1-x）Sbx,A,d1/GaAs,B,d2/GaAs（1-y）Sby,C,d3/GaAs,B,d2 four lattice layers satisfies the following weighted average interplanar spacing relationship:
（6.0954 -0.4420×（1-z））=[（6.0954 -0.4420×（1-x））×d1+（6.0954 -0.4420×（1-y））×d3+5.6533×2×d2]/（d1+2d2+d3）
Where z represents the percentage of Sb component of the P-type GaAsSb base layer in a conventional double heterojunction bipolar transistor, the value of z ranges from 3% to 6%.
Illustratively, the doping source of the P-type base layer 30 is cci 4 or CBr 4.
In one or more embodiments, N-type GaAs subcollector layer 10 is a Si-doped N-type GaAs material layer, N-type GaAs collector layer 20 is a Si-doped N-type GaAs material layer, N-type GaInP emitter layer 40 is a Si-doped N-type GaInP material layer, and N-type InGaAs contact layer 50 is a Si-doped N-type InGaAs material layer. The doping concentration of each layer and the thickness of each layer can be set as required.
Further, the double heterojunction bipolar transistor further comprises a GaAs substrate layer 60, and the n-type GaAs subcollector layer 10 is stacked on the GaAs substrate layer 60.
Illustratively, in order to illustrate the advantages of the double heterojunction bipolar transistor of the present embodiment over the conventional double heterojunction bipolar transistor, samples of two double heterojunction bipolar transistors were prepared separately for testing. The parameters of thickness, doping concentration, thickness of superlattice layer, cycle number and the like of each layer of the double heterojunction bipolar transistor of the embodiment are as follows:
The doping concentration of Si of the N-type GaAs subcollector layer 10 is 4E18/cm 3, and the thickness is 600nm;
the doping concentration of Si of the N-type GaAs collector layer 20 is 3E16/cm 3, and the thickness is 1500nm;
the number of cycles of the multicycle repeated structure of the P-type GaAs0.9Sb0.1,2E19/cm3,1nm/GaAs,3E19/cm3,1nm/GaAs0.9Sb0.1,4E19/cm3,1nm/GaAs,3E19/cm3,1nm four-layer lattice layer is 20, and the total thickness is 80nm;
the doping concentration of Si of the N-type GaInP emitter layer 40 is 5E17/cm 3, and the thickness is 40nm;
The N-type InGaAs contact layer 50 has a Si doping concentration of 1E19/cm3 and a thickness of 100nm.
In contrast, as shown in fig. 1, parameters such as thickness, doping concentration and the like of each layer of the conventional double heterojunction bipolar transistor are as follows:
The N-type GaAs subcollector layer has Si doping concentration of 4E18/cm 3 and thickness of 600nm;
the N-type GaAs collector layer has Si doping concentration of 3E16/cm 3 and thickness of 1500nm;
P-type GaAs （1-z）Sbz, a D base layer, wherein the percentage z of the Sb component is 0.05, the percentage (1-z) of the As component is 0.95, the P-type doping concentration is 3E19/cm < 3 >, and the thickness is 80nm;
The N-type GaInP emitter layer comprises Ga component with the percentage of 0.515, si doping concentration of 5E17/cm 3 and thickness of 40nm;
The doping concentration of Si is 1E19/cm 3, and the thickness of the N-type InGaAs contact layer is 100nm.
When two double heterojunction bipolar transistors are prepared, MOCVD is adopted to grow each layer, and other functional layers are grown under the same growth conditions, wherein the difference is that the base layer is different in structure and process.
Next, tests were performed to obtain indices von=1.061V, voff=0.049v, β=82 for the double heterojunction bipolar transistor of the present embodiment, and indices von=1.061V, voff=0.049v, β=65 for the conventional double heterojunction bipolar transistor. According to the test result, the current gain value β of the double heterojunction bipolar transistor of the embodiment is increased from 65 to 82, and the current gain is increased by 26% compared with the conventional double heterojunction bipolar transistor.
While certain embodiments have been shown and described, it would be appreciated by those skilled in the art that changes and modifications may be made without departing from the principles and spirit of the invention, the scope of which is defined in the claims and their equivalents.
Claims (7)
1. A double-heterojunction bipolar transistor is characterized by comprising an N-type GaAs subcollector layer, an N-type GaAs collector layer, a P-type base layer, an N-type GaInP emitter layer and an N-type InGaAs contact layer which are sequentially stacked, wherein the P-type base layer is of a multi-period repeated structure of P-type GaAs（1-x）Sbx,A,d1/GaAs,B,d2/GaAs（1-y）Sby,C,d3/GaAs,B,d2 four-layer lattice layers, x and y represent the percentage of Sb components in a GaAsSb layer, the relation between x and y satisfies x not less than y, A, B, C represents the concentration value of P-type carriers, A < B < C is satisfied, d 1、d2、d3 is the thickness of each layer, and the percentages x and y of Sb components in the GaAs （1-x）Sbx、GaAs（1-y）Sby layer are smaller than 15%.
2. The double heterojunction bipolar transistor of claim 1, wherein the number of periods of the P-type GaAs（1-x）Sbx,A,d1/GaAs,B,d2/GaAs（1-y）Sby,C,d3/GaAs,B,d2 four lattice layers is 15-20.
3. The double-heterojunction bipolar transistor of claim 1, wherein the multicycle repeating structure of the P-type GaAs（1-x）Sbx,A,d1/GaAs,B,d2/GaAs（1-y）Sby,C,d3/GaAs,B,d2 four lattice layers satisfies the following weighted doping concentration relation:
D=(A×d1+2×B×d2+C×d3）/（d1+2d2+d3)
wherein D represents the value of the concentration of the P-type carrier of the P-type GaAsSb base layer in the conventional double-heterojunction bipolar transistor, and the value of D ranges from 2.5E19/cm 3 to 5E19/cm 3.
4. The double-heterojunction bipolar transistor of claim 1, wherein the multicycle repeating structure of the P-type GaAs（1-x）Sbx,A,d1/GaAs,B,d2/GaAs（1-y）Sby,C,d3/GaAs,B,d2 four lattice layers satisfies the following weighted average interplanar spacing relationship:
（6.0954 -0.4420×（1-z））=[（6.0954 -0.4420×（1-x））× d1+（6.0954 -0.4420×（1-y））×d3+5.6533×2×d2]/（d1+2d2+d3）
Where z represents the percentage of Sb component of the P-type GaAsSb base layer in a conventional double heterojunction bipolar transistor, the value of z ranges from 3% to 6%.
5. The double heterojunction bipolar transistor of claim 1, wherein the doping source of the P-type base layer is CCl 4 or CBr 4.
6. The double heterojunction bipolar transistor of claim 1 wherein the N-type GaAs subcollector layer is a Si-doped N-type GaAs material layer, the N-type GaAs collector layer is a Si-doped N-type GaAs material layer, the N-type GaInP emitter layer is a Si-doped N-type GaInP material layer, and the N-type InGaAs contact layer is a Si-doped N-type InGaAs material layer.
7. The double heterojunction bipolar transistor of claim 1, further comprising a GaAs substrate layer, wherein the N-type GaAs subcollector layer stack is disposed on the GaAs substrate layer.
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