CN118870796B

CN118870796B - Layout structure and array structure of semiconductor devices, layout structure of integrated circuits

Info

Publication number: CN118870796B
Application number: CN202310416983.6A
Authority: CN
Inventors: 王学伟; 张涛
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2023-04-13
Filing date: 2023-04-13
Publication date: 2025-10-03
Anticipated expiration: 2043-04-13
Also published as: CN118870796A

Abstract

The embodiment of the disclosure discloses a layout structure of a semiconductor device, an array structure and a layout structure of an integrated circuit, wherein the layout structure of the semiconductor device comprises a plurality of first active areas, two grid connection structures, two second grid connection structures, wherein the plurality of first active areas extend along a first direction, each grid connection structure comprises 2N first grids and 2N second grids which are mutually connected, the first grids correspond to the first active areas, N is a positive integer, 2N third grids are located between the two grid connection structures and correspond to the N second grids of the two grid connection structures, the remaining N third grids are located on one side, away from the other grid connection structure, of the grid connection structure, correspond to the remaining N second grids, the second grids and the third grids extend along the second direction, and the second direction is perpendicular to the first direction.

Description

Layout structure of semiconductor device, array structure of semiconductor device, and layout structure of integrated circuit

Technical Field

The present disclosure relates to the field of semiconductor technology, and in particular, to a layout structure and an array structure of a semiconductor device, and a layout structure of an integrated circuit.

Background

In a semiconductor device, such as a dynamic random access memory (DRAM, dynamic Random Access Memory), a word line may be used as a conductive line that carries the gate voltage required to drive one or more transistors of a memory cell. Wherein the transistor is operable in response to a potential state of the word line such that the dynamic random access memory can write data to or read data from the memory cell through the transistor.

As chip size, capacity increases, the line delay caused by such word lines may be considered one of the most important delay factors limiting the operating speed of dynamic random access memories. In order to minimize the line delay of such word lines, sub-word line drivers (SWD, sub Wordline Driver) for dividing a long main word line (MWL, main Wordline) into a plurality of sub-word lines (SWL, sub Wordline) and for driving each sub-word line have been developed.

Disclosure of Invention

In view of the above, the embodiments of the present disclosure provide a layout structure and an array structure of a semiconductor device, and a layout structure of an integrated circuit. In one aspect, an embodiment of the present disclosure provides a layout structure of a semiconductor device, including a plurality of first active regions each extending along a first direction;

The two grid connection structures are arranged along the first direction, and each grid connection structure comprises 2N first grids and 2N second grids which are mutually connected, wherein the first grids correspond to the first active area;

The grid connection structure comprises two grid connection structures, 2N third grids, wherein the N third grids are located between the two grid connection structures and correspond to N second grids of the two grid connection structures, the rest N third grids are located on one side, away from the other grid connection structure, of one grid connection structure and correspond to the rest N second grids of the one grid connection structure, the second grids and the third grids extend along a second direction, and the second direction is perpendicular to the first direction.

In one embodiment, 2N first gates of each of the gate connection structures are physically connected;

The 2N second grids of each grid connection structure are connected to one end of the 2N first grids, or the 2N second grids of each grid connection structure are connected to two ends of the plurality of first grids.

In one embodiment, the two gate connection structures include a first gate connection structure and a second gate connection structure;

the first grid electrode connecting structure and the 2N second grid electrodes of the second grid electrode connecting structure are connected to one ends of the 2N first grid electrodes of the corresponding grid electrode connecting structure;

The first grid electrode connecting structure and the 2N second grid electrodes of the second grid electrode connecting structure comprise a first part and a second part; the first part is N second grids close to the first grid, and the second part is N second grids far away from the first grid;

the distance between the first part of the first gate connecting structure and the first part of the second gate connecting structure along the first direction is a first distance, and the distance between the second part of the first gate connecting structure and the second part of the second gate connecting structure along the first direction is a second distance.

In one embodiment, the first distance is greater than the second distance;

The N third gates are located between the first portion of the first gate connection structure and the first portion of the second gate connection structure, and the remaining N third gates are located on one side of the second portion of the first gate connection structure or one side of the second portion of the second gate connection structure.

In one embodiment, the first distance is less than the second distance;

the N third gates are located between the second portion of the first gate connection structure and the second portion of the second gate connection structure, and the remaining N third gates are located on one side of the first portion of the first gate connection structure or one side of the first portion of the second gate connection structure.

In one embodiment, the first and second portions of the 2N second gates each comprise two directly connected second gates, the N third gates comprise two spaced apart third gates, and both ends of the two directly connected second gates are substantially flush with both ends of the two spaced apart third gates along the first direction.

In one embodiment, the projection shapes of the first grid electrodes on the plane where the first active area is located comprise U shapes or inverted U shapes, the 2N first grid electrodes comprise a third part and a fourth part, the third part is N first grid electrodes close to the second grid electrodes, the fourth part is N first grid electrodes far away from the second grid electrodes, and the projection shapes of the first grid electrodes in the third part and the first grid electrodes in the fourth part on the plane where the first active area is located are different.

In one embodiment, the projection shapes of the second gate and the third gate on the plane where the first active region is located each include a rectangle.

In one embodiment, an edge of the first gate in the third portion along the second direction is substantially flush with an edge of the second gate in the first portion along the second direction, and an edge of the first gate in the fourth portion along the second direction is substantially flush with an edge of the second gate in the second portion along the second direction.

In one embodiment, the distances between the N third gates and the corresponding N second gates of the first gate connection structure along the first direction are a third distance, and the distances between the N third gates and the corresponding N second gates of the second gate connection structure along the first direction are a fourth distance;

the distances between the remaining N third grids and corresponding N second grids adjacent to the grid connection structure in the two grid connection structures along the first direction are fifth distances;

the third distance is equal to the fourth distance, and the fourth distance is equal to the fifth distance.

In one embodiment, a dimension of the first gate along the first direction is greater than a dimension of the second gate along the first direction;

The second gate has a dimension along the first direction that is equal to a dimension of the third gate along the first direction.

In one embodiment, 2N first gates in the two gate connection structures are all parallel and both ends are substantially flush along the first direction;

The 2N second gates in the two gate connection structures are all parallel and both ends are substantially flush along the first direction.

In one embodiment, the transistors corresponding to the first gate comprise PMOS transistors, and the transistors corresponding to the second gate and the transistors corresponding to the third gate comprise NMOS transistors.

In one embodiment, the layout structure of the semiconductor device further comprises a plurality of second active regions, wherein the second active regions correspond to the second grid electrode and the third grid electrode.

In another aspect, an embodiment of the present disclosure provides an array structure of a semiconductor device, including a plurality of layout structures of the semiconductor device as described in the above embodiments of the present disclosure.

In one embodiment, the layout structures of the plurality of semiconductor devices are arranged along a first direction, and the layout structure of each of the plurality of semiconductor devices has the same structural arrangement.

In one embodiment, both ends of the layout structure of the plurality of semiconductor devices are substantially flush along the first direction.

In yet another aspect, an embodiment of the present disclosure provides a layout structure of an integrated circuit, including one or more array structures of semiconductor devices as described in the above embodiments of the present disclosure, and

And each sub word line is connected with an active area corresponding to a first grid electrode and an active area corresponding to a second grid electrode in one grid electrode connecting structure through a first through hole.

In one embodiment, the layout structure of the integrated circuit further comprises a plurality of main word lines, wherein each main word line is connected with all first gates and all second gates in one gate connection structure through a second via hole.

In one embodiment, the integrated circuit is a dynamic random access memory.

The layout structure of the semiconductor device comprises a plurality of first active areas, two Gate connecting structures and 2N third gates, wherein each Gate connecting structure comprises 2N first gates and 2N second gates which are connected with each other, the N third gates are arranged between the two Gate connecting structures, the N third gates correspond to the N second gates of the two Gate connecting structures, the other remaining N third gates are arranged on one side, away from the other Gate connecting structure, of one Gate connecting structure, the remaining N third gates correspond to the remaining N second gates in the adjacent Gate connecting structure, the adjacent two Gate connecting structures share one group of third gates, the number of the third gates in the layout structure of the semiconductor device is reduced, the area of the semiconductor device is reduced, the integration level of the device is improved, in addition, under the condition that the total area of the layout structure of the semiconductor device is unchanged, the size of the semiconductor device is increased, namely the drain leakage current of the semiconductor device is improved, namely the drain electrode leakage current of the semiconductor is increased, the drain electrode is increased, and the drain electrode leakage current of the semiconductor device is increased, namely the drain electrode leakage current of the semiconductor is increased by at least the second Gate is increased by the size of the third Gate, namely, the drain electrode is increased by the size of the semiconductor device is increased by the drain electrode leakage current of the drain electrode is increased by the drain electrode of the semiconductor device.

Drawings

FIG. 1a is a schematic diagram of a partial circuit of a memory provided in an embodiment of the present disclosure;

FIG. 1b is a schematic diagram of a layout structure of a semiconductor device with sub-word line drivers provided in an embodiment of the present disclosure;

FIG. 2 is a schematic circuit diagram of a sub-word line driver provided in an embodiment of the present disclosure;

FIG. 3a is a schematic circuit diagram of a sub-word line driver provided in an embodiment of the present disclosure under a first operating condition;

FIG. 3b is a schematic diagram of a sub-word line driver according to an embodiment of the present disclosure under a second operating condition;

FIG. 3c is a schematic diagram of a circuit configuration of a sub-word line driver provided in an embodiment of the present disclosure under a third operating condition;

FIG. 4 is a circuit structure of two sub-word lines connected to two NTK_Sf2 transistors respectively, which is improved in the embodiment of the present disclosure, to a circuit structure of two sub-word lines commonly connected to one NTK_Sf2 transistor;

fig. 5 is a schematic layout structure of a semiconductor device according to an embodiment of the present disclosure;

Fig. 6 is a schematic layout structure of another semiconductor device provided in an embodiment of the present disclosure;

fig. 7 is a schematic layout structure of still another semiconductor device provided in an embodiment of the present disclosure;

FIG. 8 is an enlarged schematic diagram of 2N first gates in the first gate connection structure of FIG. 5;

FIG. 9 is an enlarged schematic diagram of the first gate connection structure of FIG. 5;

fig. 10 is a schematic diagram of a layout structure of a plurality of semiconductor devices provided in an embodiment of the present disclosure;

Fig. 11 is a schematic layout structure of a plurality of sub word lines provided in an embodiment of the present disclosure.

In the drawings (which are not necessarily drawn to scale), like numerals may describe similar components in different views. Like reference numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example and not by way of limitation, various embodiments discussed herein.

Detailed Description

In order to make the technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

The present disclosure is described more specifically in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more fully apparent from the following description and appended claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the disclosure.

It is to be understood that the meaning of "on," "above," "over," and "above" in this disclosure should be read in the broadest manner so that "on" means not only that it is "on" something and there is no intervening feature or layer therebetween (i.e., directly on something), but also that it is "on" and there is intervening feature or layer therebetween.

Further, spatially relative terms such as "on," "above," "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated for ease of description. In addition to the orientations depicted in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

In the presently disclosed embodiments, the term "substrate" refers to a material upon which subsequent layers of material are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may comprise a variety of semiconductor materials, such as silicon, silicon germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

In the presently disclosed embodiments, the term "layer" refers to a portion of material that includes a region having a thickness. The layer may extend over the entirety of the underlying or overlying structure, or may have a range that is less than the range of the underlying or overlying structure. Further, the layer may be a region of homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure, or the layer may be between any horizontal facing at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along an inclined surface. The layer may comprise a plurality of sub-layers. For example, the interconnect layer may include one or more conductors and contact sublayers (in which interconnect lines and/or via contacts are formed), and one or more dielectric sublayers.

In the presently disclosed embodiments, the terms "first," "second," and the like are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.

The disclosed embodiments relate to a layout structure of a semiconductor device that will be used in subsequent processes to form at least a portion of the final device structure. Here, the final device may include a memory including, but not limited to, a dynamic random access memory, which is described below as an example only, and is not intended to limit the scope of the present disclosure.

With the development of the technology of the dynamic random access memory, the architecture of the memory cell array is from 8F ² to 6F ² to 4F ², however, the dynamic random access memory is composed of a plurality of memory cells, whether the array architecture of 8F ² or 4F ² is the array architecture, each memory cell can be composed of a Transistor and a Capacitor controlled by the Transistor, namely, the dynamic random access memory is an architecture of 1 Transistor (T) and 1 Capacitor (C, capacitor) (1T 1C), and the main function principle is to use the quantity of stored charges in the Capacitor to represent whether a binary bit is l or 0.

Fig. 1a is a schematic diagram of a memory adopting a 1T1C architecture according to an embodiment of the disclosure, as shown in fig. 1a, a drain electrode of a transistor T is electrically connected to a Bit Line (BL), a source electrode of the transistor T is electrically connected to one of electrode plates of a capacitor C, another electrode plate of the capacitor C may be connected to a reference voltage, which may be a ground voltage or another voltage, a gate electrode of the transistor T is connected to a Word Line (WL), and a voltage is applied to the Word Line WL to control the transistor T to be turned on or off, and the Bit Line BL is used to perform a read or write operation on the transistor T when the transistor T is turned on.

Fig. 1b is a schematic layout diagram of a semiconductor device with sub-word line drivers provided in an embodiment of the present disclosure. As shown in fig. 1b, the dynamic random access memory may include at least one memory Cell Array (CA), and a circuit for controlling the Cell Array including the main word line. FIG. 1b illustrates a plurality of memory cell arrays CA, each of which may include at least one Bit line sense amplifier (BLSA, bit LINE SENSE AMPLIFIER) and at least one sub-word line driver SWD.

Each memory cell array CA may include a plurality of memory cells in an array shape for storing data. The memory cell array may include a plurality of sub word lines SWL, each of which may be coupled to a plurality of memory cells, the plurality of sub word lines may be sequentially and successively arranged over the memory cell array, and the plurality of sub word lines may be connected to one main word line MWL.

In order to minimize the line delay of the main word line, it has been developed to divide the long main word line and the main word line driver into a plurality of sub word lines and a plurality of sub word line drivers for driving each corresponding sub word line. The sub word line driver may selectively drive one or more sub word lines in response to a main word line driving signal. In this case, the main word line driving signal may represent a memory cell driving signal transmitted through the main word line.

In fig. 1b, the sub word line drivers may be divided into an EVEN sub word line driver circuit SWD (EVEN) disposed along one side of the memory cell array and an ODD sub word line driver circuit SWD (ODD) disposed along the opposite side with respect to the memory cell array. The even sub-word line driver circuits may drive one or more even sub-word lines and the odd sub-word line driver circuits may drive one or more odd sub-word lines. It is to be understood that the even sub-word line driver circuits and the odd sub-word line driver circuits have substantially similar structures, and the even sub-word line driver circuits and the odd sub-word line driver circuits are hereinafter collectively referred to as sub-word line drivers. The sense amplifier may sense and amplify cell data of an associated memory cell array. The sense amplifier may be disposed along the other side of the memory cell array.

FIG. 2 illustrates a circuit schematic of a sub-word line driver in one embodiment. As shown in fig. 2, the sub-word line driver SWD is configured to drive four sub-word lines SWL, and includes four P-type Metal-Oxide-Semiconductor (PMOS) transistors and four N-type Metal-Oxide-Semiconductor (NMOS) transistors, and gates corresponding to the four PMOS transistors and the four NMOS transistors are connected to each other to form a main word line MWL. Each sub-word line SWL includes one PMOS transistor and one NMOS transistor, wherein the PMOS transistor and the NMOS transistor may be formed as inverters for controlling the switching state of the target sub-word line. Wherein the transistor control voltage VPP turns on the sub-word line or the control voltage VKK turns off the sub-word line.

It should be noted that the sub-word line driver may further include another NMOS transistor connected to both the PMOS transistor and the NMOS transistor, where the another NMOS transistor may be a Noise suppression unit (Noise Killer), and the Noise suppression unit may be configured to input VKK voltage to the other sub-word line to turn off when a certain sub-word line is turned on, so as to prevent the signal that turns on the sub-word line from being affected.

However, the sub-word line driver SWD is prone to induce leakage current of static power consumption, which includes subthreshold leakage current between source and drain and gate-induced drain leakage current occurring in the gate-drain overlapped region, especially for a short Channel (Channel) device, which is more serious in the phenomenon of suffering from Hot carrier injection effect (HCI, hot CARRIER IN jection effect), and when the Channel length is smaller, increasing the drain terminal voltage, the source-drain depletion region will get closer (punch through) so that the electric field passes through from the drain to the source, and thus electrons injected into the Channel from the source terminal increase, resulting in an increase in leakage current.

For example, referring to fig. 3a, 3b, 3c, three different operating conditions of the sub-word line driver SWD are shown, wherein H shown in fig. 3a-3c is high and L is low, in the first operating condition shown in fig. 3a, the PMOS transistor (ptk_sv) is in an off-state, the NMOS transistor (ntk_sv1) is in an on-state, the other NMOS transistor (ntk_sv2) is in an off-state, and the corresponding sub-word line SWL is in an off-state. In a second operating condition shown in fig. 3b, the PMOS transistor (ptk_sv) is in an off-state, the NMOS transistor (ntk_sv1) is in an on-state, the other NMOS transistor (ntk_sv2) is in an on-state, and the corresponding sub-word line SWL is in an off-state. In a third operating condition shown in fig. 3c, the PMOS transistor (ptk_sv) is in an on state, the NMOS transistor (ntk_sv1) is in an off state, the other NMOS transistor (ntk_sv2) is in an off state, and the corresponding sub-word line SWL is in an on state. The PMOS transistor (ptk_sv) is highly susceptible to gate-induced drain leakage current GIDL under the operating conditions shown in fig. 3a and 3b, while subthreshold leakage current (Ioff) is highly susceptible under the operating conditions shown in fig. 3 c.

In view of this, in order to solve one or more of the above problems, the embodiment of the disclosure provides a circuit structure of a semiconductor device, referring to fig. 4, fig. 4 is an improvement of the circuit structure provided in the embodiment of the disclosure, in which two sub-word lines are respectively connected to two ntk_sv2 transistors, into a circuit structure in which two sub-word lines are commonly connected to one ntk_sv2 transistor, wherein in the improved circuit structure, two sub-word lines (WL-a and WL-B) are commonly connected to one ntk_sv2 transistor, so that the number of ntk_sv2 transistors in a sub-word line driver can be reduced, a larger area can be saved, and the integration level of the semiconductor device can be improved, and simultaneously, the channel lengths of the remaining transistors (PMOS (ptk_sv), NMOS (ntk_sv1), NMOS (ntk_sv2)) can be increased, the hot carrier effects of the NMOS transistors (ntk_sv1, ntk_sv2) can be reduced, and the subthreshold leakage currents and the gate leakage currents can be reduced.

The embodiment of the disclosure also provides a layout structure of the semiconductor device corresponding to the circuit structure of the semiconductor device, wherein the layout structure of the semiconductor device comprises a plurality of first active regions, a plurality of second active regions and a plurality of first conductive regions, wherein the plurality of first active regions extend along a first direction;

Here and hereinafter, for convenience in describing embodiments of the present disclosure, the first direction is an extension direction of the first active region, an extension direction of each of the plurality of first active regions is the same and is a first direction, and the second direction is a direction perpendicular to the first direction and parallel to a plane in which the first active regions are located. In some specific examples, the first direction may be represented as a Y-axis direction in the drawing, the second direction may be represented as an X-axis direction in the drawing, and the plane in which the first active region is located may be represented as an XOY plane in the drawing.

Referring to fig. 5, fig. 5 is a schematic diagram of a layout structure of a semiconductor device according to an embodiment of the present disclosure, where the layout structure of the semiconductor device may include a plurality of first active regions 401, a plurality of second active regions 402, and a plurality of gate connection structures 50, where the number of first gates 501 and second gates 502 in each gate connection structure 50 is the same, the transistor types represented by the first gates 501 and the second gates 502 are different, and the transistor types represented by the first gates 501 and the second gates 502 may be interchanged. Illustratively, the transistor corresponding to the first gate may include a PMOS transistor, the transistor corresponding to the second gate may include an NMOS transistor, or the transistor corresponding to the first gate may include an NMOS transistor, and the transistor corresponding to the second gate may include a PMOS transistor. Here, the first active region 401 corresponds to the first gate 501, and a portion of the second active region 402 corresponds to the second gate 502.

In some embodiments, 2N first gates of each gate connection structure are physically connected, 2N second gates of each gate connection structure are connected at one end of the 2N first gates, or 2N second gates of each gate connection structure are connected at two ends of the plurality of first gates.

Here, the physical connection may be understood as a direct connection between the connected objects by means of contact or a direct connection by means of a connection structure such as a metal wire, a metal via, etc., and no other connection object having a non-connection structure is inserted between the physical connection objects. That is, the 2N first gates of each gate connection structure are directly connected along the second direction, the 2N second gates of each gate connection structure are directly connected along the second direction, the directly connected 2N second gates may be all disposed at one end of the directly connected 2N first gates, and the directly connected 2N second gates may be split into two parts, which are disposed at two ends of the physically connected 2N first gates, respectively.

Illustratively, referring to fig. 5, 2N first gates directly connected in each gate connection structure are formed on the right side, and 2N second gates directly connected are formed on the left side, i.e., 2N first gates are disposed on the right side of 2N second gates.

Referring to fig. 6, fig. 6 is a schematic layout structure of another semiconductor device according to an embodiment of the present disclosure, wherein 2N first gates directly connected in each gate connection structure are formed in the middle, N second gates of the 2N second gates are directly connected and formed on the left, and the remaining N second gates are directly connected and formed on the right, i.e., the 2N second gates are respectively disposed at two ends of the 2N first gates. The specific connection structure of the first grid electrode and the second grid electrode can be selected and set according to actual requirements.

In some embodiments, 2N first gates of the two gate connection structures are parallel and both ends are substantially flush along the first direction, and 2N second gates of the two gate connection structures are parallel and both ends are substantially flush along the first direction.

Illustratively, referring to fig. 5,N = 2, the two gate connection structures include a first gate connection structure 50a and a second gate connection structure 50b, 4 first gates 501 in the first gate connection structure 50a and 4 first gates 501 in the second gate connection structure 50b are all parallel, and two ends of the 4 first gates 501 in the first gate connection structure 50a are substantially flush with two ends of the 4 first gates 501 in the second gate connection structure 50b along the Y-axis direction, as indicated by a dashed line A-A', the substantially flush including non-flush within practically allowable manufacturing error range criteria. The 4 second gates 502 in the first gate connection structure 50a and the 4 second gates 502 in the second gate connection structure 50B are all parallel, and both ends of the 4 second gates 502 in the first gate connection structure 50a and both ends of the 4 second gates 502 in the second gate connection structure 50B are all substantially flush in the Y-axis direction, as indicated by a broken line B-B ".

The layout structure of the semiconductor device further comprises a plurality of third gates 503, a part of the second active regions 402 further correspond to the third gates 503, and the types of transistors characterized by the third gates 503 and the first gates 501 are the same, wherein the plurality of third gates 503 may be all arranged between two gate connection structures, may be all arranged at one side of one gate connection structure far away from the other gate connection structure, may also be partially arranged between two gate connection structures, and the rest of the third gates are arranged at one side of one gate connection structure far away from the other gate connection structure.

In the embodiment of the disclosure, N third gates 503 of the 2N third gates 503 are disposed between two gate connection structures, and the remaining N third gates 503 are disposed on a side of one gate connection structure away from the other gate connection structure, where the N third gates 503 correspond to the N second gates of the two gate connection structures, and the remaining N third gates correspond to the remaining N second gates of the adjacent one gate connection structure.

In some embodiments, the two gate connection structures comprise a first gate connection structure and a second gate connection structure, wherein 2N second gates of the first gate connection structure and the second gate connection structure are connected to one ends of the 2N first gates of the corresponding gate connection structure, each of the 2N second gates of the first gate connection structure and the second gate connection structure comprises a first portion and a second portion, the first portion is N second gates close to the first gate, the second portion is N second gates far away from the first gate, a distance between the first portion of the first gate connection structure and the first portion of the second gate connection structure along the first direction is a first distance, and a distance between the second portion of the first gate connection structure and the second portion of the second gate connection structure along the first direction is a second distance.

Illustratively, referring to FIG. 5, each of the 2N second gates of the first gate connection structure 50a is connected to one end of the 2N first gates of the first gate connection structure 50a, wherein the 2N second gates of the first gate connection structure 50a include a first portion 502-1 and a second portion 502-2, the first portion 502-1 is the N second gates adjacent to the first gate 501, and the second portion 502-2 is the N second gates distant from the first gate 501. The 2N second gates of the second gate connection structure 50b are all connected to one end of the 2N first gates of the second gate connection structure 50b, wherein the 2N second gates of the second gate connection structure 50b include a first portion 502-3 and a second portion 502-4, the first portion 502-3 is N second gates close to the first gate 501, and the second portion 502-4 is N second gates far away from the first gate 501.

The distance between the first portion 502-1 of the second gate of the first gate connection structure 50a and the first portion 502-3 of the second gate connection structure 50b along the Y-axis direction is a first distance L1, and the distance between the second portion 502-2 of the second gate of the first gate connection structure 50a and the second portion 502-4 of the second gate connection structure 50b along the Y-axis direction is a second distance L2. In some specific embodiments, the first distance L1 may be greater than the second distance L2 in the layout structure of the semiconductor device (the two gate connection structures of the layout structure as shown in fig. 5 include a first gate connection structure 50a and a second gate connection structure 50 b). In some specific embodiments, the first distance L1 may be smaller than the second distance L2 (the two gate connection structures of the layout structure as shown in fig. 5 include a first gate connection structure 50c and a second gate connection structure 50 b).

In some embodiments, the first distance is greater than the second distance, the N third gates are located between a first portion of the first gate connection structure and a first portion of the second gate connection structure, and the remaining N third gates are located on one side of the second portion of the first gate connection structure or one side of the second portion of the second gate connection structure.

Illustratively, referring to FIG. 5,2N, the third gate 503 includes a first portion 503-1 and a second portion 503-2, each of the first portion 503-1 and the second portion 503-2 includes N third gates, where the first distance L1 is greater than the second distance L2, two gate connection structures of the layout structure 50 as shown in FIG. 5 include a first gate connection structure 50a and a second gate connection structure 50b, a first portion 503-1 of the 2N third gates 503 is disposed between the first portion 502-1 of the second gate of the first gate connection structure 50a and the first portion 502-3 of the second gate connection structure 50b, the second portion 503-2 of the 2N third gates 503 is disposed on a side of the second portion 502-2 of the second gate of the first gate connection structure 50a (a side remote from the second gate connection structure 50 b), and in other examples, the second portion 503-2 of the 2N third gates may also be disposed on a side of the second gate connection structure 50a (a side remote from the second portion 502-4 of the second gate connection structure).

In some embodiments, the first distance is less than the second distance, the N third gates are located between the second portion of the first gate connection structure and the second portion of the second gate connection structure, and the remaining N third gates are located on one side of the first portion of the first gate connection structure or one side of the first portion of the second gate connection structure.

Illustratively, referring to fig. 5, the two gate connection structures of the layout structure 50 include a first gate connection structure 50c and a second gate connection structure 50b, a first portion 503-1 of the 2N third gates 503 is disposed at one side of a first portion 502-3 of the second gate connection structure 50b (a side away from the first gate connection structure 50 c), and in other examples, a first portion 503-1 of the 2N third gates 503 may also be disposed at one side of a first portion 502-1 of the second gate of the first gate connection structure 50c (a side away from the second gate connection structure 50b, not shown in fig. 5), and a second portion 503-2 of the 2N third gates 503 is disposed between a second portion 502-2 of the second gate of the first gate connection structure 50c and a second portion 502-4 of the second gate connection structure 50 b. Therefore, the third grid can be shared between the two grid connection structures, and the purpose of reducing the area is achieved under the condition that the circuit structure of the semiconductor device is ensured to be complete.

In some embodiments, referring to fig. 5 and 6, the second gate 502 and the third gate 503 in the first gate connection structure 50a and the second gate connection structure 50b extend along the Y-axis direction, and the projection shapes of the second gate 502 and the third gate 503 on the plane where the first active region is located are in a shape of "one", in other words, in some embodiments, the projection shapes of the second gate and the third gate on the plane where the first active region is located each include a rectangle. Illustratively, referring to FIG. 5, the projected shapes of the second gate (502-1, 502-2, 502-3, 502-4) and the third gate (503-1 and 503-2) in the plane of the first active region each comprise a rectangle.

In other embodiments, referring to fig. 7, fig. 7 is a schematic layout structure of another semiconductor device provided in the embodiments of the present disclosure, in which the second gate 502 in the first gate connection structure 50a and the second gate connection structure 50b extend along the Y-axis direction, and the projection shape of the third gate 503 in the first gate connection structure 50a and the second gate connection structure 50b on the plane where the first active region is located is in a "C" shape or a mirror image of the "C" shape. The plane of the first active region is an XOY plane shown in the drawing. In this way, when the total area of the layout structure of the semiconductor device is fixed, the projection shape of the third gate 503 on the plane where the first active region is located is in a shape of a straight line, compared with the projection shape of the third gate 503 on the plane where the first active region is located, the projection shape of the third gate 503 on the plane where the first active region is located is in a shape of a C, which can increase the size of the second gate and/or the third gate in the Y-axis direction, and further increase the size of the second active region in the Y-axis direction, thereby increasing the size of the channel in the Y-axis direction, so as to improve the hot carrier effect, reduce the subthreshold leakage current Ioff and the gate-induced drain leakage current, and improve the reliability of the semiconductor device. In addition, due to the increase of the size of the channel in the Y-axis direction, the process of lightly doped drain regions (LDD, lightly Doped Drain) in the transistor can be omitted, the process operation steps are reduced, and the process cost is reduced.

In some embodiments, the first gate has a dimension along the first direction that is greater than a dimension along the first direction of the second gate, and the second gate has a dimension along the first direction that is equal to a dimension along the first direction of the third gate.

Illustratively, referring to fig. 6, the first gate has a dimension R1 along the Y-axis direction, the second gate has a dimension R2 along the Y-axis direction, and the third gate has a dimension R3 along the Y-axis direction, wherein R1> R2, and r2=r3. In some embodiments, r1=0.42 μm, r2=0.375 μm, r3=0.375 μm.

In other embodiments, the first gate has a dimension along the first direction that is greater than the second gate, and the second gate has a dimension along the first direction that is greater than the third gate and is equal to the third gate.

Illustratively, referring to fig. 7, the first gate has a dimension R4 along the Y-axis, the second gate has a dimension R5 along the Y-axis, and the third gate has a dimension R6 along the Y-axis, wherein R4> R5> R6. In some embodiments, r4=0.416 μm, r5=0.27 μm, r6=0.257 μm.

It should be understood that, in some embodiments, the dimensions of the second gate 502 and the third gate 503 in the first direction are significantly increased, for example, the dimension of the second gate in the Y-axis direction is increased from 0.27 μm to 0.375 μm, and the dimension of the third gate in the Y-axis direction is increased from 0.257 μm to 0.375 μm, compared to the layout structure in which the projection of the third gate 503 in the plane of the first active region is in the shape of "C" (see fig. 7, where R4> R5> R6) in the plane of the first active region (see fig. 5 and 6), where R1> R2, and R2=r3). The dimensions of the second gate along the Y-axis direction and the dimension of the third gate along the Y-axis direction are the same as the channel dimensions of the transistor, in other words, the projection shape of the third gate on the plane where the first active region is located is changed from a straight shape to a C shape, which can save the area of the semiconductor device, so that the dimensions of the second gate and/or the third gate along the first direction can be increased, the dimensions of the second active region 402 corresponding to the second gate and/or the third gate along the first direction can be further increased, the dimensions of the channel corresponding to the second gate and/or the third gate along the first direction can be further increased, the hot carrier effect can be further improved, the subthreshold leakage current and the gate-induced drain leakage current can be reduced, and the reliability of the semiconductor device can be improved.

In some embodiments, the first and second portions of the 2N second gates each comprise two second gates directly connected, the N third gates comprise two third gates spaced apart, and both ends of the two second gates directly connected are substantially flush with both ends of the two third gates spaced apart along the first direction.

For example, referring to fig. 5,N =2, the first gate connection structure 50a includes four second gates, wherein the second gate of the first portion 502-1 includes two second gates, the second gate of the second portion 502-2 includes two second gates, two second gates in each portion are directly connected, two third gates 503-1 corresponding to the second gate of the first portion 502-1 are disposed apart, that is, a gap exists between the two third gates, and the two third gates are not connected, where two ends of the two third gates 503-1 having the gap are substantially flush with two ends of the two second gates 502-1 directly connected in the Y-axis direction, as indicated by dotted lines B-B ", C-C". Similarly, the two third gates 503-2 corresponding to the second gates of the second portion 502-2 are also disposed at intervals, and two ends of the two third gates 503-2 having a gap are substantially flush with two ends of the two directly connected second gates 502-2 along the Y-axis direction, as indicated by dotted lines D-D ", E-E".

In some embodiments, the projection shapes of the first grid electrodes on the plane where the first active region is located all comprise a U shape or an inverted U shape, the 2N first grid electrodes in the layout structure of the semiconductor device comprise a third portion and a fourth portion, the third portion is N first grid electrodes close to the second grid electrodes, the fourth portion is N first grid electrodes far away from the second grid electrodes, and the projection shapes of the first grid electrodes in the third portion and the first grid electrodes in the fourth portion on the plane where the first active region is located are different.

Referring to fig. 5 and 8, fig. 8 is an enlarged schematic diagram of the first gate connection structure 50a in fig. 5 corresponding to 2N first gates, where n=2, where the 2N first gates include a third portion 501-1 and a fourth portion 501-2, the number of first gates in the third portion 501-1 and the fourth portion 501-2 may be the same, and N is a positive integer. The first gate electrode in the third portion 501-1 and the first gate electrode in the fourth portion 501-2 have different projection shapes on the plane where the first active region is located. For example, referring to fig. 8, the projection of the first gate in the third portion 501-1 on the plane of the first active region is in an inverted "U" shape, and the projection of the first gate in the fourth portion 501-2 on the plane of the first active region is in a "U" shape. In other examples, the projection of the first gate in the third portion 501-1 on the plane of the first active region may have a "U" shape, and the projection of the first gate in the fourth portion 501-2 on the plane of the first active region may have an inverted "U" shape.

In other embodiments, the projection shape of the first gate on the plane where the first active area is located may further include a "straight" shape, where the projection shape of the first gate in the third portion and the projection shape of the first gate in the fourth portion on the plane where the first active area is located may be the same.

In some embodiments, an edge of the first gate in the third portion along the second direction is substantially flush with an edge of the second gate in the first portion along the second direction, and an edge of the first gate in the fourth portion along the second direction is substantially flush with an edge of the second gate in the second portion along the second direction.

Referring to fig. 5 and 9, fig. 9 is an enlarged schematic view of the first gate connection structure 50a in fig. 5, and as can be seen from fig. 9, one side a1 of the first gate 501-1 in the X-axis direction in the third portion, and one side a2, a1 and a2 of the second gate 502-1 in the X-axis direction in the first portion are substantially flush. The first gate 501-2 in the fourth portion is along an edge a3 in the X-axis direction, and the second gate 502-2 in the second portion is along an edge a4 in the X-axis direction, a3 being substantially flush with a 4.

In some embodiments, the N third gates are a third distance from the respective N second gates of the first gate connection structure along the first direction, a fourth distance from the respective N second gates of the second gate connection structure along the first direction, a fifth distance from the remaining N third gates to the respective N second gates of the two gate connection structures adjacent to the gate connection structure along the first direction, the third distance being equal to the fourth distance, and the fourth distance being equal to the fifth distance.

Referring to fig. 5 and 6, one of the first partial third gates 503-1 is spaced apart from one of the first partial second gates 502-1 of the first gate connection structure 50a by a third distance S1 in the Y-axis direction, one of the first partial third gates 503-1 is spaced apart from one of the first partial second gates 502-1 of the second gate connection structure 50b by a fourth distance S2 in the Y-axis direction, one of the second partial third gates 503-2 is spaced apart from one of the second partial second gates 502-2 of the first gate connection structure 50a by a fifth distance S3 in the Y-axis direction, where third distance s1=fourth distance s2=fifth distance S3.

In view of the above, the layout structure of the semiconductor device provided in the embodiment of the disclosure includes a plurality of first active regions, two gate connection structures, and 2N third gates, where each gate connection structure includes 2N first gates and 2N second gates that are interconnected, where the N third gates are disposed between the two gate connection structures and correspond to the N second gates of the two gate connection structures, and the N remaining third gates are disposed on a side of one gate connection structure far from the other gate connection structure, and the remaining N third gates correspond to the N second gates remaining in an adjacent gate connection structure, so that the number of third gates in the layout structure of the semiconductor device is reduced, the area of the semiconductor device is reduced, and the integration of the device is improved.

The embodiment of the disclosure also provides an array structure of the semiconductor device, which comprises a plurality of layout structures of the semiconductor device as described in the above embodiment of the disclosure.

In some embodiments, the layout structures of the plurality of semiconductor devices are arranged along a first direction, and the layout structure of each of the layout structures of the plurality of semiconductor devices is identical in structural arrangement.

Fig. 10 shows a partial schematic view of an array structure of a semiconductor device in an embodiment of the present disclosure. Referring to fig. 10, the array structure 60 of semiconductor devices may include a plurality of (five are shown in fig. 10) layout structures 50 of semiconductor devices arranged in a Y-axis direction, each of the layout structures 50 of semiconductor devices including a first gate connection structure 50a and a second gate connection structure 50b arranged in the Y-axis direction, the arrangement of the first gate connection structure 50a and the second gate connection structure 50b and the third gate in each of the layout structures of semiconductor devices being identical, and here, the plurality of first gate connection structures 50a and the second gate connection structures 50b in the array structure 60 of semiconductor devices are arranged at intervals. Here, the arrangement is the same and it is understood that the positional relationship and the size between the first gate connection structure and the second gate connection structure and the third gate are the same, similarly to the case where the layout structure of one semiconductor device is duplicated, and the layout structures of the duplicated plurality of semiconductor devices are arranged in order along the first direction.

It should be noted that the layout structure of the semiconductor device may include various arrangements, for example, a first structure P1, a second structure P2, a third structure P3, and a fourth structure P4 as shown in fig. 10, where the first structure P1 and the second structure P2 are mirror symmetry, and the third structure P3 and the fourth structure P4 are mirror symmetry. The layout structure of each of the plurality of semiconductor devices is identical in structural arrangement, and it is understood that the array structure of the semiconductor device includes a plurality of first structures P1 arranged along the first direction, a plurality of second structures P2 arranged along the first direction, a plurality of third structures P3 arranged along the first direction, or a plurality of fourth structures P4 arranged along the first direction.

In some embodiments, both ends of the layout structure of the plurality of semiconductor devices are substantially flush along the first direction. Illustratively, referring to FIG. 10, both ends of the layout structure 50 of the three semiconductor devices are substantially flush in the Y-axis direction, referenced by dashed lines F-F ", G-G".

The embodiment of the disclosure also provides a layout structure of an integrated circuit, which comprises one or more array structures of the semiconductor devices as described in the above embodiment of the disclosure, and a plurality of sub word lines, wherein each sub word line is connected with an active area corresponding to a first grid electrode and an active area corresponding to a second grid electrode in one grid electrode connection structure through a first via hole.

Illustratively, referring to fig. 11, the layout structure of the integrated circuit includes an array structure of one semiconductor device and a plurality of sub-word lines SWL, each of which is correspondingly connected to one first gate 501 and one second gate 502 in one gate connection structure (50 a or 50 b) through a first via 601. Here, each first gate connection structure 50a or each second gate connection structure 50b includes four first gates and four second gates, and based thereon, each first gate connection structure 50a or each second gate connection structure 50b may be connected to four sub-word lines through the first via 601, respectively. In other words, the layout structure 1100 of the integrated circuit includes eight sub-word lines (e.g., SWL-1, SWL-2, SWL-3, SWL-4, SWL-5, SWL-6, SWL-7, SWL-8), each sub-word line is connected to two first vias 601, and is connected to one first gate 501 and one second gate 502 in one gate connection structure through the two first vias 601.

In some embodiments, the layout structure of the integrated circuit further comprises a plurality of main word lines, wherein each main word line is connected with all first gates and all second gates in one gate connection structure through a second via hole. Illustratively, referring to fig. 11, one main word line is connected to one gate connection structure, i.e., one main word line is connected to four first gates and four second gates in each first gate connection structure 50a or each second gate connection structure 50b through a second via (not shown in fig. 11). In other words, each main word line may include four sub word lines (e.g., SWL-1, SWL-2, SWL-3, SWL-4).

In some embodiments, the integrated circuit is a dynamic random access memory.

In addition, the sub-word line driver formed by the layout structure of the semiconductor device in the above embodiment of the disclosure has reduced subthreshold leakage current and gate-induced drain leakage current under different operating conditions.

The scope of the present disclosure is not limited thereto, and any person skilled in the art, who is skilled in the art, can easily conceive of variations or substitutions within the technical scope of the present disclosure, should be covered in the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A layout structure of a semiconductor device, comprising:

a plurality of first active regions each extending along a first direction;

And 2N third grids, wherein the N third grids are positioned between the two grid connection structures adjacent along the first direction and correspond to N second grids of the two grid connection structures, devices corresponding to the N third grids are respectively and electrically connected with devices corresponding to the N second grids of the two adjacent grid connection structures, the rest N third grids are positioned at one side of one grid connection structure far away from the other grid connection structure and correspond to the rest N second grids of the one grid connection structure, the second grids and the third grids extend along the second direction, and the second direction is perpendicular to the first direction.

2. The layout structure of a semiconductor device according to claim 1, wherein 2N first gates of each of the gate connection structures are physically connected;

3. The layout structure of a semiconductor device according to claim 2, wherein the two gate connection structures include a first gate connection structure and a second gate connection structure;

4. The layout structure of a semiconductor device according to claim 3, wherein the first distance is larger than the second distance;

5. The layout structure of a semiconductor device according to claim 3, wherein the first distance is smaller than the second distance;

6. The layout structure of a semiconductor device according to claim 3, wherein the first and second portions of the 2N second gates each include two directly connected second gates, the N third gates include two spaced apart third gates, and both ends of the directly connected second gates are substantially flush with both ends of the spaced apart third gates along the first direction.

7. The layout structure of a semiconductor device according to claim 3, wherein the projection shapes of the first gates on the plane where the first active region is located include a U shape or an inverted U shape, the 2N first gates include a third portion and a fourth portion, the third portion is N first gates close to the second gate, the fourth portion is N first gates far away from the second gate, and the projection shapes of the first gates in the third portion and the first gates in the fourth portion on the plane where the first active region is located are different.

8. The layout structure of a semiconductor device according to claim 7, wherein a projection shape of the second gate and the third gate on a plane where the first active region is located each comprises a rectangle.

9. The layout structure of claim 8 wherein an edge of the first gate in the third portion along the second direction is substantially flush with an edge of the second gate in the first portion along the second direction, and wherein an edge of the first gate in the fourth portion along the second direction is substantially flush with an edge of the second gate in the second direction.

10. The layout structure of a semiconductor device according to claim 1, wherein a distance between the N third gates and the corresponding N second gates of the first gate connection structure in the first direction is a third distance and a distance between the N third gates and the corresponding N second gates of the second gate connection structure in the first direction is a fourth distance;

11. The layout structure of a semiconductor device according to claim 1, wherein a size of the first gate electrode in the first direction is larger than a size of the second gate electrode in the first direction;

12. The layout structure of a semiconductor device according to claim 1, wherein 2N first gates in the two gate connection structures are each parallel and both ends are substantially flush along the first direction;

13. The layout structure of a semiconductor device according to claim 1, wherein the transistors corresponding to the first gate comprise PMOS transistors, and wherein the transistors corresponding to the second gate and the transistors corresponding to the third gate comprise NMOS transistors.

14. The layout structure of a semiconductor device according to claim 1, further comprising a plurality of second active regions, wherein the plurality of second active regions correspond to the second gate and the third gate.

15. An array structure of a semiconductor device according to any one of claims 1 to 14, characterized by comprising a plurality of layout structures of the semiconductor device.

16. The array structure of semiconductor devices according to claim 15, wherein the layout structures of a plurality of the semiconductor devices are arranged in the first direction, and the layout structure of each of the layout structures of the plurality of semiconductor devices is identical in structural arrangement.

17. The array structure of semiconductor devices according to claim 16, wherein both ends of the layout structure of a plurality of the semiconductor devices are substantially flush along the first direction.

18. A layout structure of an integrated circuit comprising an array structure of one or more semiconductor devices as claimed in any one of claims 15 to 17, and

19. The integrated circuit layout structure of claim 18 further comprising a plurality of main word lines, each of said main word lines being connected to all of the first gates and all of the second gates in one of said gate connection structures by second vias.

20. The integrated circuit layout structure of claim 18 wherein the integrated circuit is a dynamic random access memory.