CN118866966A - Lateral high voltage MOS device and doping method for optimizing body diode performance - Google Patents

Abstract

The invention provides a transverse high-voltage MOS device for optimizing the performance of a body diode and a doping method, and belongs to the technical field of power semiconductor devices. The method performs local lifetime control for the drift region or body region of a lateral metal oxide semiconductor device to optimize the reverse recovery characteristics of its body diode. Under the trend of increasingly shrinking power devices, the loss caused by the performance of the body diode is more and more paid attention to, the forward characteristic and breakdown characteristic of the device are often deteriorated when the reverse recovery charge of the body diode is reduced through overall life control.

Description

Lateral high voltage MOS device and doping method for optimizing body diode performance

Technical Field

The invention belongs to the technical field of power semiconductors and relates to a lateral high-voltage MOS device for optimizing body diode performance and a doping method.

Background Art

As the core component of the electronic system, the power module is like the heart, which is an indispensable part of the human body. Wherever electricity is used, there will be a power management chip. BUCK type DC-DC converter occupies an important position in the switching power supply with its unique step-down advantages and performance advantages. With the rapid development of various communication equipment, digital signal processors, base stations, microprocessors and portable electronic products, people have put forward higher requirements for power management chips. In addition to optimizing the trade-off relationship between breakdown voltage and specific on-resistance, the quality of the reverse recovery characteristics of the device is also very critical to the power loss of the entire chip, and is one of the important factors to meet the requirements of high efficiency and low cost applications. In order to obtain excellent reverse recovery performance of the device, people have developed technologies that can accurately control the carrier lifetime in materials and device processes. Discrete power devices often use Au, Pt diffusion and electron irradiation to increase the switching speed of the device, but they are difficult to achieve local lifetime control and are incompatible with large-scale integrated circuit processes. For BCD process integrated circuits known for their low power consumption, how to introduce local lifetime control at specific locations of specific devices to reduce the carrier lifetime and thus optimize the reverse recovery characteristics of the device body diode, and ultimately reduce the power loss of the entire circuit is an issue that the industry currently needs to focus on and pursue in research.

Summary of the invention

In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a lateral high-voltage MOS device with optimized body diode performance.

To achieve the above-mentioned purpose of the invention, the technical solution of the present invention is as follows:

A lateral high-voltage MOS device comprises a first conductive type substrate 107, a second conductive type drift region 104 located above the first conductive type substrate 107, a first conductive type body region 106 is provided in the second conductive type drift region 104, a first conductive type body contact region 105 and a second conductive type heavily doped source region 101 are provided in the first conductive type body region 106, the second conductive type heavily doped source region 101 is located outside the first conductive type body contact region 105, the first conductive type body contact region 105 and the second conductive type heavily doped source region 101 are both connected to a source metal 108, a second conductive type heavily doped drain region 103 is provided in the second conductive type drift region 104, gate oxide and gate polysilicon 102 are provided above the second conductive type drift region 104, and a dielectric layer 110 is filled between the source metal 108, the drain metal 109 and the gate polysilicon 102.

As a preferred method, a local low lifetime zone 111 is provided in the second conductive type drift region 104 near the side of the first conductive type body region 106; the implementation process of the local low lifetime zone 111 is: after the second conductive type drift region 104 and the first conductive type body region 106 of the device are formed, silicon dioxide and silicon nitride are used as blocking layers during ion implantation, and the ion implantation window is limited to the second conductive type drift region 104 near the side of the first conductive type body region 106, and through multiple injections of different energies, a local low lifetime zone 111 is formed in the second conductive type drift region 104 near the side of the first conductive type body region 106 after annealing.

As a preferred method, a local low lifetime zone 111 is provided on the side of the first conductive type body region 106 near the second conductive type drift region 104, and the implementation process of the local low lifetime zone 111 is as follows: after the second conductive type drift region 104 and the first conductive type body region 106 of the device are formed, silicon dioxide and silicon nitride are used as blocking layers during ion implantation, and the ion implantation window is limited to the side of the first conductive type body region 106 near the second conductive type drift region 104, and through multiple injections of different energies, a local low lifetime zone will be formed on the side of the first conductive type body region 106 near the second conductive type drift region 104 after annealing.

As a preferred embodiment, a local low lifetime zone 111 is provided in the second conductive type drift region 104 below the first conductive type body region 106. The implementation process of the local low lifetime zone 111 is as follows: after the second conductive type drift region 104 and the first conductive type body region 106 of the device are formed, silicon dioxide and silicon nitride are used as barrier layers during ion implantation to limit the ion implantation window within the first conductive type body region 106. By adjusting the implantation energy, the depth of the helium ion implantation is controlled in the second conductive type drift region 104 below the first conductive type body region 106.

As a preferred method, a local low lifetime zone 111 is provided at the bottom of the first conductive type body region 106. The implementation process of the local low lifetime zone 111 is as follows: after the second conductive type drift region 104 and the first conductive type body region 106 of the device are formed, silicon dioxide and silicon nitride are used as barrier layers during ion implantation to limit the ion implantation window to the first conductive type body region 106. By adjusting the implantation energy, the depth of the helium ion implantation is controlled at the bottom of the first conductive type body region 106.

The present invention also provides a second lateral high-voltage MOS device for optimizing body diode performance, comprising a first conductive type substrate 201, a second conductive type buried layer 202 is arranged on the first conductive type substrate 201, a second conductive type drift region 203 and a second conductive type connection region 205 are arranged above the second conductive type buried layer 202; a second conductive type heavily doped drain region 207 is arranged above the second conductive type connection region 205; a first conductive type body region 204 and a gate polysilicon 209 are arranged above the second conductive type drift region 203, and the gate polysilicon 209 is provided with a first conductive type body region 204 and a gate polysilicon 209. The silicon 209 and the second conductive type drift region 203 are separated by an insulating dielectric layer 208; a gate oxide layer is provided between the gate polysilicon 209 and the first conductive type body region 204; a second conductive type heavily doped source region 206 and a first conductive type body contact region are provided above the first conductive type body region 204, and the two are alternately distributed in a direction perpendicular to the paper surface; an active region electrode metal 210 is provided above the second conductive type heavily doped source region 206 and the first conductive type body contact region, and a drain region electrode metal 211 is provided above the second conductive type heavily doped drain region 207;

The local low lifetime region 212 is disposed in the second conductive type drift region 203 below the first conductive type body region 204 or at the bottom of the first conductive type body region 204;

The implementation process of the local low lifetime region 212 disposed in the second conductive type drift region 203 below the first conductive type body region 204 is as follows: after the second conductive type drift region 203 and the first conductive type body region 204 of the device are formed, silicon dioxide and silicon nitride are used as barrier layers during ion implantation to limit the ion implantation window within the first conductive type body region 204, and the depth of helium ion implantation is controlled within the second conductive type drift region 203 below the first conductive type body region 204 by adjusting the implantation energy;

The implementation process of the local low lifetime zone 212 set at the bottom of the first conductive type body region 204 is: after the second conductive type drift region 203 and the first conductive type body region 204 of the device are formed, silicon dioxide and silicon nitride are used as barrier layers during ion implantation to limit the ion implantation window to the first conductive type body region 204, and the depth of helium ion implantation is controlled at the bottom of the first conductive type body region 204 by adjusting the implantation energy.

The present invention also provides a method for realizing local platinum doping in a lateral high-voltage MOS device that optimizes body diode performance. Before performing local lifetime control helium ion implantation on the device, platinum is first sputtered onto the surface of a silicon wafer, and a platinum silicon layer is formed through high-temperature sintering annealing at 400 to 460°C. After helium ion implantation forms induced defects in specific areas, these defects absorb platinum on the surface of the silicon wafer during high-temperature thermal annealing at 800 to 1050°C. The distribution of these platinums is similar to the defect distribution formed by helium ion implantation, thereby realizing local platinum doping.

As a preferred embodiment, the helium ions mentioned in the above local lifetime control can be replaced by hydrogen ions or other irradiated particles that meet the requirements.

The beneficial effects of the present invention are:

The present invention realizes local lifetime control in a lateral high-voltage device as a switching device, and optimizes the reverse recovery characteristics of the device body diode by reducing the minority carrier lifetime in a specific area of the device on the basis of ensuring a good compromise relationship between the forward and reverse characteristics of the device and lower leakage, thereby achieving the purpose of reducing the overall switching loss of the device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of a lateral planar gate MOS device structure in the prior art;

FIG2 is a schematic diagram of the structure of a lateral planar gate MOS device for optimizing body diode performance according to Embodiment 1 of the present invention;

3 is a schematic diagram of the structure of a lateral planar gate MOS device for optimizing body diode performance according to Embodiment 2 of the present invention;

FIG4 is a schematic diagram of the structure of a lateral planar gate MOS device for optimizing body diode performance according to Embodiment 3 of the present invention;

FIG5 is a schematic diagram of the structure of a lateral planar gate MOS device for optimizing body diode performance according to Embodiment 4 of the present invention;

6 is a schematic diagram of the structure of a lateral trench gate MOS device for optimizing body diode performance according to Embodiment 5 of the present invention;

7 is a schematic diagram of the structure of a lateral trench gate MOS device for optimizing body diode performance according to Embodiment 6 of the present invention;

8 is a flow chart of the local lifetime control of a lateral planar gate MOS device for optimizing body diode performance according to Embodiment 1 provided by the present invention;

9A to 9H are schematic diagrams of a process flow for implementing local lifetime control of a lateral planar gate MOS device for optimizing body diode performance as described in Example 1 of the present invention.

Among them, 101 is a second conductivity type heavily doped source region, 102 is gate polysilicon, 103 is a second conductivity type heavily doped drain region, 104 is a second conductivity type drift region, 105 is a first conductivity type body contact region, 106 is a first conductivity type body region, 107 is a first conductivity type substrate, 108 is a source metal, 109 is a drain metal, 110 is a dielectric layer, and 111 is a local low lifetime region.

201 is a first conductivity type substrate, 202 is a second conductivity type buried layer, 203 is a second conductivity type drift region, 204 is a first conductivity type body region, 205 is a second conductivity type connection region, 206 is a second conductivity type heavily doped source region, 207 is a second conductivity type heavily doped drain region, 208 is an insulating dielectric layer, 209 is a gate polysilicon, 210 is a source region electrode metal, 211 is a drain region electrode metal, and 212 is a local low lifetime region.

DETAILED DESCRIPTION

The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

In the following embodiments, the ions implanted for lifetime control may be helium ions, hydrogen ions, or other particles that meet the requirements.

The material of the oxide layer may be a gate oxide layer or a high dielectric constant material.

The gate electrode can be metal or polysilicon.

The first conductivity type is P-type doping and the second conductivity type is N-type doping; or the first conductivity type is N-type doping and the second conductivity type is P-type doping. The following embodiments are described based on the assumption that the first conductivity type is P-type doping and the second conductivity type is N-type doping.

As shown in FIG1 , a conventional lateral planar gate high voltage MOS device structure is shown. The structure is implemented on a first conductive type substrate 107, and includes a first conductive type substrate 107, a second conductive type drift region 104 located above the first conductive type substrate 107, a first conductive type body region 106 is provided in the second conductive type drift region 104, a first conductive type body contact region 105 and a second conductive type heavily doped source region 101 are provided in the first conductive type body region 106, the second conductive type heavily doped source region 101 is located outside the first conductive type body contact region 105, the first conductive type body contact region 105 and the second conductive type heavily doped source region 101 are both connected to a source metal 108, a second conductive type heavily doped drain region 103 is provided in the second conductive type drift region 104, a gate oxide and a gate polysilicon 102 are provided above the second conductive type drift region 104, and a dielectric layer 110 is filled between the source metal 108, the drain metal 109 and the gate polysilicon 102.

Embodiment 1:

As shown in FIG. 2 , this embodiment proposes a lateral high-voltage MOS device that optimizes body diode performance. The difference from FIG. 1 is that a local low lifetime region 111 is provided in the second conductive type drift region 104 close to the side of the first conductive type body region 106 .

With respect to the proposed device structure, the implementation process is as follows: first prepare a substrate 107, and start local lifetime controlled ion implantation after forming a second conductivity type drift region 104 and a first conductivity type body region 106. Use silicon dioxide and silicon nitride as barrier layers during ion implantation, limit the ion implantation window to the second conductivity type drift region 104 near the side of the first conductivity type body region 106, and through multiple implantations of different energies, after annealing, form a local low lifetime region 111 in the second conductivity type drift region 104 near the side of the first conductivity type body region 106. Grow gate oxide, etch gate polysilicon 102, perform second conductivity type self-aligned implantation to form a second conductivity type source region 101, perform first conductivity type ion implantation to form a heavily doped first conductivity type body contact region 105, perform second conductivity type ion implantation to form a heavily doped second conductivity type drain region 103, deposit a dielectric layer 110, and punch and fill source metal 108 and drain metal 109;

The working principle of this example is as follows: this embodiment introduces a local low lifetime region in the second conductive type drift region close to the side of the first conductive type body region, shortening the minority carrier lifetime in this region, accelerating the carrier extraction speed, and optimizing the reverse recovery characteristics of the device body diode.

Embodiment 2:

As shown in FIG3 , the difference between this embodiment and embodiment 1 is that:

The localized low lifetime region 111 is located at a side of the first conductivity type body region 106 close to the second conductivity type drift region 104 .

The implementation process of the local low lifetime zone 111 is as follows: after the second conductive type drift region 104 and the first conductive type body region 106 of the device are formed, silicon dioxide and silicon nitride are used as blocking layers during ion implantation, and the ion implantation window is limited to the side of the first conductive type body region 106 close to the second conductive type drift region 104. Through multiple injections of different energies, a local low lifetime zone will be formed on the side of the first conductive type body region 106 close to the second conductive type drift region 104 after annealing.

The working principle of this example is similar to that of Example 1, but since the introduction of the lifetime control region in this example will not change the minority carrier distribution in the drift region, the impact on the forward characteristics and leakage current of the device is relatively small.

Embodiment 3:

As shown in Figure 4, the difference between this embodiment and Embodiment 1 is that a local low lifetime region 111 is provided in the second conductive type drift region 104 below the first conductive type body region 106, and the implementation process of the local low lifetime region 111 is as follows: after the second conductive type drift region 104 and the first conductive type body region 106 of the device are formed, silicon dioxide and silicon nitride are used as barrier layers during ion implantation, and the ion implantation window is limited to the first conductive type body region 106, and by adjusting the implantation energy, the depth of the helium ion implantation is controlled in the second conductive type drift region 104 below the first conductive type body region 106.

Since the formed low lifetime region is thin in the depth direction, multiple implantations are not required.

The working principle of this example is the same as that of Example 1, but the current mainly flows horizontally when the device is working, so the effect of the low lifetime region on improving the reverse characteristics of the body diode is relatively weak.

Embodiment 4:

As shown in FIG5 , the difference between this embodiment and embodiment 1 is that:

A local low lifetime zone 111 is provided at the bottom of the first conductive type body region 106. The implementation process of the local low lifetime zone 111 is as follows: after the second conductive type drift region 104 and the first conductive type body region 106 of the device are formed, silicon dioxide and silicon nitride are used as barrier layers during ion implantation to limit the ion implantation window within the first conductive type body region 106. By adjusting the implantation energy, the depth of the helium ion implantation is controlled at the bottom of the first conductive type body region 106.

The principle of this embodiment is similar to that of the first embodiment, but the current mainly flows in the transverse direction when the device is working, so the effect of the low lifetime region on improving the reverse characteristics of the body diode is relatively weak.

Embodiment 5:

As shown in FIG6 , the difference between this embodiment and embodiment 1 is that:

In this embodiment, the planar gate structure is replaced by a trench gate structure.

The present invention comprises a first conductive type substrate 201, a second conductive type buried layer 202 is arranged on the first conductive type substrate 201, a second conductive type drift region 203 and a second conductive type connection region 205 are arranged above the second conductive type buried layer 202; a second conductive type heavily doped drain region 207 is arranged above the second conductive type connection region 205; a first conductive type body region 204 and a gate polysilicon 209 are arranged above the second conductive type drift region 203, and the gate polysilicon 209 and the second conductive type drift region 203 are arranged above the second conductive type drift region 203. 203 are separated by an insulating dielectric layer 208; a gate oxide layer is arranged between the gate polysilicon 209 and the first conductive type body region 204; a second conductive type heavily doped source region 206 and a first conductive type body contact region are arranged above the first conductive type body region 204, and the two are alternately distributed in the vertical direction of the paper; an active region electrode metal 210 is arranged above the second conductive type heavily doped source region 206 and the first conductive type body contact region, and a drain region electrode metal 211 is arranged above the second conductive type heavily doped drain region 207;

The local low lifetime region 212 is disposed near the second conductivity type drift region 203 below the first conductivity type body region 204 .

The implementation process of the local low lifetime zone 212 arranged in the second conductive type drift region 203 near the bottom of the first conductive type body region 204 is as follows: after the second conductive type drift region 203 and the first conductive type body region 204 of the device are formed, silicon dioxide and silicon nitride are used as barrier layers during ion implantation to limit the ion implantation window within the first conductive type body region 204, and by adjusting the implantation energy, the depth of the helium ion implantation is controlled in the second conductive type drift region 203 below the first conductive type body region 204.

This embodiment introduces a local low lifetime region into the lateral trench gate structure, combines the advantages of trench gate devices, and speeds up the switching speed of the device.

Embodiment 6:

As shown in FIG7 , the difference between this embodiment and embodiment 5 is that:

The localized low lifetime region 212 is located at the bottom of the first conductivity type body region 204 .

The implementation process of the local low lifetime zone 212 set at the bottom of the first conductive type body region 204 is: after the second conductive type drift region 203 and the first conductive type body region 204 of the device are formed, silicon dioxide and silicon nitride are used as barrier layers during ion implantation to limit the ion implantation window to the first conductive type body region 204, and the depth of helium ion implantation is controlled at the bottom of the first conductive type body region 204 by adjusting the implantation energy.

Embodiment 7:

This embodiment provides a method for realizing local lifetime control of lateral high-voltage MOS devices, as shown in Figure 8, wherein the key steps are helium ion implantation and high-temperature thermal annealing after P-well implantation. The implementation process is _as follows: _SiO2 and _Si3N4 are selected as barrier layers when implanting ions, low-energy and high-dose helium ions are used, and short high-temperature annealing is performed under _N2 after implantation, thereby forming a local low lifetime region in the area specified by the mask and in the depth range limited by energy.

The principle of realizing local lifetime control in the present invention is: the solid solubility of inert gas in silicon is extremely low. When the concentration of inert gas injected into silicon exceeds a certain value, bubbles will be formed. Different ion injection energies can be used to control the bubbles within a certain range at different depths from the silicon surface, and the concentration is determined by the dose of ion injection. The atomic model shows that helium ions can easily form many He lattice void pairs in silicon, that is, point defects. These high-concentration point defects and helium atoms produce a large number of trap centers, which become the cores for forming bubbles. The He in the bubble is very unstable. During the heat treatment process at 300 to 700°C, it will leave the bubble and diffuse in the silicon crystal, and finally evaporate from the silicon surface. When He completely evaporates, a fairly stable void will be formed in the silicon crystal. While introducing traps into the void, electrons and trap energy levels are also introduced. Each trap energy level is near the center of the band gap. These deep energy levels, as recombination centers, will reduce the lifetime of minority carriers, thereby accelerating the extraction of minority carriers, so that the effect of local lifetime control can be achieved.

Specifically, the method described in Embodiment 1 of the present invention realizes the local lifetime control of the lateral high-voltage MOS device of the present invention. As shown in FIGS. 9A-9H , the main process steps and process parameters in the process of manufacturing are as follows:

Step a: preparing a substrate: selecting a P-type silicon single crystal wafer with a resistivity of 8-12Ω·cm and a crystal orientation of <100> with a relatively small defect density as the first conductive type substrate 107, as shown in FIG. 9A.

Step b: Drift region formation: Using a chemical vapor deposition (CVD) method at 1100-1150° C., an N-type lightly doped epitaxial layer is grown on the first conductive type substrate 107 at a rate of 0.3-0.5 μm/min to form a second conductive type drift region 104, as shown in FIG. 9B .

Step c: P-well implantation: includes three steps to form the first conductivity type body region 106. The first step is to implant boron ions, which are implanted deeply and have high energy, and are used to adjust the depth of the well and reduce the resistance of the well. The second step is to implant boron ions, which are implanted shallowly and have low energy, and are used as channel concentration adjustment to prevent source-drain penetration leakage. The third step is to implant _BF2 ions, which are implanted on the surface and have very low energy, and are used to adjust the threshold voltage, as shown in FIG9C .

Step d: Helium ion implantation: SiO ₂ and Si ₃ N ₄ are selected as barrier layers for ion implantation, and the ion implantation window is limited to the second conductivity type drift region 104 close to the side of the first conductivity type body region 106 . The helium ion dose is 5×10 ¹⁶ , and multiple implantations with different energies are performed, as shown in FIG. 9D .

Step e: high temperature thermal annealing: annealing at 1050°C under _N2 for 30 min to form a stable local low lifetime region 111, as shown in FIG9E.

Step f: Deposit gate oxide and etch polysilicon: A thin gate oxide layer is grown by thermally growing a furnace tube, and a layer of polysilicon is deposited by LPCVD to form gate polysilicon 102, as shown in FIG. 9F .

Step g: source and drain heavy doping and body region injection: self-aligned high-energy ion injection is performed to form a heavily doped second conductivity type heavily doped source region 101, and high-energy ion injection is performed to form a heavily doped first conductivity type body contact region 105 and a second conductivity type heavily doped drain region 103, as shown in FIG. 9G .

Step h: CT etching and filling: ILD deposition forms an interlayer dielectric layer 110, CT lithography and etching form through holes, and metal CVD is used to deposit source metal 108 and drain metal 109, as shown in FIG9H .

The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims (7)

1. A lateral high-voltage MOS device, characterized in that: it comprises a first conductive type substrate (107), a second conductive type drift region (104) located above the first conductive type substrate (107), a first conductive type body region (106) is provided in the second conductive type drift region (104), a first conductive type body contact region (105) and a second conductive type heavily doped source region (101) are provided in the first conductive type body region (106), the second conductive type heavily doped source region (101) is located above the first conductive type substrate (107), and the first conductive type body contact region (105) and the second conductive type heavily doped source region (101) are provided in the first conductive type body region (106). The first conductive type body contact region (105) and the second conductive type heavily doped source region (101) are both connected to a source metal (108), a second conductive type heavily doped drain region (103) is provided in the second conductive type drift region (104), a gate oxide and a gate polysilicon (102) are provided above the second conductive type drift region (104), and a dielectric layer (110) is filled between the source metal (108), the drain metal (109) and the gate polysilicon (102). 2. The lateral high-voltage MOS device with optimized body diode performance according to claim 1 is characterized in that: a local low lifetime region (111) is provided in the second conductive type drift region (104) close to the side of the first conductive type body region (106); the implementation process of the local low lifetime region (111) is as follows: after the second conductive type drift region (104) and the first conductive type body region (106) of the device are formed, silicon dioxide and silicon nitride are used as barrier layers during ion implantation, and the ion implantation window is limited to the second conductive type drift region (104) close to the side of the first conductive type body region (106); by multiple injections of different energies, a local low lifetime region (111) is formed in the second conductive type drift region (104) close to the side of the first conductive type body region (106) after annealing. 3. The lateral high-voltage MOS device with optimized body diode performance according to claim 1 is characterized in that: a local low lifetime region (111) is provided on the side of the first conductive type body region (106) close to the second conductive type drift region (104), and the implementation process of the local low lifetime region (111) is as follows: after the second conductive type drift region (104) and the first conductive type body region (106) of the device are formed, silicon dioxide and silicon nitride are used as blocking layers during ion implantation, and the ion implantation window is limited to the side of the first conductive type body region (106) close to the second conductive type drift region (104), and through multiple injections of different energies, a local low lifetime region is formed on the side of the first conductive type body region (106) close to the second conductive type drift region (104) after annealing. 4. The lateral high-voltage MOS device with optimized body diode performance according to claim 1 is characterized in that: a local low lifetime region (111) is provided in the second conductive type drift region (104) below the first conductive type body region (106), and the implementation process of the local low lifetime region (111) is as follows: after the second conductive type drift region (104) and the first conductive type body region (106) of the device are formed, silicon dioxide and silicon nitride are used as barrier layers during ion implantation, and the ion implantation window is limited to the first conductive type body region (106), and by adjusting the implantation energy, the depth of helium ion implantation is controlled to the second conductive type drift region (104) below the first conductive type body region (106). 5. The lateral high-voltage MOS device with optimized body diode performance according to claim 1 is characterized in that: a local low lifetime region (111) is provided at the bottom of the first conductive type body region (106), and the implementation process of the local low lifetime region (111) is as follows: after the second conductive type drift region (104) and the first conductive type body region (106) of the device are formed, silicon dioxide and silicon nitride are used as barrier layers during ion implantation, and the ion implantation window is limited to the first conductive type body region (106), and the depth of helium ion implantation is controlled at the bottom of the first conductive type body region (106) by adjusting the implantation energy. 6. A lateral high-voltage MOS device for optimizing body diode performance, characterized in that: it comprises a first conductive type substrate (201), a second conductive type buried layer (202) is arranged on the first conductive type substrate (201), a second conductive type drift region (203) and a second conductive type connection region (205) are arranged above the second conductive type buried layer (202); a second conductive type heavily doped drain region (207) is arranged above the second conductive type connection region (205); a first conductive type body region (204) and gate polysilicon (209) are arranged above the second conductive type drift region (203), and the gate polysilicon (209) is provided The silicon (209) and the second conductive type drift region (203) are separated by an insulating dielectric layer (208); a gate oxide layer is provided between the gate polysilicon (209) and the first conductive type body region (204); a second conductive type heavily doped source region (206) and a first conductive type body contact region are provided above the first conductive type body region (204), and the two are alternately distributed in a direction perpendicular to the paper surface; an active region electrode metal (210) is provided above the second conductive type heavily doped source region (206) and the first conductive type body contact region, and a drain region electrode metal (211) is provided above the second conductive type heavily doped drain region (207); The local low lifetime region (212) is arranged in the second conductive type drift region (203) below the first conductive type body region (204), or is arranged at the bottom of the first conductive type body region (204); The implementation process of the local low lifetime region (212) arranged in the second conductive type drift region (203) below the first conductive type body region (204) is as follows: after the second conductive type drift region (203) and the first conductive type body region (204) of the device are formed, silicon dioxide and silicon nitride are used as barrier layers during ion implantation to limit the ion implantation window within the first conductive type body region (204), and the implantation energy is adjusted to control the depth of the helium ion implantation to the second conductive type drift region (203) below the first conductive type body region (204); The implementation process of the local low lifetime region (212) arranged at the bottom of the first conductive type body region (204) is as follows: after the second conductive type drift region (203) and the first conductive type body region (204) of the device are formed, silicon dioxide and silicon nitride are used as barrier layers during ion implantation, the ion implantation window is limited within the first conductive type body region (204), and the depth of helium ion implantation is controlled at the bottom of the first conductive type body region (204) by adjusting the implantation energy. 7. A method for local platinum doping of a lateral high-voltage MOS device with optimized body diode performance according to any one of claims 2 to 6, characterized in that: before performing local lifetime control helium ion implantation on the device, platinum is first sputtered onto the surface of a silicon wafer, and a platinum silicon layer is formed after high-temperature sintering annealing at 400-460°C. After helium ion implantation forms induced defects in specific areas, these defects will absorb platinum on the surface of the silicon wafer during high-temperature thermal annealing at 800-1050°C. The distribution of these platinums is similar to the defect distribution formed by helium ion implantation, thereby achieving local platinum doping.