CN118866043A - Data writing circuit, memory and data writing method - Google Patents

Abstract

The present invention relates to a data writing circuit, a memory and a data writing method. The data writing circuit comprises: a multi-level driving module, each level of driving module is used to connect a plurality of storage arrays of a corresponding level and a driving module of a next level, and is used to drive the data to be written to be transmitted to the data path corresponding to the plurality of storage arrays of a corresponding level and/or the driving module of the next level; a control module, connected to each level of driving module, is used to send a driving control signal to the driving module of the corresponding level of the target storage array to be written and/or the driving module of the next level according to the writing control signal of each storage array, and the driving control signal is used to adjust the driving ability of the driving module; wherein the data paths corresponding to different storage arrays are used to receive different writing control signals, and the writing control signal is used to connect the data path and the corresponding storage array. The present invention can reduce the difficulty of time matching.

Description

Data writing circuit, memory and data writing method

Technical Field

The present invention relates to the technical field of integrated circuits, and in particular to a data writing circuit, a memory and a data writing method.

Background Art

Dynamic Random Access Memory (DRAM) is a semiconductor memory that uses the amount of charge stored in a capacitor to represent whether a binary bit is 1 or 0.

DRAM is usually arranged in a two-dimensional matrix with a capacitor and a transistor as a unit. The basic operation mechanism is divided into read and write. In traditional technology, multiple storage arrays are arranged in multiple levels, and each level has a driver module. When writing data, the driver module drives the data according to the write control signal of different storage arrays to achieve accurate data writing.

However, as the capacity of DRAM increases and the number of storage arrays continues to increase, timing matching of write control signals becomes increasingly difficult.

Summary of the invention

Based on this, it is necessary to provide a data writing circuit, a memory and a data writing method that can reduce the difficulty of time matching.

In a first aspect, a data writing circuit is provided, comprising:

A multi-level driving module, wherein each level of the driving module is used to connect the multiple storage arrays of the corresponding level and the driving module of the next level, and is used to drive the data to be written to be transmitted to the data path corresponding to the multiple storage arrays of the corresponding level and/or the driving module of the next level;

a control module connected to each level of the driving modules, and configured to send a driving control signal to the driving module of the corresponding level of the target storage array to be written with data and/or the driving module of the next level according to a write control signal of each storage array, wherein the driving control signal is used to adjust the driving capability of the driving module;

The data paths corresponding to different storage arrays are used to receive different write control signals, and the write control signals are used to connect the data paths and the corresponding storage arrays.

The data writing circuit includes a multi-level driver module and a control module. Each level of the driver module is connected to a plurality of storage arrays of a corresponding level and a driver module of a next level, and drives the data to be written to be transmitted to the data path corresponding to the plurality of storage arrays of a corresponding level and/or the driver module of the next level. Through the cooperation of the multi-level driver modules, the data to be written can be transmitted to the data path corresponding to any storage array. The control module is connected to each level of the driver module, and according to the write control signal of each storage array, a drive control signal is sent to the driver module of the corresponding level of the target storage array and/or the driver module of the next level. The drive control signal is used to adjust the driving ability of the driver module, and the multi-level driver module can be controlled to transmit the data to be written to the data path corresponding to the target storage array, and the time matching will not be affected. In addition, the data paths corresponding to different storage arrays receive different write control signals, and the write control signal is used to connect the data path and the storage array, so that the control of the write control signal can be further utilized to transmit the data to be written to the target storage array, so as to realize the correct writing of the data, and the write control signal only needs to be time-matched with the data signal transmitted to the corresponding storage array, and the difficulty of time matching is greatly reduced.

In one embodiment, the control module is used to send the drive control signal to the drive module of the corresponding level and/or the drive module of the next level if the write control signals of the plurality of storage arrays at the same level are at different levels.

In one embodiment, the driving module is used to adjust its own driving capability upon receiving the driving control signal, wherein the adjusted driving capability is smaller than the driving capability required for transmitting the data to be written to the next-level driving module.

In one of the embodiments, the control module is further configured to send the driving control signal to each level of the driving module after the corresponding level of the target storage array.

In one embodiment, the driving module includes:

A first driving unit, configured to drive the data to be written to be transmitted to the data paths corresponding to the plurality of storage arrays at the corresponding level and to the driving module at the next level when the driving control signal is not received; and to adjust its own driving capability when the driving control signal is received, wherein the adjusted driving capability is less than the driving capability required for transmitting the data to be written to the driving module at the next level;

Among them, when the control module sends a driving control signal to the driving module of the next level of the target storage array to which the data is to be written, the adjusted driving capability is less than the driving capability required for transmitting the data to be written to the data paths corresponding to the multiple storage arrays of the corresponding level; when the control module sends a driving control signal to the driving module of the corresponding level of the target storage array to which the data is to be written, the adjusted driving capability is greater than the driving capability required for transmitting the data to be written to the data paths corresponding to the multiple storage arrays of the corresponding level.

In one embodiment, the driving module includes:

A second driving unit, used for driving the data to be written to be transmitted to data paths corresponding to the plurality of storage arrays at a corresponding level;

The third driving unit is used to drive the data to be written to be transmitted to the driving module of the next level when the driving control signal is not received; and adjust its own driving capability when the driving control signal is received, and the adjusted driving capability is less than the driving capability required for transmitting the data to be written to the driving module of the next level.

In one of the embodiments, the second driving unit is used to adjust its own driving capability when receiving the driving control signal, and the adjusted driving capability is greater than the driving capability required for transmitting the data to be written to the data paths corresponding to the plurality of storage arrays at the corresponding level.

In one embodiment, the driving control signal includes a first sub-control signal and a second sub-control signal, and the driving module includes:

a fourth driving unit, configured to adjust its own driving capability when receiving the first sub-control signal, wherein the adjusted driving capability is greater than the driving capability required for transmitting the to-be-written data to the data paths corresponding to the plurality of storage arrays at the corresponding level;

The fifth driving unit is used to drive the data to be written to be transmitted to the driving module of the next level when the second sub-control signal is not received; and when the second sub-control signal is received, adjust its own driving capability, and the adjusted driving capability is less than the driving capability required for transmitting the data to be written to the driving module of the next level.

In a second aspect, a memory is provided, comprising a plurality of memory arrays and a data writing circuit as provided in the first aspect.

The above-mentioned memory includes a plurality of storage arrays and the data writing circuit as described above, and can also effectively reduce the difficulty of time matching while correctly writing the data to be written into the target storage array.

In a third aspect, a data writing method is provided, comprising:

Generate a drive control signal according to the write control signal of each storage array, wherein the drive control signal is used to adjust the drive capability of the drive module, wherein each level of the drive module is used to connect the multiple storage arrays of the corresponding level and the drive module of the next level, and to drive the data to be written to be transmitted to the data path corresponding to the multiple storage arrays of the corresponding level and/or the drive module of the next level;

Sending the driving control signal to the driving module of the corresponding layer of the target storage array to which the data is to be written and/or the driving module of the next layer, so that the driving module receiving the driving control signal adjusts its own driving capability, wherein the adjusted driving capability is less than the driving capability required for transmitting the data to be written to the driving module of the next layer;

The data paths corresponding to different storage arrays are used to receive different write control signals, and the write control signals are used to connect the data paths and the corresponding storage arrays.

The above-mentioned data writing method first generates a driving control signal according to the writing control signal of each storage array, and the driving control signal is used to adjust the driving capability of the driving module. Each level of the driving module is connected to the multiple storage arrays of the corresponding level and the driving module of the next level, and can drive the data to be written to be transmitted to the data path corresponding to the multiple storage arrays of the corresponding level and/or the driving module of the next level. Then, the driving control signal is sent to the driving module of the corresponding level of the target storage array to be written and/or the driving module of the next level, so that the driving module receiving the driving control signal adjusts its own driving capability, and the adjusted driving capability is less than the driving capability required for transmitting the data to be written to the driving module of the next level. In this way, the multi-level driving module transmits the data to be written to the driving module of the corresponding level of the target storage array step by step, that is, it stops transmitting the data to be written to the driving module of the next level, and transmits the data to be written to the data path corresponding to the target storage array. Then, the data paths corresponding to different storage arrays receive different write control signals. The write control signals are used to connect the data paths and the corresponding storage arrays, and can further transmit the data to be written to the target storage array to achieve correct data writing. Moreover, the write control signals only need to be time-matched with the data signals transmitted to the corresponding storage arrays, and the difficulty of time matching is greatly reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

FIG1 is a schematic structural diagram of a data writing circuit in the related art;

FIG2 is a schematic structural diagram of a data writing circuit according to an embodiment;

FIG3 is a schematic diagram of the structure of a memory according to an embodiment;

FIG. 4 is a flow chart of a data writing method according to an embodiment of the present invention.

Description of reference numerals:

110, data module, 120, controller, 130, storage array, 140, drive module;

200, data writing circuit, 210, driving module, 220, control module, 230, storage array, 290, data module.

DETAILED DESCRIPTION

In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

It is understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

When used herein, the singular forms "a", "an", and "said/the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include/comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and/or" used in this specification includes any and all combinations of the relevant listed items.

DRAM is usually arranged in a two-dimensional matrix with a capacitor and a transistor as a unit. The gate of the transistor is electrically connected to the word line (WL), the source of the transistor is electrically connected to the bit line (BL), and the drain of the transistor is electrically connected to the capacitor. The voltage on the word line controls the opening and closing of the transistor, so that the data information stored in the capacitor is read through the bit line, or the data information is written into the capacitor.

The data writing process is implemented by a data writing circuit. FIG1 is a schematic diagram of the structure of a data writing circuit in the related art. As shown in FIG1 , a data module 110 and a controller (English: controller) 120 are arranged on the same side of a plurality of storage arrays (English: bank) 130. The plurality of storage arrays 130 are arranged in a plurality of levels in a direction away from the data module 110 and the controller 120. A driving module 140 is arranged in each level.

When writing data, the data module 110 sends the data signal to the first-level driver module 140. The driver module 140 of each level can drive the data signal to be transmitted to the data path of each storage array 130 of the same level and the driver module 140 of the next level. Each storage array 130 receives the data signal from the corresponding data path, thereby realizing the transmission of the data signal to any storage array 130.

The control process of transmitting the data signal to the storage array 130 to be written with data is as follows:

The controller 120 sends the write control signal of each storage array 130 to the first-level driver module 140. Each level of driver module 140 transmits the write control signal to the next level of driver module 140 to determine whether to continue driving the data signal to the next level of driver module 140 according to the write control signal.

The driver module 140 of each level performs a logical OR operation on the write control signals of the storage arrays 130 after the corresponding level, and drives the data signal to be transmitted to the data paths of the storage arrays 130 of the same level or the driver module 140 of the next level according to the result of the logical OR operation. If the result of the logical OR operation is valid, it means that the storage array 130 to be written with data is in the storage array 130 after the corresponding level of this driver module 140, and this driver module 140 drives the data signal to be transmitted to the driver module 140 of the next level according to the result of the logical OR operation. On the contrary, if the result of the logical OR operation is invalid, it means that the storage array 130 to be written with data is in the storage array 130 of the corresponding level of this driver module 140, and this driver module 140 drives the data signal to be transmitted to the data paths corresponding to the multiple storage arrays 130 of the corresponding level according to the result of the logical OR operation. It can be understood that in this case, the driver module 140 of the last level does not need to receive the write control signal, but directly transmits the data signal to the data paths corresponding to the multiple storage arrays 130 of the corresponding level.

The controller 120 also sends the write control signal of each memory array 130 to the corresponding memory array 130. Each memory array 130 determines whether to receive a data signal from a corresponding data path according to the corresponding write control signal.

Taking FIG. 1 as an example, 16 storage arrays 130 are arranged in four levels in a direction away from the data module 110 and the controller 120 (FIG. 1 only shows the first and second levels). The storage arrays 130 of the first level are BANK0, BANK1, BANK2, and BANK3, and their respective write control signals are WrtBnk0, WrtBnk1, WrtBnk2, and WrtBnk3. The storage arrays 130 of the second level are BANK4, BANK5, BANK6, and BANK7, and their respective write control signals are WrtBnk4, WrtBnk5, WrtBnk6, and WrtBnk7. The storage arrays 130 of the third level are BANK8, BANK9, BANK10, and BANK11, and their respective write control signals are WrtBnk8, WrtBnk9, WrtBnk10, and WrtBnk11. The fourth-level memory arrays 130 are BANK12, BANK13, BANK14, and BANK15, and their respective write control signals are WrtBnk12, WrtBnk13, WrtBnk14, and WrtBnk15.

The controller 120 sends the write control signals WrtBnk<15:0> of the 16 storage arrays 130 to the first-stage driver module 140, and each stage of the driver module 140 transmits the write control signal WrtBnk<15:0> to the next-stage driver module 140. The first-stage driver module 140 performs a logical OR operation on the write control signals WrtBnk<15:4> of the second-stage to fourth-stage storage arrays 130, and drives the data signal to be transmitted to the data path of the four storage arrays 130 of the first stage or the second-stage driver module 140 according to the result of the logical OR operation. The second-stage driver module 140 performs a logical OR operation on the write control signals WrtBnk<15:8> of the third-stage to fourth-stage storage arrays 130, and drives the data signal to be transmitted to the data path of the four storage arrays 130 of the second stage or the third-stage driver module 140 according to the result of the logical OR operation. That is, each driver module 140 receives write control signals from all storage arrays 130, but only determines to drive data signals to be transmitted to the corresponding data path or the next driver module 140 based on part of the write control signals, or does not drive data signals to be transmitted to the corresponding data path based on the write control signals.

The controller 120 also sends the write control signals WrtBnk0, WrtBnk1, WrtBnk2, WrtBnk3, WrtBnk4, WrtBnk5, WrtBnk6, WrtBnk7, WrtBnk8, WrtBnk9, WrtBnk10, WrtBnk11, WrtBnk12, WrtBnk13, WrtBnk14, and WrtBnk15 of each storage array 130 to BANK0, BANK1, BANK2, BANK3, BANK4, BANK5, BANK6, BANK7, BANK8, BANK9, BANK10, BANK11, BANK12, BANK13, BANK14, and BANK15 respectively. For example, if BANK0 is the storage array 130 to which data is to be written, BANK0 receives a data signal from a corresponding data path according to a corresponding write control signal WrtBnk0, while other storage arrays 130 do not receive data signals from corresponding data paths according to their respective corresponding write control signals.

Therefore, in the related art, the data signal and the write control signal of each storage array 130 need to be time-matched so that the data can be correctly written. As the capacity of DRAM increases, the number of storage arrays continues to increase, the number of write control signals increases accordingly, and time matching becomes increasingly difficult.

Based on the above situation, the present application provides a data writing circuit. FIG2 is a structural diagram of a data writing circuit according to an embodiment of the present application. As shown in FIG2 , the data writing circuit 200 includes a multi-stage driving module 210 and a control module 220 .

Each level of driving module 210 is used to connect the multiple storage arrays 230 of the corresponding level and the driving module 210 of the next level, and to drive the data to be written to be transmitted to the corresponding data path of the multiple storage arrays 230 of the corresponding level and/or the driving module 210 of the next level.

The control module 220 is connected to each level of the driving module 210, and is used to send a driving control signal WrtEn to the driving module 210 of the corresponding level of the target storage array to be written data and/or the driving module 210 of the next level according to the write control signal WrtBnk of each storage array 230. The driving control signal WrtEn is used to adjust the driving capability of the driving module 210.

The data paths corresponding to different storage arrays 230 are used to receive different write control signals WrtBnk, and the write control signal WrtBnk is used to connect the data paths and the corresponding storage arrays 230 .

In one embodiment, the control module 220 sends a drive control signal WrtEn to the driver module 210 of the corresponding level of the target storage array to be written according to the write control signal WrtBnk of each storage array 230, and the driver module 210 of the corresponding level of the target storage array adjusts its own drive capability, and can only drive the data to be written to be transmitted to the data path corresponding to the target storage array, and cannot drive the data to be written to be transmitted to the next level of the driver module 210. Correspondingly, the driver module 210 before the corresponding level of the target storage array maintains the default drive capability, and can drive the data to be written to be transmitted to the next level of the driver module 210. In this way, the multi-level driver modules 210 cooperate with each other, and the data to be written can be transmitted from the first level of the driver module 210 to the data path corresponding to the target storage array step by step. The target storage array then receives the data to be written from the corresponding data path according to the corresponding write control signal WrtBnk, so as to further transmit the data to be written to the target storage array.

In another embodiment, the control module 220 sends a drive control signal WrtEn to the next-level driver module 210 of the target storage array to be written according to the write control signal WrtBnk of each storage array 230, and the next-level driver module 210 of the target storage array adjusts its own drive capability and cannot drive the data to be written to be transmitted to the data paths corresponding to the multiple storage arrays 230 of the corresponding level and the next-level driver module 210. Accordingly, the driver modules 210 before the corresponding level of the target storage array maintain the default drive capability and can drive the data to be written to be transmitted to the next-level driver module 210. In this way, the multi-level driver modules 210 cooperate with each other, and the data to be written can be transmitted from the first-level driver module 210 to the data path corresponding to the target storage array step by step.

That is to say, the present invention has two ideas to achieve writing the data to be written only to the data path corresponding to the target storage array, but not to the data path corresponding to the storage array 230 of the next level of the target storage array. The first is to change the driving capability of the driver module 210 of the corresponding level of the target storage array, so that the driver module 210 can only transmit the data to be written (data signal) to the data path of the corresponding level, but cannot transmit it to the driver module 210 of the next level; the second is to change the driving capability of the driver module 210 of the next level of the target storage array, so that the driver module 210 of the next level can neither transmit the data to the data path of the corresponding level nor to the driver module 210 of the next level after receiving the data. It should be noted that the adjusted driving capability in this article is less than the driving capability required for a certain action, which includes two types: "weakened and unable" and "lost and unable".

In the related art, each level of driver module 110 performs logic judgment according to the write control signal WrtBnk of multiple storage arrays 130, and transmits the data signal to the next level of driver module 110 when the result of the logic judgment is valid, so as to transmit the data signal step by step to the driver module 110 of the corresponding level of the target storage array to be written with data. In this way, the write control signal WrtBnk of each storage array 130 needs to be time-matched with the timing of writing the data signal to the corresponding data path to ensure accurate writing of data, which will seriously affect the time matching of the data signal when the number of storage arrays 130 is large, because as the level of the target storage array is higher, the path time is getting longer and longer, and the interference is getting greater and greater, and the difficulty of time matching is very great. In the present application, the control module 220 generates a driving control signal WrtEn according to the write control signals WrtBnk of the plurality of storage arrays 230, and sends the driving control signal WrtEn to the driving module 210 of the corresponding level of the target storage array to which data is to be written and/or the driving module 210 of the next level, so as to prevent the data signal from being further transmitted. Before the data signal is blocked from transmission, there is no judgment or other part that may cause the data signal to wait or be delayed. Therefore, it is only necessary to ensure that the data signal and the write control signal WrtBnk of the target storage array maintain timing matching, without considering the influence of the judgment and other steps on the timing, which is conducive to ensuring the normal writing of data.

Exemplarily, as shown in FIG. 2 , the control module 220 and the data module 290 are arranged on the same side of the plurality of storage arrays 230 , and the plurality of storage arrays 230 are arranged in multiple levels in a direction away from the data module 290 and the control module 220 , and each level is provided with a plurality of storage arrays 230 and a drive module 210 .

The control module 220 includes a logic control device, such as a multiplexer, and sends a drive control signal WrtEn to the drive module 210 of the corresponding layer of the target storage array to be written and/or the next-level drive module 210 according to the write control signal WrtBnk of each storage array 230. The drive module 210 may include a plurality of cascaded inverters to drive the data to be written to be transmitted to the corresponding data paths of the plurality of storage arrays 230 of the corresponding layer and/or the next-level drive module 210. The drive module 210 may also include a switch tube to adjust its own drive capability according to the drive control signal WrtEn.

In one embodiment, the control module 220 is configured to send a driving control signal WrtEn to a driving module 210 at a corresponding level and/or a driving module 210 at a next level if the write control signals WrtBnk of multiple storage arrays 230 at the same level are at different levels.

In the above embodiment, the write control signals WrtBnk of the multiple storage arrays 230 of the same level are at different levels, indicating that one of the multiple storage arrays 230 of this level is a target storage array. At this time, sending the drive control signal WrtEn to the drive module 210 of the corresponding level and/or the drive module 210 of the next level can enable the drive module 210 of the corresponding level of the target storage array and/or the drive module 210 of the next level to adjust its own driving capability.

Accordingly, the control module 220 is used to not send the driving control signal WrtEn to the driving module 210 of the corresponding level and/or the driving module 210 of the next level if the write control signals WrtBnk of the multiple storage arrays 230 of the same level are at the same level, so as to avoid unnecessary adjustment.

In one embodiment, the driving module 210 is configured to adjust its own driving capability upon receiving the driving control signal WrtBnk, wherein the adjusted driving capability is smaller than the driving capability required for transmitting the to-be-written data to the next-level driving module 210 .

In the above embodiment, when the driving module 210 receives the driving control signal WrtBnk, it adjusts its own driving capability to be less than the driving capability required to transmit the data to be written to the driving module 210 of the next level, so that the driving module 210 that receives the driving control signal WrtBnk cannot transmit the data to be written to the driving module 210 of the next level, and the step-by-step transmission of the data to be written is stopped.

In one implementation, if the driver module 210 of the corresponding level of the target storage array receives the driving control signal WrtBnk, the adjusted driving capability is greater than or equal to the driving capability required by the data paths corresponding to the plurality of storage arrays 230 of the corresponding level to transmit the data to be written.

In another implementation, if the driver module 210 at the next level of the target storage array receives the drive control signal WrtBnk, the adjusted drive capability can be greater than or equal to the drive capability required for the data path corresponding to the multiple storage arrays 230 at the corresponding level to transmit the data to be written, or it can be less than the drive capability required for the data path corresponding to the multiple storage arrays 230 at the corresponding level to transmit the data to be written.

Exemplarily, the control module 220 is further configured to send a driving control signal WrtEn to each level of driving module 210 after the corresponding level of the target storage array.

In the above embodiment, the control module 220 sends a drive control signal WrtEn to each level of drive module 210 after the corresponding level of the target storage array, so that each level of drive module 210 after the corresponding level of the target storage array will adjust its own drive capability, so that all drive modules 210 that do not need to transmit can be turned off to avoid data transmission errors and additional power consumption caused by normal data transmission of subsequent drive modules 210 when the drive modules 210 of the corresponding level of the target storage array fail to work normally.

In one embodiment, the control module 220 is further configured to send a write enable signal to the driver module 210 of each stage.

Correspondingly, the driving module 210 is also used to drive the to-be-written data to be transmitted to the driving module 210 of the next stage if the write enable signal is received but the drive control signal WrtEn is not received.

In the above embodiment, the control module 220 first sends a write enable signal to the driver module 210 of each level, so that the driver module 210 of each level has the ability to drive the data to be written to be transmitted to the driver module 210 of the next level. Through the cooperation of multiple levels of driver modules 210, the data to be written can be transmitted step by step to the driver module 210 of the corresponding level of the target storage array.

Exemplarily, the data writing circuit 200 further includes an enable signal line. The enable signal line is connected to the control module 220 or the driving module 210, and is used to transmit the write enable signal to each level of the driving module 210 through the control module 220 or directly.

In the above embodiment, if the enable signal line is connected to the control module 220, the control module 220 transmits the write enable signal to each level of the driving module 210 through the enable signal line. If the enable signal line is connected to the driving module 210, the write enable signal is directly transmitted to each level of the driving module 210 through the enable signal line. Therefore, by setting the enable signal line, the write enable signal can be transmitted to each level of the driving module 210.

In one embodiment, the driving module 210 includes a first driving unit. The first driving unit is used to, when the driving control signal WrtEn is not received, drive the data to be written to be transmitted to the data path corresponding to the plurality of storage arrays 230 of the corresponding level and to the driving module 210 of the next level; when the driving control signal WrtEn is received, adjust its own driving capability, and the adjusted driving capability is less than the driving capability required to transmit the data to be written to the driving module 210 of the next level.

Among them, when the control module 220 sends the driving control signal WrtEn to the driving module 210 of the next level of the target storage array to which data is to be written, the adjusted driving capability is less than the driving capability required for transmitting the data to be written to the data paths corresponding to the multiple storage arrays 230 of the corresponding level; when the control module 220 sends the driving control signal WrtEn to the driving module 210 of the corresponding level of the target storage array to which data is to be written, the adjusted driving capability is greater than the driving capability required for transmitting the data to be written to the data paths corresponding to the multiple storage arrays 230 of the corresponding level.

In the above embodiment, if the driver module 210 before the corresponding level of the target storage array does not receive the driving control signal WrtEn, the first driving unit can drive the data to be written to be transmitted to the data paths corresponding to the multiple storage arrays 230 of the corresponding level and to the driver module 210 of the next level. In this way, the data to be written can be transmitted step by step to the driver module 210 of the corresponding level of the target storage array.

If the driver module 210 of the corresponding level of the target storage array receives the driving control signal WrtEn, the first driver unit adjusts its own driving capability, and the adjusted driving capability is less than the driving capability required to transmit the data to be written to the driver module 210 of the next level, and greater than the driving capability required to transmit the data to be written to the data path corresponding to the multiple storage arrays 230 of the corresponding level, and the data to be written can be driven to be transmitted to the data path corresponding to the multiple storage arrays 230 of the corresponding level. In this way, the data to be written can be further transmitted to the data path corresponding to the target storage array.

If the driver module 210 of the next level of the target storage array receives the driving control signal WrtEn, and the driver module 210 of the corresponding level of the target storage array does not receive the driving control signal WrtEn, the first driver unit of the corresponding level of the target storage array can drive the data to be written to be transmitted to the data path corresponding to the multiple storage arrays 230 of the corresponding level and the driver module 210 of the next level, so as to further transmit the data to be written to the data path corresponding to the target storage array. The driver module 210 of the next level of the target storage array receives the driving control signal WrtEn, and the first driver unit adjusts its own driving capability. The adjusted driving capability is less than the driving capability required to transmit the data to be written to the driver module 210 of the next level, and is less than the driving capability required to transmit the data to be written to the data path corresponding to the multiple storage arrays 230 of the corresponding level, and stops the transmission of the data to be written.

In one embodiment, the driving module 210 includes a second driving unit and a third driving unit. The second driving unit is used to drive the data to be written to be transmitted to the data path corresponding to the multiple storage arrays 230 of the corresponding level. The third driving unit is used to drive the data to be written to be transmitted to the next level driving module 210 when the driving control signal WrtEn is not received; when the driving control signal WrtEn is received, the third driving unit is used to adjust its own driving capability, and the adjusted driving capability is less than the driving capability required to transmit the data to be written to the next level driving module 210.

If the driver module 210 of the corresponding level of the target storage array receives the driving control signal WrtEn, the third driver unit adjusts its own driving capability, and the adjusted driving capability is less than the driving capability required to transmit the data to be written to the driver module 210 of the next level. At this time, the second driver unit can still drive the data to be written to be transmitted to the data paths corresponding to the multiple storage arrays of the corresponding level. In this way, the data to be written can be further transmitted to the data path corresponding to the target storage array.

If the driver module 210 of the next level of the target storage array receives the drive control signal WrtEn, and the driver module 210 of the corresponding level of the target storage array does not receive the drive control signal WrtEn, the third driver unit of the corresponding level of the target storage array can drive the data to be written to be transmitted to the driver module 210 of the next level. At this time, the second driver unit can still drive the data to be written to be transmitted to the data path corresponding to the multiple storage arrays of the corresponding level, so as to further transmit the data to be written to the data path corresponding to the target storage array. The driver module 210 of the next level of the target storage array receives the drive control signal WrtEn, and the third driver unit adjusts its own driving capability. The adjusted driving capability is less than the driving capability required to transmit the data to be written to the driver module 210 of the next level, and stops the transmission of the data to be written.

Exemplarily, the second driving unit is used to adjust its own driving capability when receiving the driving control signal WrtEn, and the adjusted driving capability is greater than the driving capability required for the data path corresponding to the plurality of storage arrays 230 of the corresponding level to transmit the data to be written.

In the above embodiment, the driver module 210 of the corresponding level of the target storage array receives the driving control signal WrtEn, and the second driving unit adjusts its driving capability, and the adjusted driving capability is greater than the driving capability required for transmitting the data to be written to the data paths corresponding to the multiple storage arrays 230 of the corresponding level, thereby further transmitting the data to be written to the data path corresponding to the target storage array. The driver module 210 of the corresponding level of the non-target storage array does not receive the driving control signal WrtEn, and the driving capability of the second driving unit is less than the driving capability required for transmitting the data to be written to the data paths corresponding to the multiple storage arrays 230 of the corresponding level, thereby reducing unnecessary transmission.

In one embodiment, the driving control signal includes a first sub-control signal and a second sub-control signal, and the driving module includes a fourth driving unit and a fifth driving unit. The fourth driving unit is used to adjust its own driving capability when receiving the first sub-control signal, and the adjusted driving capability is greater than the driving capability required for transmitting the data to be written to the data path corresponding to the multiple storage arrays 230 of the corresponding level. The fifth driving unit is used to drive the data to be written to be transmitted to the driving module 210 of the next level when the second sub-control signal is not received; when receiving the second sub-control signal, it adjusts its own driving capability, and the adjusted driving capability is less than the driving capability required for transmitting the data to be written to the driving module 210 of the next level. In other words, the first sub-control signal and the second sub-control signal can be two independent signals.

In the above embodiment, the driver module 210 before the corresponding level of the target storage array has not received the first sub-control signal and the second sub-control signal, and the driving capability of the fourth driver unit is less than the driving capability required for transmitting the data to be written to the data paths corresponding to the multiple storage arrays 230 of the corresponding level, and the fifth driver unit can drive the data to be written to be transmitted to the next level of driver module 210. In this way, the data to be written can be transmitted step by step from the first level of driver module 210 to the driver module 210 of the corresponding level of the target storage array.

The driver module 210 of the corresponding level of the target storage array receives the first sub-control signal, and the fourth driver unit adjusts its own driving capability. The adjusted driving capability is greater than the driving capability required for transmitting the data to be written to the data paths corresponding to the multiple storage arrays 230 of the corresponding level, and can drive the data to be written to be transmitted to the data paths corresponding to the multiple storage arrays of the corresponding level. In this way, the data to be written can be further transmitted to the data path corresponding to the target storage array.

The driver module 210 of the corresponding level or the next level of the target storage array receives the second sub-control signal, and the fifth driver unit adjusts its own driving capability. The adjusted driving capability is less than the driving capability required to transmit the data to be written to the driver module 210 of the next level, and stops the transmission of the data to be written.

Based on the same inventive concept, the present application also provides a memory. FIG3 is a schematic diagram of the structure of a memory of an embodiment of the present application. As shown in FIG3, the memory includes a plurality of memory arrays 230 and a data writing circuit 200. The above-mentioned memory includes a plurality of memory arrays 230 and the data writing circuit 200 as described above, and can also effectively reduce the difficulty of time matching while correctly writing the data to be written into the target memory array.

Based on the same inventive concept, the present application also provides a data writing method. FIG4 is a flow chart of a data writing method according to an embodiment of the present application. As shown in FIG4 , the data writing method includes the following steps:

S401, generating a driving control signal according to the write control signal of each storage array, wherein the driving control signal is used to adjust the driving capability of the driving module, wherein each level of the driving module is used to connect the multiple storage arrays of the corresponding level and the driving module of the next level, and to drive the data to be written to be transmitted to the data path corresponding to the multiple storage arrays of the corresponding level and/or the driving module of the next level.

S402, sending a driving control signal to a driving module of a corresponding layer of a target storage array to which data is to be written and/or a driving module of a next layer, so that the driving module receiving the driving control signal adjusts its own driving capability, and the adjusted driving capability is less than the driving capability required to transmit the data to be written to the driving module of the next layer.

The data paths corresponding to different storage arrays are used to receive different write control signals, and the write control signals are used to connect the data paths and the corresponding storage arrays.

The above-mentioned data writing method first generates a driving control signal according to the writing control signal of each storage array, and the driving control signal is used to adjust the driving capability of the driving module. Each level of the driving module is connected to the multiple storage arrays of the corresponding level and the driving module of the next level, and can drive the data to be written to be transmitted to the data path corresponding to the multiple storage arrays of the corresponding level and/or the driving module of the next level. Then, the driving control signal is sent to the driving module of the corresponding level of the target storage array to be written and/or the driving module of the next level, so that the driving module receiving the driving control signal adjusts its own driving capability, and the adjusted driving capability is less than the driving capability required for transmitting the data to be written to the driving module of the next level. In this way, the multi-level driving module transmits the data to be written to the driving module of the corresponding level of the target storage array step by step, that is, it stops transmitting the data to be written to the driving module of the next level, and transmits the data to be written to the data path corresponding to the target storage array. Then, the data paths corresponding to different storage arrays receive different write control signals. The write control signals are used to connect the data paths and the corresponding storage arrays, and can further transmit the data to be written to the target storage array to achieve correct data writing. Moreover, the write control signals only need to be time-matched with the data signals transmitted to the corresponding storage arrays, and the difficulty of time matching is greatly reduced.

In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims (10)

1. A data writing circuit, comprising:

The multi-stage driving module is used for connecting a plurality of storage arrays of a corresponding level with the driving module of the next level and is used for driving data to be written to be transmitted to data paths corresponding to the plurality of storage arrays of the corresponding level and/or the driving module of the next level;

The control module is connected with each stage of the driving module and is used for sending a driving control signal to the driving module of the corresponding level of the target storage array of the data to be written and/or the driving module of the next stage according to the writing control signal of each storage array, and the driving control signal is used for adjusting the driving capability of the driving module;

The data paths corresponding to different storage arrays are used for receiving different writing control signals, and the writing control signals are used for communicating the data paths with the corresponding storage arrays.

2. The circuit of claim 1, wherein the control module is configured to send the drive control signal to the drive module of a corresponding level and/or the drive module of a next level if the write control signals of the plurality of memory arrays of the same level are at different levels.

3. The circuit of claim 2, wherein the driving module is configured to adjust the driving capability of the driving module if the driving control signal is received, the adjusted driving capability being smaller than the driving capability required by the driving module for transmitting the data to be written to a next stage.

4. The circuit of claim 3, wherein the control module is further configured to send the drive control signal to the drive module at each level subsequent to the corresponding level of the target storage array.

5. The circuit of any of claims 1-4, wherein the drive module comprises:

The first driving unit is used for driving the data to be written to be transmitted to the driving module on the data path corresponding to the storage arrays of the corresponding level and in the next level when the driving control signal is not received; when the driving control signal is received, the driving capacity of the driver is adjusted, and the adjusted driving capacity is smaller than the driving capacity required by the driving module for transmitting the data to be written to the next stage;

When the control module sends a driving control signal to the driving module at the next stage of the target storage array of the data to be written, the adjusted driving capacity is smaller than the driving capacity required by the data paths corresponding to the plurality of storage arrays for transmitting the data to be written to the corresponding level; when the control module sends a driving control signal to the driving module of the corresponding level of the target storage array of the data to be written, the driving capacity after adjustment is larger than the driving capacity required by the data paths corresponding to the plurality of storage arrays of the corresponding level.

6. The circuit of any of claims 1-4, wherein the drive module comprises:

The second driving unit is used for driving the data to be written to be transmitted to the data paths corresponding to the storage arrays of the corresponding level;

The third driving unit is used for driving the data to be written to be transmitted to the driving module of the next stage when the driving control signal is not received; when the driving control signal is received, the driving capability of the driver is adjusted, and the adjusted driving capability is smaller than the driving capability required by the driving module for transmitting the data to be written to the next stage.

7. The circuit of claim 6, wherein the second driving unit is configured to adjust the driving capability of the second driving unit when the driving control signal is received, the adjusted driving capability being greater than the driving capability required for transmitting the data to be written to the data paths corresponding to the plurality of memory arrays of the corresponding hierarchy.

8. The circuit of any of claims 1-4, wherein the drive control signal comprises a first sub-control signal and a second sub-control signal, the drive module comprising:

The fourth driving unit is used for adjusting the driving capability of the fourth driving unit when the first sub-control signal is received, wherein the driving capability after adjustment is larger than the driving capability required by a data path corresponding to a plurality of storage arrays for transmitting the data to be written to a corresponding level;

a fifth driving unit, configured to drive the data to be written to be transmitted to the driving module of the next stage when the second sub-control signal is not received; when the second sub control signal is received, the driving capability of the driver is adjusted, and the adjusted driving capability is smaller than the driving capability required by the driving module for transmitting the data to be written to the next stage.

9. A memory comprising a plurality of memory arrays and a data write circuit as claimed in any one of claims 1 to 8.

10. A data writing method, comprising:

Generating a driving control signal according to a writing control signal of each storage array, wherein the driving control signal is used for adjusting the driving capability of a driving module, and each driving module is used for connecting a plurality of storage arrays of a corresponding level and the driving module of the next level and is used for driving data to be written to be transmitted to a data path corresponding to the plurality of storage arrays of the corresponding level and/or the driving module of the next level;

The driving control signals are sent to the driving module of the corresponding level of the target storage array of the data to be written and/or the driving module of the next level, so that the driving module which receives the driving control signals adjusts the driving capacity of the driving module, and the driving capacity after adjustment is smaller than the driving capacity required by the data to be written to be transmitted to the driving module of the next level;

The data paths corresponding to different storage arrays are used for receiving different writing control signals, and the writing control signals are used for communicating the data paths with the corresponding storage arrays.