CN118860953A - Processor voltage and frequency adjustment method, device, electronic device and storage medium - Google Patents

Abstract

The present invention provides a processor voltage and frequency adjustment method, device, electronic device and storage medium. The processor voltage and frequency adjustment method provided by the present invention includes: monitoring the dynamic voltage and frequency adjustment request of the client; obtaining the frequency change value, timestamp and preset weight configuration value of multiple processing cores corresponding to the dynamic voltage and frequency adjustment request; determining the adjustment order of the voltage and frequency of the multiple processing cores according to the frequency change value, the timestamp and the preset weight configuration value; adjusting the frequency and voltage of the multiple processing cores according to the adjustment order of the voltage and frequency of the multiple processing cores, and the core requested frequency value and the core requested voltage value of the multiple processing cores. The processor voltage and frequency adjustment method of the present invention can enhance the flexibility of the processor in some application scenarios, and can improve the energy efficiency ratio of the processor.

Description

Processor voltage and frequency adjustment method, device, electronic device and storage medium

Technical Field

The present invention relates to the field of processor technology, and in particular to a method, device, electronic device and storage medium for adjusting processor voltage and frequency.

Background Art

As the performance of a single processor continues to improve, its improvement speed has encountered many bottlenecks. Processor manufacturers have proposed placing multiple processing cores inside a single processor, called a multi-core processor, to improve the overall performance of the processor. As the number of cores integrated in a single processor continues to increase, the overall performance of the processor is also constantly improving, but the accompanying problem is that the power consumption, design and manufacturing costs of the processor continue to increase. The industry mainly uses dynamic voltage and frequency adjustment technology to improve the energy efficiency of the processor. There are as many as hundreds of processing cores inside the processor. If each processing core of the processor is to dynamically adjust the voltage and frequency independently, from the perspective of chip design, each processing core needs to have an independent voltage domain and clock domain. From the perspective of motherboard design, each processing core needs to be powered independently from the outside. Some processor manufacturers adopt a solution that all processing cores inside the processor share a unique voltage domain and clock domain, or each processing core inside the processor has an independent clock domain. For the first solution mentioned above, since each processing core cannot independently adjust the frequency and voltage, it lacks flexibility in some application scenarios such as virtualization and fixed-frequency scenarios, thereby limiting the user's usage scenarios; in the second solution mentioned above, each processing core cannot independently adjust the voltage, but can only independently adjust the frequency, which makes the processor energy efficiency relatively low.

Summary of the invention

The purpose of the present invention is to provide a processor voltage and frequency adjustment method, device, electronic device and storage medium to solve the technical problems in the prior art that the processor is not flexible enough in some application scenarios and the energy efficiency of the processor is relatively low.

The technical solution of the present invention is as follows: a method for adjusting processor voltage and frequency is provided, comprising: monitoring a dynamic voltage and frequency adjustment request from a client;

Obtain frequency change values, timestamps, and preset weight configuration values of multiple processing cores corresponding to the dynamic voltage and frequency adjustment request;

Determining an adjustment order of voltages and frequencies of the plurality of processing cores according to the frequency change value, the timestamp, and the preset weight configuration value;

The frequencies and voltages of the multiple processing cores are adjusted according to the adjustment order of the voltages and frequencies of the multiple processing cores, and the core-requested frequency values and core-requested voltage values of the multiple processing cores.

Further, the monitoring of the dynamic voltage and frequency adjustment request of the client includes monitoring the dynamic voltage and frequency adjustment requests of multiple clients;

Correspondingly, before obtaining the frequency change values, timestamps and preset weight configuration values of multiple processing cores corresponding to the dynamic voltage and frequency adjustment request, it also includes determining the response order of the dynamic voltage and frequency adjustment requests of the clients according to the performance requirement modes of the multiple clients, and the performance requirement modes include hardware automatic control performance mode, low power consumption control mode, temperature control mode, power consumption control mode or operating system internal control processing core performance mode.

Further, monitoring the dynamic voltage and frequency adjustment requests of multiple clients includes:

At each interval preset duration, the client's dynamic voltage and frequency adjustment request is polled once to monitor the dynamic voltage and frequency adjustment requests of multiple clients, or, after receiving the dynamic voltage and frequency adjustment request sent by the client, the monitoring of the dynamic voltage and frequency adjustment request is woken up to monitor the dynamic voltage and frequency adjustment requests of multiple clients.

Further, obtaining frequency change values of multiple processing cores corresponding to the dynamic voltage and frequency adjustment request includes:

The core-requested frequency values and current frequency values of the multiple processing cores corresponding to the dynamic voltage frequency adjustment request are obtained, and a frequency change value is obtained according to the core-requested frequency values and the current frequency values.

Further, obtaining timestamps of multiple processing cores corresponding to the dynamic voltage and frequency adjustment request includes:

The current time point of the core request and the time point of the last core request of the multiple processing cores corresponding to the dynamic voltage and frequency adjustment request are obtained, and the timestamp is obtained according to the current time point of the core request and the time point corresponding to the last core request.

Further, determining the adjustment order of the voltage and frequency of the plurality of processing cores according to the frequency change value, the timestamp, and the preset weight configuration value includes:

An arbitration value is determined according to the frequency change value, the timestamp, the preset weight configuration value and an arbitration calculation formula, and an adjustment sequence of the voltage and frequency of the multiple processing cores is determined according to the arbitration value, wherein the arbitration calculation formula includes , wherein V is the arbitration value, weight is the preset weight configuration value, is the frequency change value, and m is the preset dimension value.

Further, adjusting the frequencies and voltages of the multiple processing cores according to the adjustment order of the voltages and frequencies of the multiple processing cores, and the core-requested frequency values and the core-requested voltage values of the multiple processing cores, comprises:

According to the adjustment order of the voltages and frequencies of the multiple processing cores, as well as the core-requested frequency values and core-requested voltage values of the multiple processing cores, the frequencies and voltages of the multiple processing cores are adjusted in sequence; if the core-requested voltage value of the processing core is less than the actual voltage value of the current shared voltage domain of the processing core, the voltage of the processing core is not adjusted.

Another technical solution of the present invention is as follows: a processor voltage and frequency adjustment device is also provided, including a monitoring module, a processing core information acquisition module, an adjustment sequence determination module and an adjustment module;

The monitoring module is used to monitor the dynamic voltage and frequency adjustment request of the client;

The processing core information acquisition module is used to obtain frequency change values, timestamps and preset weight configuration values of multiple processing cores corresponding to the dynamic voltage and frequency adjustment request;

The adjustment sequence determination module is used to determine the adjustment sequence of the voltage and frequency of the multiple processing cores according to the frequency change value, the timestamp and the preset weight configuration value;

The adjustment module is used to adjust the frequencies and voltages of the multiple processing cores according to the adjustment order of the voltages and frequencies of the multiple processing cores, and the core-requested frequency values and core-requested voltage values of the multiple processing cores.

Another technical solution of the present invention is as follows: an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program executable by the processor, and when the processor executes the computer program, the processor voltage and frequency adjustment method as described in any of the above technical solutions is implemented.

Another technical solution of the present invention is as follows: a computer-readable storage medium is also provided, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the processor voltage and frequency adjustment method described in any of the above technical solutions is implemented.

The beneficial effects of the present invention are: monitoring the dynamic voltage and frequency adjustment request of the client; obtaining the frequency change values, timestamps and preset weight configuration values of multiple processing cores corresponding to the dynamic voltage and frequency adjustment request; determining the adjustment order of the voltage and frequency of the multiple processing cores according to the frequency change values, the timestamps and the preset weight configuration values; adjusting the frequency and voltage of the multiple processing cores according to the adjustment order of the voltage and frequency of the multiple processing cores, as well as the core requested frequency values and core requested voltage values of the multiple processing cores; through the above technical scheme, the flexibility of the processor in some application scenarios can be enhanced, and the energy efficiency ratio of the processor can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic flow chart of a method for adjusting processor voltage and frequency according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a framework for adjusting processor voltage and frequency according to an embodiment of the present invention.

FIG3 is a schematic diagram of the structure of a processor voltage and frequency adjustment device provided by an embodiment of the present invention.

FIG. 4 is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention.

FIG5 is a schematic diagram of the structure of a computer-readable storage medium provided by an embodiment of the present invention.

DETAILED DESCRIPTION

The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

FIG1 is a flowchart of a method for adjusting processor voltage and frequency according to an embodiment of the present invention. It should be noted that the method for adjusting processor voltage and frequency according to the present invention is not limited to the flowchart sequence shown in FIG1 if substantially the same results are achieved. As shown in FIG1 , the method for adjusting processor voltage and frequency includes:

S101, monitoring a dynamic voltage and frequency adjustment request from a client;

As an implementation method, a framework diagram of processor voltage and frequency adjustment is shown in FIG2 . In FIG2 , processing cores Core 0-n represent n+1 processing cores inside the processor, and each processing core can perform dynamic voltage and frequency adjustment. The microprocessor unit MCU in FIG2 can be used to initialize and configure a dynamic voltage and frequency adjustment control unit (DVFS controller). The functions of the microprocessor unit can be implemented in software, and the functions of the dynamic voltage and frequency adjustment control unit can be implemented in software to achieve the same logical functions as the hardware of the dynamic voltage and frequency adjustment control unit.

In some embodiments, monitoring dynamic voltage and frequency adjustment requests from multiple clients includes:

At each interval preset duration, the client's dynamic voltage and frequency adjustment request is polled once to monitor the dynamic voltage and frequency adjustment requests of multiple clients, or, after receiving the dynamic voltage and frequency adjustment request sent by the client, the monitoring of the dynamic voltage and frequency adjustment request is woken up to monitor the dynamic voltage and frequency adjustment requests of multiple clients.

As an implementation mode, during the processor startup phase, the internal firmware of the microprocessor unit initializes the dynamic voltage and frequency adjustment control unit, performs basic configuration and enables it. After the dynamic voltage and frequency adjustment control unit is enabled, it can be in a monitoring state and can receive dynamic voltage and frequency adjustment (DVFS) requests from various clients. The monitoring mode of the dynamic voltage and frequency adjustment control unit may include an active mode and a passive mode. In the active mode, according to the configured period, at each interval of a preset duration, polling can be performed to determine whether a dynamic voltage and frequency adjustment request is triggered. When the dynamic voltage and frequency adjustment control unit is configured in this mode, the dynamic voltage and frequency adjustment control unit polls at each interval of a preset duration to determine whether a dynamic voltage and frequency adjustment request is received, so as to collect the dynamic voltage and frequency adjustment requests of various clients in batches. In the passive mode, each client can actively wake up the dynamic voltage and frequency adjustment control unit by sending a dynamic voltage and frequency adjustment request. After receiving the dynamic voltage and frequency adjustment request sent by the client, the dynamic voltage and frequency adjustment control unit will wake up its monitoring of the dynamic voltage and frequency adjustment request, thereby realizing the monitoring of the dynamic voltage and frequency adjustment request to collect the dynamic voltage and frequency adjustment request of the client.

In some embodiments, the monitoring of the dynamic voltage and frequency adjustment request of the client includes monitoring the dynamic voltage and frequency adjustment requests of multiple clients;

Correspondingly, before obtaining the frequency change values, timestamps and preset weight configuration values of multiple processing cores corresponding to the dynamic voltage and frequency adjustment request, it also includes determining the response order of the dynamic voltage and frequency adjustment requests of the clients according to the performance requirement modes of the multiple clients, and the performance requirement modes include hardware automatic control performance mode, low power consumption control mode, temperature control mode, power consumption control mode or operating system internal control processing core performance mode.

As an implementation mode, a response order of the dynamic voltage and frequency adjustment requests of the clients is determined according to the performance requirement modes of the multiple clients, and the response order of the dynamic voltage and frequency adjustment requests of the clients corresponding to different performance requirement modes may be, in sequence, the dynamic voltage and frequency adjustment request of the client corresponding to the low power control mode, the dynamic voltage and frequency adjustment request of the client corresponding to the temperature control mode, the dynamic voltage and frequency adjustment request of the client corresponding to the power consumption control mode, the dynamic voltage and frequency adjustment request of the client corresponding to the hardware automatic control performance mode, and the dynamic voltage and frequency adjustment request of the client corresponding to the operating system internal control processing core performance mode, wherein the response priority of the dynamic voltage and frequency adjustment request of the client corresponding to the temperature control mode and the dynamic voltage and frequency adjustment request of the client corresponding to the power consumption control mode may be the same; for example, if the performance requirement mode of the first client is the low power control mode and the performance requirement mode of the second client is the temperature control mode, the dynamic voltage and frequency adjustment request of the first client will be responded to first.

As an implementation mode, as shown in FIG2 , a dynamic voltage and frequency adjustment request arbitration unit (DVFS requestarbiter) can be used to arbitrate dynamic voltage and frequency adjustment requests of each client. In FIG2 , a dynamic voltage and frequency adjustment control request register table (DVFS Request register Table) corresponds to one table for each client. The client corresponding to the hardware automatic control performance mode and the client corresponding to the control processing core performance mode in the operating system can share the same table. Each entry in the table corresponds to a dynamic voltage and frequency adjustment control request register (DVFSRequest register) of each processing core. The dynamic voltage and frequency adjustment processing core entry register table is shown in Table 1.

Table 1 Dynamic voltage and frequency adjustment processing core entry register table

The client's id table is shown in Table 2.

Table 2 Client ID table

The second row in Table 2 represents the client ID, and the third row in Table 2 represents the performance requirement mode of the client corresponding to the ID. In Table 2, perf management, thermal management, power management, and low power management respectively represent the hardware automatic control performance mode, temperature control mode, power consumption control mode, and low power consumption control mode. The priority can be configured independently for each client, 0 represents the lowest priority, and 15 represents the highest priority. The priority definition of the client is shown in Table 3.

Table 3 Client priority table

The second row of Table 3 indicates the IDs corresponding to different clients, and the third row of Table 3 indicates the priorities of clients with different IDs.

As an implementation mode, the hardware automatic performance control unit (hardware performance management) in Figure 2 can be a client corresponding to the hardware automatic performance control mode, and the unit indicates that the dynamic voltage and frequency adjustment request (dynamic voltage and frequency adjustment control request) is sent by automatically analyzing the processor performance requirements through hardware. The low power control unit (low power management) can be a client of the low power control mode. The unit sends a dynamic voltage and frequency adjustment request when the processing core enters or exits the low power state. The temperature control unit (thermal management) can be a client of the temperature control mode. The unit collects temperature and sends a dynamic voltage and frequency adjustment request when temperature control is required. The power consumption control unit (power limit management) can be a client corresponding to the power consumption control mode. The unit collects power consumption and sends a dynamic voltage and frequency adjustment request when power consumption control is required. The processor dynamic voltage and frequency adjustment driver unit (CPU DVFS driver) represents a driver unit that controls the core performance of the processor in the operating system, and can be a client corresponding to the core performance mode of the processing in the operating system. The unit sends a dynamic voltage and frequency adjustment request according to the dynamic performance requirements of the application.

S102, obtaining frequency change values, timestamps, and preset weight configuration values of multiple processing cores corresponding to the dynamic voltage and frequency adjustment request;

In some embodiments, obtaining frequency change values of multiple processing cores corresponding to the dynamic voltage and frequency adjustment request includes:

The core-requested frequency values and current frequency values of the multiple processing cores corresponding to the dynamic voltage frequency adjustment request are obtained, and a frequency change value is obtained according to the core-requested frequency values and the current frequency values.

As an implementation method, a dynamic voltage and frequency adjustment request from a client corresponds to multiple processing cores. After the dynamic voltage and frequency adjustment request is sent to the processing core, a core request of the processing core is generated, and the frequency change values of the multiple processing cores are obtained by obtaining the core request frequency value and the current frequency value of each processing core. The larger the frequency change value of the processing core, the higher the priority of its voltage and frequency adjustment.

In some embodiments, obtaining timestamps of multiple processing cores corresponding to the dynamic voltage and frequency adjustment request includes:

The current time point of the core request of the multiple processing cores corresponding to the dynamic voltage and frequency adjustment request and the time point corresponding to the last core request are obtained, and the timestamp is obtained according to the current time point of the core request and the time point of the last core request.

As an implementation method, after the dynamic voltage and frequency adjustment request is sent to the processing core, a core request of the processing core is generated. By obtaining the current time point of the core request of each processing core and the time point corresponding to the last core request, the current time point is subtracted from the time point corresponding to the last core request to obtain a timestamp (time difference), and then the timestamps of multiple processing cores are obtained.

S1033, determining an adjustment order of voltages and frequencies of the plurality of processing cores according to the frequency change value, the timestamp, and the preset weight configuration value;

In some embodiments, determining the adjustment order of the voltage and frequency of the plurality of processing cores according to the frequency change value, the timestamp, and the preset weight configuration value includes:

An arbitration value is determined according to the frequency change value, the timestamp, the preset weight configuration value and an arbitration calculation formula, and an adjustment sequence of the voltage and frequency of the multiple processing cores is determined according to the arbitration value, wherein the arbitration calculation formula includes , wherein V is the arbitration value, weight is the preset weight configuration value, is the frequency change value, and m is the preset dimension value.

As an implementation mode, as shown in FIG. 2 , the preset dimension value m is related to the value range of the preset weight configuration value weight . The dynamic voltage frequency adjustment configuration register (DVFS configuration register) is used to control the dynamic voltage frequency adjustment control unit. The configuration format of the dynamic voltage frequency adjustment configuration register is shown in Table 4.

Table 4 Configuration format of dynamic voltage frequency adjustment configuration register

The second to fifth rows of Table 4 are the bit value range, preset weight configuration, preset weight configuration value and corresponding description respectively. The preset dimension value weight ranges from 0 to 255, and the preset dimension value m is 256. The preset weight configuration value is 0, and the corresponding description can be that it tends to arbitrate the optimal power consumption. The preset weight configuration value is 255, and the corresponding description can be that it tends to arbitrate the optimal performance. The preset weight configuration value is a number between 0 and 255, and the corresponding description is that it is between the optimal power consumption and the optimal performance of arbitration.

S104, adjusting the frequencies and voltages of the multiple processing cores according to the adjustment order of the voltages and frequencies of the multiple processing cores, and the core-requested frequency values and core-requested voltage values of the multiple processing cores.

As an implementation method, under the same client, the adjustment order of the voltage and frequency of multiple processing cores can be determined according to the frequency change value, timestamp, preset weight configuration value and arbitration value V determined by arbitration calculation formula. The larger the arbitration value V is, the higher the adjustment priority of the voltage and frequency of the corresponding processing core is. The core request of the corresponding processing core is first input to the dynamic voltage and frequency adjustment processing unit (DVFS handler) of Figure 2. The dynamic voltage and frequency adjustment processing unit is used to process specific dynamic voltage and frequency adjustment requests (or core requests). The dynamic voltage and frequency adjustment processing unit is used to adjust the voltage and frequency of the processing core through the clock generation unit and the board power supply module unit. In Figure 2, the processing core Core 0-n clock generation unit (Core 0-n clock generator), each processing core corresponds to a private clock generation unit to provide a clock for the corresponding processing core, and the dynamic voltage and frequency adjustment processing unit can directly control this unit to adjust the frequency of the corresponding processing core. In FIG. 2 , the voltage regulator (VR) provides the voltage required for the processing cores Core0-n to work. The specific number of the voltage regulators can be determined based on the target energy efficiency ratio. The dynamic voltage and frequency adjustment processing unit can directly control this unit to adjust the voltage of the corresponding processing core.

In some embodiments, adjusting the frequencies and voltages of the multiple processing cores according to the adjustment order of the voltages and frequencies of the multiple processing cores, and the core-requested frequency values and the core-requested voltage values of the multiple processing cores includes:

According to the adjustment order of the voltages and frequencies of the multiple processing cores, as well as the core-requested frequency values and core-requested voltage values of the multiple processing cores, the frequencies and voltages of the multiple processing cores are adjusted in sequence; if the core-requested voltage value of the processing core is less than the actual voltage value of the current shared voltage domain of the processing core, the voltage of the processing core is not adjusted.

As an implementation method, the dynamic voltage and frequency adjustment request arbitration unit can output arbitration information, and the dynamic voltage and frequency adjustment processing unit receives the arbitration information output by the dynamic voltage and frequency adjustment request arbitration unit, and configures the voltage and frequency of the corresponding processing core according to the arbitration information. The arbitration information includes the processing core ID, the voltage ID and the frequency ID. The specific processing core can be determined according to the processing core ID, and the specific core requested frequency value and the core requested voltage value can be determined respectively according to the voltage ID and the frequency ID. If the voltage required by the arbitrated processing core (the voltage value requested by the core) is less than the actual voltage value of the current shared voltage domain, only the frequency can be adjusted without adjusting the voltage.

The processor voltage and frequency adjustment method of the embodiment of the present invention monitors the dynamic voltage and frequency adjustment request of the client; obtains the frequency change value, timestamp and preset weight configuration value of multiple processing cores corresponding to the dynamic voltage and frequency adjustment request; determines the adjustment order of the voltage and frequency of the multiple processing cores according to the frequency change value, the timestamp and the preset weight configuration value; adjusts the frequency and voltage of the multiple processing cores according to the adjustment order of the voltage and frequency of the multiple processing cores, as well as the core requested frequency value and the core requested voltage value of the multiple processing cores, which can enhance the flexibility of the processor in some application scenarios and improve the energy efficiency ratio of the processor.

The processor voltage and frequency adjustment method of the embodiment of the present invention can achieve the maximum balance between design cost and energy efficiency by dynamically adjusting the voltage and frequency of each processing core when the number of processor cores and the external power supply are not one-to-one corresponding. The processor voltage and frequency adjustment method of the embodiment of the present invention can support user-defined arbitration weight parameters, that is, preset weight configuration values, to provide a flexible operating mode for the processor.

Based on the above processor voltage and frequency adjustment method, an embodiment of the present invention further provides a processor voltage and frequency adjustment device, whose structural diagram is shown in FIG3 . The processor voltage and frequency adjustment device 30 includes a monitoring module 31, a processing core information acquisition module 32, an adjustment sequence determination module 33, and an adjustment module 34;

The monitoring module 31 is used to monitor the dynamic voltage and frequency adjustment request of the client;

The processing core information acquisition module 32 is used to obtain frequency change values, timestamps and preset weight configuration values of multiple processing cores corresponding to the dynamic voltage and frequency adjustment request;

The adjustment sequence determination module 33 is used to determine the adjustment sequence of the voltage and frequency of the multiple processing cores according to the frequency change value, the timestamp and the preset weight configuration value;

The adjustment module 34 is used to adjust the frequencies and voltages of the multiple processing cores according to the adjustment order of the voltages and frequencies of the multiple processing cores, and the core requested frequency values and core requested voltage values of the multiple processing cores.

For other details about how the modules in the processor voltage and frequency adjustment device 30 implement the above technical solution, please refer to the description of the processor voltage and frequency adjustment method provided in the above invention embodiment, which will not be repeated here.

Based on the above processor voltage and frequency adjustment method, an embodiment of the present invention further provides an electronic device 40, whose structural diagram is shown in FIG4 , and the electronic device 40 includes a processor 41 and a memory 42 coupled to the processor 41. The memory 42 stores a computer program, and when the computer program is executed by the processor 41, the processor 41 executes the steps of the processor voltage and frequency adjustment method in the above embodiment.

For other details about the implementation of the above technical solution by the processor 41 in the above electronic device 40, please refer to the description of the processor voltage and frequency adjustment method provided in the above invention embodiment, which will not be repeated here.

Among them, the processor 41 may be an integrated circuit chip with signal processing capabilities; the processor 41 may also be a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, wherein the general-purpose processor may be a microprocessor or the processor 41 may also be any conventional processor, etc.

The embodiment of the present invention also provides a computer-readable storage medium, the structure diagram of which is shown in FIG5 , wherein a readable computer program 51 is stored on the storage medium 50; wherein the computer program 51 can be stored in the above storage medium in the form of a software product, including several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a magnetic disk or an optical disk, a read-only memory, a random access memory, or a terminal device such as a computer, a server, a mobile phone, and a tablet.

In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional module in each embodiment of the present application can be integrated into a processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The above-mentioned integrated module can be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium.

In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of the embodiments may be implemented in the form of a computer program product.

The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website site, a computer, a server, or a data center to another website site, a computer, a server, or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a server or a data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)), etc.

The technical solution provided by the present application is introduced in detail above. The principles and implementation methods of the present application are explained by using specific examples in the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

The present application is described with reference to the flowcharts and/or block diagrams of the methods, devices and computer program products according to the present application. It should be understood that each process and/or box in the flowchart and/or block diagram, as well as the combination of the processes and/or boxes in the flowchart and/or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for implementing the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.

These computer program instructions may also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, whereby the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.

Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims (10)

1. A method for adjusting processor voltage and frequency, comprising: Monitor the client's dynamic voltage and frequency adjustment requests; Obtain frequency change values, timestamps, and preset weight configuration values of multiple processing cores corresponding to the dynamic voltage and frequency adjustment request; Determining an adjustment order of voltages and frequencies of the plurality of processing cores according to the frequency change value, the timestamp, and the preset weight configuration value; The frequencies and voltages of the multiple processing cores are adjusted according to the adjustment order of the voltages and frequencies of the multiple processing cores, and the core-requested frequency values and core-requested voltage values of the multiple processing cores. 2. The processor voltage and frequency adjustment method according to claim 1, wherein monitoring the dynamic voltage and frequency adjustment request of the client comprises monitoring the dynamic voltage and frequency adjustment requests of multiple clients; Correspondingly, before obtaining the frequency change values, timestamps and preset weight configuration values of multiple processing cores corresponding to the dynamic voltage and frequency adjustment request, it also includes determining the response order of the dynamic voltage and frequency adjustment requests of the clients according to the performance requirement modes of the multiple clients, and the performance requirement modes include hardware automatic control performance mode, low power consumption control mode, temperature control mode, power consumption control mode or operating system internal control processing core performance mode. 3. The processor voltage and frequency adjustment method according to claim 1, wherein monitoring dynamic voltage and frequency adjustment requests from multiple clients comprises: At each interval preset duration, the client's dynamic voltage and frequency adjustment request is polled once to monitor the dynamic voltage and frequency adjustment requests of multiple clients, or, after receiving the dynamic voltage and frequency adjustment request sent by the client, the monitoring of the dynamic voltage and frequency adjustment request is woken up to monitor the dynamic voltage and frequency adjustment requests of multiple clients. 4. The processor voltage and frequency adjustment method according to claim 1, wherein obtaining frequency change values of multiple processing cores corresponding to the dynamic voltage and frequency adjustment request comprises: The core-requested frequency values and current frequency values of the multiple processing cores corresponding to the dynamic voltage frequency adjustment request are obtained, and a frequency change value is obtained according to the core-requested frequency values and the current frequency values. 5. The processor voltage and frequency adjustment method according to claim 1, wherein obtaining the timestamps of the multiple processing cores corresponding to the dynamic voltage and frequency adjustment request comprises: The current time point of the core request and the time point of the last core request of the multiple processing cores corresponding to the dynamic voltage and frequency adjustment request are obtained, and the timestamp is obtained according to the current time point of the core request and the time point corresponding to the last core request. 6. The processor voltage and frequency adjustment method according to claim 1, wherein determining the adjustment order of the voltage and frequency of the plurality of processing cores according to the frequency change value, the timestamp and the preset weight configuration value comprises: An arbitration value is determined according to the frequency change value, the timestamp, the preset weight configuration value and an arbitration calculation formula, and an adjustment sequence of the voltage and frequency of the multiple processing cores is determined according to the arbitration value, wherein the arbitration calculation formula includes , wherein V is the arbitration value, weight is the preset weight configuration value, is the frequency change value, and m is the preset dimension value. 7. The processor voltage and frequency adjustment method according to claim 1, characterized in that the frequency and voltage of the multiple processing cores are adjusted according to the adjustment order of the voltage and frequency of the multiple processing cores, and the core requested frequency values and the core requested voltage values of the multiple processing cores, comprising: According to the adjustment order of the voltages and frequencies of the multiple processing cores, as well as the core-requested frequency values and core-requested voltage values of the multiple processing cores, the frequencies and voltages of the multiple processing cores are adjusted in sequence; if the core-requested voltage value of the processing core is less than the actual voltage value of the current shared voltage domain of the processing core, the voltage of the processing core is not adjusted. 8. A processor voltage and frequency adjustment device, characterized by comprising a monitoring module, a processing core information acquisition module, an adjustment sequence determination module and an adjustment module; The monitoring module is used to monitor the dynamic voltage and frequency adjustment request of the client; The processing core information acquisition module is used to obtain frequency change values, timestamps and preset weight configuration values of multiple processing cores corresponding to the dynamic voltage and frequency adjustment request; The adjustment sequence determination module is used to determine the adjustment sequence of the voltage and frequency of the multiple processing cores according to the frequency change value, the timestamp and the preset weight configuration value; The adjustment module is used to adjust the frequencies and voltages of the multiple processing cores according to the adjustment order of the voltages and frequencies of the multiple processing cores, and the core-requested frequency values and core-requested voltage values of the multiple processing cores. 9. An electronic device, comprising a memory and a processor, wherein the memory stores a computer program executable by the processor, wherein the processor implements the processor voltage and frequency adjustment method as described in any one of claims 1 to 7 when executing the computer program. 10. A computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the processor voltage and frequency adjustment method according to any one of claims 1 to 7.