CN118841053A - FPGA system based on PSRAM particles and control method and equipment thereof - Google Patents

Abstract

The present application discloses an FPGA system based on PSRAM particles and its control method and equipment, which relate to the field of integrated circuit technology. The FPGA system includes: a PSRAM controller, including: an internal bus module, an automatic training module connected to the internal bus module, and at least two single-particle channel modules; the single-particle channel module includes: an IO interface module, a write data channel and a LUT output delay module connected in sequence between the internal bus module and the IO interface module, and a read data channel and a LUT sampling delay module connected in sequence between the internal bus module and the IO interface module; at least two PSRAM particles, each PSRAM particle correspondingly connected to an IO interface module; it can realize a delay function with certain versatility in the FPGA system, and can realize mutually independent multi-channel communication, thereby reducing data congestion and improving data processing efficiency and bandwidth utilization.

Description

FPGA system based on PSRAM particles and its control method and device

Technical Field

The present application relates to the field of integrated circuit technology, and in particular to a PSRAM particle-based FPGA system and a control method and device thereof.

Background Art

At present, with the development of integrated circuits, on the one hand, Field-Programmable Gate Array (FPGA), as a semi-custom circuit in the field of application-specific integrated circuits, is widely used in various fields due to its reconfigurable, rich logic resources, and flexible input and output interfaces. On the other hand, PSRAM (Pseudo static random access memory) is also widely used in many fields due to its high data transmission rate. Based on the characteristics of FPGA and PSRAM, the combination of the two can be widely used in many fields such as image video timing control systems and industrial control systems. In ASIC chip design, the PSRAM controller can use the delay-locked loop (DLL) designed by analog engineers to delay the input sampling signal and clock, thereby achieving the effect of multi-phase sampling. There are some DLL-like primitive logic resources in FPGA. Taking Xilinx as an example, there are primitive logic resources such as IDELAY and IDDR. Using these resources can partially realize the DLL function. However, not all selected FPGA chips have suitable delay resources to use. Using primitive logic resources to realize the delay function has certain limitations. In addition, in an FPGA system with multiple PSRAM particles, when multiple PSRAM particles return different data, the data is not synchronized, which easily causes data congestion, and the PSRAM controller needs to wait for different numbers of clock cycles to receive data, resulting in low bandwidth utilization.

Summary of the invention

The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes an FPGA system based on PSRAM particles and a control method and device thereof, which can realize a delay function with certain versatility in the FPGA system based on a LUT lookup table, and can realize independent multi-channel communication between a PSRAM controller and multiple PSRAM particles, thereby reducing data congestion and improving data processing efficiency and bandwidth utilization.

In a first aspect, an embodiment of the present application provides an FPGA system based on PSRAM particles, including:

The PSRAM controller comprises: an internal bus module, an automatic training module communicatively connected to the internal bus module, and at least two single-grain channel modules;

The single particle channel module includes: an IO interface module, a write data channel and a LUT output delay module connected in sequence between the internal bus module and the IO interface module, and a read data channel and a LUT sampling delay module connected in sequence between the internal bus module and the IO interface module;

At least two PSRAM particles, each of which is correspondingly connected to one of the IO interface modules for communication; the number of the PSRAM particles is equal to the number of the single-particle channel modules;

The PSRAM controller is used to:

The automatic training module is started to perform phase coarse adjustment processing and phase fine adjustment processing to determine the target sampling phase; after the phase training is completed, the internal bus module responds to the received data read and write request, and determines the PSRAM target address of at least one PSRAM particle to be accessed from the data read and write request; the data read and write request is subjected to read and write arbitration to determine the type of operation performed on the PSRAM particle to be accessed; the type of operation includes: read operation and write operation; according to the type of operation, the PSRAM particle indicated by the PSRAM target address is operated with the target sampling phase through the delay processing of the corresponding single-particle channel module; the delay processing includes: the output delay processing performed by the LUT output delay module in the write operation, and the sampling delay processing performed by the LUT sampling delay module in the read operation.

In a second aspect, an embodiment of the present application provides a control method for an FPGA system based on PSRAM particles, which is applied to an FPGA system based on PSRAM particles as described in any one of the embodiments of the first aspect; the FPGA system comprises: a PSRAM controller, comprising: an internal bus module, an automatic training module communicatively connected to the internal bus module, and at least two single-particle channel modules; the single-particle channel module comprises: an IO interface module, a LUT output delay module, and a LUT sampling delay module; at least two PSRAM particles;

The control method comprises:

Starting the automatic training module to perform phase coarse adjustment processing and phase fine adjustment processing to determine the target sampling phase;

After the phase training is completed, the internal bus module responds to the received data read and write request and determines the PSRAM target address of at least one PSRAM particle to be accessed from the data read and write request;

Performing read and write arbitration on the data read and write request to determine the type of operation to be performed on the PSRAM particle to be accessed; the type of operation includes: a read operation and a write operation;

According to the type of the operation, the PSRAM particle indicated by the PSRAM target address is operated with the target sampling phase through the delay processing of the corresponding single-particle channel module; the delay processing includes: the output delay processing performed by the LUT output delay module in the write operation, and the sampling delay processing performed by the LUT sampling delay module in the read operation.

In a third aspect, an embodiment of the present application provides an electronic device, characterized in that it includes an FPGA system based on PSRAM particles as described in any one of the embodiments of the first aspect.

The embodiment of the present application includes: an FPGA system based on PSRAM particles includes: a PSRAM controller and at least two PSRAM particles, the PSRAM controller includes: an internal bus module, an automatic training module connected to the internal bus module, and at least two single-particle channel modules; the single-particle channel module includes: an IO interface module, a write data channel and a LUT output delay module connected in sequence between the internal bus module and the IO interface module, and a read data channel and a LUT sampling delay module connected in sequence between the internal bus module and the IO interface module; each PSRAM particle is correspondingly connected to an IO interface module for communication; the number of PSRAM particles is equal to that of the single-particle channel modules; the DLL or DELAY logic resources of the FPGA chip are not used, but the LUT output delay module and the LUT sampling delay module are constructed based on the LUT lookup table to realize the delay function in the FPGA system, which has It has certain versatility; in the process of PFGA system operation, using PSRAM controller, first, start the automatic training module to perform phase coarse adjustment processing and phase fine adjustment processing to determine the target sampling phase; then, after the phase training is completed, the internal bus module responds to the received data read and write request, and determines the PSRAM target address of at least one PSRAM particle to be accessed from the data read and write request; then, read and write arbitration is performed on the data read and write request to determine the type of operation to be performed on the PSRAM particle to be accessed; the type of operation includes: read operation and write operation; finally, according to the type of operation, the PSRAM particle indicated by the PSRAM target address is operated with the target sampling phase through the delay processing of the corresponding single-particle channel module; the delay processing includes: output delay processing performed by the LUT output delay module in the write operation, and sampling delay processing performed by the LUT sampling delay module in the read operation. By setting the single-particle channel module, independent multi-channel communication is realized between the PSRAM controller and multiple PSRAM particles, which reduces data congestion and improves data processing efficiency and bandwidth utilization. That is to say, the embodiment of the present application can implement a delay function with a certain degree of universality in the FPGA system based on the LUT lookup table, and can realize independent multi-channel communication between the PSRAM controller and multiple PSRAM particles, thereby reducing data congestion and improving data processing efficiency and bandwidth utilization.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of the structure of an FPGA system based on PSRAM particles provided by an embodiment of the present application;

FIG2 is a schematic diagram of the overall structure of an FPGA system based on PSRAM particles provided by an embodiment of the present application;

FIG3 is a schematic diagram of the specific structure of multiple single particle channel modules provided by one embodiment of the present application;

FIG4 is a schematic diagram of the specific structure of a LUT output delay module provided by an embodiment of the present application;

FIG5 is a schematic diagram of the specific structure of a LUT sampling delay module provided by an embodiment of the present application;

FIG. 6 is a flowchart showing the steps of a control method for an FPGA system based on PSRAM particles provided in one embodiment of the present application.

DETAILED DESCRIPTION

In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments.

It should be understood that in the description of the present application, the orientation descriptions, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

It should be noted that although a logical order is shown in the flowchart in the description of the present application, in some cases, the steps shown or described may be performed in an order different from that in the flowchart. In the description of the present application, a number of means one or more, and a plurality of means two or more. The description of "first" and "second" is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

First, some terms used in this application are explained:

PSRAM: refers to pseudo-static random access memory, the full name is Pseudostatic Random Access Memory. PSRAM is a memory that combines the SRAM (static random access memory) interface protocol and the DRAM (dynamic random access memory) architecture.

IDDR: IDDR (Input Double Data Rate) is a primitive used in FPGA design, mainly used for high-speed data communication interfaces. IDDR can convert a single-bit double-edge sampled input into a double-bit single-edge sampled output.

CPU: The full name is Central Processing Unit, which is one of the core components of computer hardware.

DMA: The full name is Direct Memory Access, which is a data transmission method in a computer system.

The present application discloses an FPGA system based on PSRAM particles and its control method and equipment. The FPGA system includes: a PSRAM controller, including: an internal bus module, an automatic training module connected to the internal bus module, and at least two single-particle channel modules; the single-particle channel module includes: an IO interface module, a write data channel and a LUT output delay module connected in sequence between the internal bus module and the IO interface module, and a read data channel and a LUT sampling delay module connected in sequence between the internal bus module and the IO interface module; at least two PSRAM particles, each PSRAM particle correspondingly connected to an IO interface module; a delay function with certain versatility can be realized in the FPGA system, and independent multi-channel communication can be realized, thereby reducing data congestion and improving data processing efficiency and bandwidth utilization.

The embodiments of the present application are further described below in conjunction with the accompanying drawings.

As shown in FIG. 1 , a PSRAM particle-based FPGA system includes: a PSRAM controller and at least two PSRAM particles.

The PSRAM controller includes: an internal bus module, an automatic training module connected to the internal bus module for communication, and at least two single-grain channel modules.

The single-particle channel module includes: an IO interface module, a write data channel and a LUT output delay module sequentially connected between the internal bus module and the IO interface module, and a read data channel and a LUT sampling delay module sequentially connected between the internal bus module and the IO interface module.

At least two PSRAM particles, each PSRAM particle is correspondingly connected to an IO interface module for communication; the number of PSRAM particles is equal to the number of single-particle channel modules.

The automatic training module is used to perform phase training, that is, to perform phase coarse adjustment processing and phase fine adjustment processing to determine the target sampling phase for reading and writing.

The internal bus module is used to: in response to receiving a data read and write request, access the PSRAM particles individually through the single-particle channel module, which is conducive to reducing data congestion and improving the data processing efficiency and bandwidth utilization of the FPGA system.

The PSRAM controller is used to: start the automatic training module to perform phase coarse adjustment processing and phase fine adjustment processing to determine the target sampling phase; after the phase training is completed, respond to the received data read and write request through the internal bus module, and determine the PSRAM target address of at least one PSRAM particle to be accessed from the data read and write request; perform read and write arbitration on the data read and write request to determine the type of operation to be performed on the PSRAM particle to be accessed; the types of operations include: read operation and write operation; according to the type of operation, the PSRAM particle indicated by the PSRAM target address is operated with the target sampling phase through the delay processing of the corresponding single-particle channel module; the delay processing includes: output delay processing performed by the LUT output delay module in the write operation, and sampling delay processing performed by the LUT sampling delay module in the read operation.

According to the PSRAM particle-based FPGA system provided by the embodiment of the first aspect of the present application, the DLL or DELAY logic resources of the FPGA chip are not used, but the LUT output delay module and the LUT sampling delay module are constructed based on the LUT lookup table to realize the delay function in the FPGA system, which has a certain versatility; by setting a single-particle channel module, independent multi-channel communication is realized between the PSRAM controller and multiple PSRAM particles, thereby reducing data congestion and improving data processing efficiency and bandwidth utilization.

As shown in Figure 2, according to some embodiments of the present application, the FPGA system also includes: a standard bus interface; the PSRAM controller also includes: a bus conversion module and a register configuration module; one end of the standard bus interface is connected to an external device; the other end of the standard bus interface is communicated with the register configuration module through the APB bus and is communicated with the bus conversion module through the AXI bus; the bus conversion module is connected to the internal bus module.

Specifically, the external devices connected to the standard bus interface include but are not limited to: a CPU and a DMA device.

It is understandable that the present application encapsulates the entire PSRAM particle-based FPGA system into a standard bus interface, namely the AXI bus and the APB bus. Then the peripherals directly cooperate with the CPU + other verification IPs that need to access the external storage space to build a complete FPGA platform.

Specifically, the bus conversion module is used to: receive the initialization configuration instruction issued by the CPU, and send the controller initialization instruction to the register configuration module through the APB bus, so that the register configuration module completes the initialization processing of the PSRAM controller in response to the initialization configuration instruction. The bus conversion module is used to: receive the data read and write request issued by the external device, and send the data read and write request to the internal bus module through the AXI bus, so that the internal bus module responds to the data read and write request and accesses the PSRAM particles.

Specifically, the register configuration module is used to initialize and configure the PSRAM controller, laying a foundation for the subsequent normal operation of the PSRAM controller.

As shown in FIG. 2 , according to some embodiments of the present application, the internal bus module includes: a plurality of read-write controllers, each of which is communicatively connected to a single-grain channel module; and a plurality of storage units, each of which is communicatively connected to a read-write controller.

Among them, the storage unit is used to cache the data to be written to the PSRAM particles and the read-back data read from the PSRAM particles; the read-write controller is used to respond to the received data read and write requests, split the data to be written according to the PSRAM target address and store it in the storage unit, waiting to be written to the corresponding PSRAM particles; and sample, splice and reorganize the read-back data according to the PSRAM target address and store it in the storage unit to restore it to normal data.

It is understandable that the internal BUS module includes multiple read-write controllers that can convert the AXI bus into multiple independently accessible read-write controls. When reading the data of the PSRAM particles, due to the self-refresh of the PSRAM particles, different PSRAM particles have different lengths of time from receiving the reading request issued by the read-write controller to returning the read data; for the read-write controller, after different numbers of clock cycles, the data returned by different PSRAM particles are received. Therefore, the embodiment of the present application sets a storage unit in the internal bus module, and the read-write controller splits the data in the write operation and sends it to the storage unit according to the PSRAM target address of the PSRAM particle to be accessed, or splices the read-back data and sends it to the storage unit in the read operation. When the data of one PSRAM particle returns slowly, it will not affect the access to another PSRAM particle. By realizing independent data reading and writing for multiple PSRAM particles, the waste of clock cycles caused by the asynchronous return of data by PSRAM particles can be reduced, thereby achieving the purpose of improving bandwidth utilization.

As shown in FIG2 , in some embodiments, each PSRAM particle is connected to the IO interface module via a control line and a data line. The control line is used to transmit the CS signal (chip select signal), CLK signal (clock signal), CLKN signal (clock inversion signal), and RSTN signal (reset signal) for controlling the dual PSRAM particles. The data line is used to transmit the DQ signal, DQS signal, and DM signal of the dual PSRAM particles.

As shown in Figure 3, the single-particle channel module also includes: a write command channel. The write command channel is used to receive a write command signal and an address signal corresponding to the write command signal, and in response to the received write command signal, generates a write enable signal corresponding to the write command signal, and sends the write enable signal to the PSRAM particle.

Furthermore, the LUT output delay module and the LUT sampling delay module provided in the embodiments of the present application are further described.

As shown in Figure 4, Figure 4 is a specific structural diagram of the LUT output delay module provided by an embodiment of the present application; according to some embodiments of the present application, the LUT output delay module includes: a first trigger, a data delay unit, and a clock delay unit. Among them, the output end of the first D trigger is connected to the IO interface module; the DQ input end of the data delay unit is connected to the write data channel, and the output end of the data delay unit is connected to the D end of the first D trigger; the clock delay unit, the DQS input end of the clock delay unit is connected to the write data channel, and the output end of the clock delay unit is connected to the CLK end of the first D trigger.

According to some embodiments of the present application, a data delay unit includes: a first multiplexer and an N-stage LUT delay structure; wherein the output end of the first multiplexer is connected to the D end of the D flip-flop; the N-stage LUT delay structure includes: N-1 LUT lookup tables, the input end of each LUT lookup table and the output end of the last LUT lookup table are connected to the input end of the first multiplexer.

It is understandable that in the data delay unit, the LUT unit delay of a single LUT lookup table is fixed and the same, and the maximum fixed delay length that the data delay unit can achieve is determined by the N-level LUT delay structure, where N is a natural number. Assuming that the delay of each LUT lookup table is t, the maximum fixed delay length of the data delay unit is: Nt. It is understandable that by selecting the first multiplexer of the data delay unit, the delay gear can be adjusted to determine the fixed delay of the data delay unit. For example, the fixed delay corresponding to the 0-gear delay is 0, the fixed delay corresponding to the 1-gear delay is t, the fixed delay corresponding to the 2-gear delay is 2t, and so on.

According to some embodiments of the present application, the clock delay unit includes: a second multiplexer and an M-level LUT clock delay structure; wherein the output end of the second multiplexer is connected to the CLK end of the D flip-flop; the M-level LUT clock delay structure includes: M-1 LUT lookup tables, and the input end of each LUT lookup table and the output end of the last LUT lookup table are connected to the input end of the second multiplexer.

It is understandable that in the clock delay unit, the LUT unit delay of a single LUT lookup table is fixed, and the maximum fixed delay length that the clock delay unit can achieve is determined by the M-level LUT delay structure, where M is a natural number. Assuming that the delay of each LUT lookup table is t, the maximum fixed delay length of the clock delay unit is: Mt. It is understandable that by selecting the second multiplexer of the clock delay unit, the delay gear can be adjusted to determine the fixed delay of the clock delay unit. For example, the fixed delay corresponding to the 0-gear delay is 0, the fixed delay corresponding to the 1-gear delay is t, the fixed delay corresponding to the 2-gear delay is 2t, and so on.

Based on this structure, in the phase training stage, after the automatic training module completes the coarse phase adjustment processing, the phase can be fine-tuned to determine the optimal write phase by adjusting the N-level LUT delay structure and the M-level LUT delay structure in the phase fine adjustment processing; thereby, the delay function can be realized in the process of writing data, and data can be written to the PSRAM particles with the optimal write phase.

The embodiment of the present application constructs a LUT output delay module based on the LUT lookup table without using the DLL or DELAY logic resources of the FPGA chip, and implements the delay function in the write operation of the FPGA controller, which has a certain degree of versatility.

As shown in Figure 5, Figure 5 is a specific structural diagram of a LUT sampling delay module provided by an embodiment of the present application; according to some embodiments of the present application, the LUT sampling delay module includes: a second D flip-flop, a data delay unit, and a clock delay unit. Among them, the output end of the second D flip-flop is connected to the read data channel; the data delay unit, the DQ input end of the data delay unit is connected to the IO interface module, and the output end of the data delay unit is connected to the D end of the second D flip-flop; the DQS input end of the clock delay unit is connected to the IO interface module, and the output end of the clock delay unit is connected to the CLK end of the second D flip-flop.

According to some embodiments of the present application, a data delay unit includes: a first multiplexer and an N-stage LUT delay structure; wherein the output end of the first multiplexer is connected to the D end of the D flip-flop; the N-stage LUT delay structure includes: N-1 LUT lookup tables, the input end of each LUT lookup table and the output end of the last LUT lookup table are connected to the input end of the first multiplexer.

According to some embodiments of the present application, the clock delay unit includes: a second multiplexer and an M-level LUT clock delay structure; wherein the output end of the second multiplexer is connected to the CLK end of the D flip-flop; the M-level LUT clock delay structure includes: M-1 LUT lookup tables, and the input end of each LUT lookup table and the output end of the last LUT lookup table are connected to the input end of the second multiplexer.

It can be understood that the data delay unit and the clock delay unit in the LUT sampling delay module have the same structure and function as the data delay unit and the clock delay unit in the LUT output delay module, and the specific structure and corresponding functions of the data delay unit and the clock delay unit in the LUT sampling delay module are not repeated here.

Based on this structure, in the phase training stage, after the automatic training module completes the coarse phase adjustment processing, the phase can be fine-tuned to determine the optimal read phase by adjusting the N-level LUT delay structure and the M-level LUT delay structure in the phase fine adjustment processing; thereby, the delay function can be realized in the process of writing data, and data can be sampled from the PSRAM particles with the optimal read phase.

The embodiment of the present application constructs a LUT sampling delay module based on a LUT lookup table without using the DLL or DELAY logic resources of the FPGA chip, and implements a delay function in the read operation of the FPGA controller, which has a certain degree of versatility.

It is understandable that, taking input sampling as an example, if the IDELAY+IDDR primitive method of the ready-made resources inside the FPGA is used, the data needs to be spliced in the IDDR, and a faster high-multiple clock is required for sampling, which will cause the PSRAM controller interface frequency to not be too high. The embodiment of the present application uses a pure LUT method, and uses the fixed delay of the LUT lookup table to delay the DQS signal, so as to achieve the purpose of latching data in the current cycle. Compared with the IDELAY+IDDR method, the method of implementing the delay function using a pure LUT method in the present application can save at least 2 to 3 cycles, thereby improving data processing efficiency and bandwidth utilization. In addition, for some FPGA chips that do not have delayed sampling resources such as IDELAY and IDDR inside, the delay function based on the pure LUT method provided by the embodiment of the present application can be implemented. Therefore, the delay function provided by the embodiment of the present application is universal.

It is understandable that since the DQ signal and the DQS signal are aligned when they are sent from the PSRAM particles, the DQS signal needs to be delayed so that the edge of the DQS signal is aligned with the center of the DQ data for sampling (i.e., center sampling). Therefore, it is necessary to set a reasonable number of LUT levels and set the delay value of each level. Since the position of the LUT in the FPGA is fixed, the position of each LUT in the FPGA needs to be specified and cannot be optimized. The physical position of each LUT needs to be constrained in the FPGA layout and routing tool so that the LUT unit delay of each LUT lookup table is basically the same, thereby achieving the purpose of equivalent delay at each level and realizing center sampling.

It is understandable that due to different manufacturing processes of FPGA chips, the unit LUT delay is also different. Therefore, this application does not make specific restrictions on the delay value of a single LUT lookup table in the data delay unit.

It should be noted that in the embodiment of the present application, the number of levels (ie, N) of the N-level LUT delay structure and the number of levels (ie, M) of the M-level LUT clock delay structure can be determined according to the actual PSRAM operating frequency and the LUT unit delay; the number of levels referred to here refers to the number of signals connected to the multiplexer. For example, if the PSRAM operating frequency of the PSRAM particle is 100M (cycle 10ns), then the half cycle of the PSRAM operating frequency is 5ns. When sampling data, the DQ signal is sampled based on the DQS signal. When the edge of the DQS signal is aligned with the center of the DQ signal, the read-write controller samples the data at this moment to achieve center sampling. Therefore, it is necessary to delay the DQS signal by 2.5ns through the M-level LUT delay structure. Assuming that the LUT unit delay is 0.5ns, 2.5/0.5=5 LUT lookup tables are required. Therefore, in this case, at least 6 levels of delay sampling are required to meet the center sampling condition. In setting the M-level LUT delay structure, 5 LUT lookup tables are required to achieve a 6-level delay structure.

The embodiment of the present application utilizes the LUT delay structure to implement data sampling and latching in the current cycle, thereby saving the number of sampling clock cycles and reducing the total number of clock cycles for a single data read, thereby improving bandwidth utilization.

Those skilled in the art will appreciate that the system structure shown in the figure does not constitute a limitation on the embodiments of the present application, and may include more or fewer components than shown in the figure, or a combination of certain components, or a different arrangement of components.

The system embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

Those skilled in the art will appreciate that the system architecture and application scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of the system architecture and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are equally applicable to similar technical problems.

Based on the above system structure, various embodiments of the control method of the FPGA system based on PSRAM particles of the present application are proposed below.

In the second aspect, as shown in FIG6 , the control method of the FPGA system based on PSRAM particles can be applied to the FPGA system based on PSRAM particles as shown in FIG1 , wherein the FPGA system includes: a PSRAM controller, including: an internal bus module, an automatic training module connected to the internal bus module, and at least two single-particle channel modules; the single-particle channel module includes: an IO interface module, a LUT output delay module, and a LUT sampling delay module; and at least two PSRAM particles. The control method may include but is not limited to steps S110 to S140.

Step S110: start the automatic training module to perform phase coarse adjustment processing and phase fine adjustment processing to determine the target sampling phase.

Step S120: After the phase training is completed, the internal bus module responds to the received data read/write request and determines the PSRAM target address of at least one PSRAM particle to be accessed from the data read/write request.

Step S130: performing read/write arbitration on the data read/write request to determine the type of operation to be performed on the PSRAM particle to be accessed; the types of operation include: read operation and write operation.

Step S140: According to the type of operation, the PSRAM particle indicated by the PSRAM target address is operated with the target sampling phase through the delay processing of the corresponding single-particle channel module; the delay processing includes: the output delay processing performed by the LUT output delay module in the write operation, and the sampling delay processing performed by the LUT sampling delay module in the read operation.

Through step S110 to step S140, during the operation of the PFGA system, the PSRAM controller is used to first start the automatic training module to perform phase coarse adjustment processing and phase fine adjustment processing to determine the target sampling phase; then, after the phase training is completed, the internal bus module responds to the received data read and write request, and determines the PSRAM target address of at least one PSRAM particle to be accessed from the data read and write request; then, the data read and write request is read and written arbitration is performed to determine the type of operation to be performed on the PSRAM particle to be accessed; the type of operation includes: read operation and write operation; finally, according to the type of operation, the PSRAM particle indicated by the PSRAM target address is operated with the target sampling phase through the delay processing of the corresponding single-particle channel module; the delay processing includes: output delay processing performed by the LUT output delay module in the write operation, and sampling delay processing performed by the LUT sampling delay module in the read operation. By setting the single-particle channel module, independent multi-channel communication is realized between the PSRAM controller and multiple PSRAM particles, which reduces data congestion and improves data processing efficiency and bandwidth utilization. Therefore, the embodiment of the present application can implement a delay function with a certain degree of universality in the FPGA system based on the LUT lookup table, and can realize independent multi-channel communication between the PSRAM controller and multiple PSRAM particles, thereby reducing data congestion and improving data processing efficiency and bandwidth utilization.

Specifically, before step S110, the control method further includes: enabling the register configuration module to receive an initialization configuration instruction sent by the CPU through the APB bus, and completing initialization processing on the PSRAM controller in response to the initialization configuration instruction.

Specifically, step S110 is further described, and step S110 includes: according to the PSRAM protocol format, starting the automatic training module to first perform a read phase coarse adjustment process; the read phase coarse adjustment process includes: through the binary method, quickly coarsely adjust the PSRAM read phase, and then control the automatic training module and the LUT sampling delay module to continue the LUT phase fine adjustment process to determine the optimal read phase; after the automatic training module completes the confirmation of the optimal read phase, the training continues; perform a write phase coarse adjustment process; the write phase coarse adjustment process includes: through the binary method, quickly coarsely adjust the PSRAM write phase, and then control the automatic training module and the LUT output delay module to continue the LUT phase fine adjustment process to determine the optimal write phase; after obtaining the optimal read phase and the optimal write phase, initiate a completion interrupt to end the phase training.

Specifically, when quickly locating the phase, first perform a coarse adjustment, first fix all DQ signals to the same phase, then change the DQS phase, perform data read and write comparison tests based on different phases, and preliminarily determine the DQS phase when the read and write data are consistent; then fine-tune the LUT phase of the DQ signal based on the selected DQS phase, perform data read and write comparison tests based on different LUT phases, and determine the optimal data sampling phase when the read and write data are consistent. The optimal read phase and the optimal write phase can be determined by this method of first coarse adjustment and then fine adjustment.

It can be understood that in the phase training process, the use of binary division for phase coarse adjustment means: traversing all LUT levels of the DQS signal input terminal and the DQ signal input terminal, quickly positioning by binary division, first using a test phase to perform data read and write comparison test to determine whether the candidate phase is feasible, if not feasible, then taking half of the test phase to continue the data read and write comparison test to preliminarily determine the phase, and further adjusting the LUT sampling delay module and the LUT output delay module gear by gear to perform data read and write comparison test until the optimal read phase and the optimal write phase are determined. Or you can directly traverse one by one starting from phase 0.

Specifically, step S120 is further explained, and step S120 includes: after the phase training is completed, the bus conversion module receives a data read and write request initiated by an external device through the AXI bus, and sends the data read and write request to the internal bus module; the internal bus module responds to the received data read and write request, and determines the PSRAM target address of at least one PSRAM particle to be accessed from the data read and write request.

Specifically, step S130 is further described. It can be understood that the AXI bus has a read-write parallel function. However, an operation performed on a PSRAM particle can only be a read operation or a write operation. In this way, it is necessary to arbitrate the data read and write requests from the AXI through the read-write controller of the internal bus module, and determine whether to perform a read operation or a write operation first when the read and write data arrive at the same time. In this way, the type of operation to be performed on the PSRAM particle to be accessed is determined through step S130, so as to determine whether to use the write data channel or the read data channel in the single-particle channel module.

According to some embodiments of the present application, step S140 is further described, and the target sampling phase includes: an optimal read phase and an optimal write phase; step S140: according to the type of operation, through the delay processing of the corresponding single-grain channel module, the PSRAM grain indicated by the PSRAM target address is operated with the target sampling phase, including but not limited to steps S141 to S142.

Step S141: When the operation type is a write operation, the internal bus module sends a first data transmission signal to the corresponding single-grain channel module according to the PSRAM target address. After the first data transmission signal is transmitted by the write data channel and delayed by the LUT output delay module, the data to be written in the first data transmission signal is written into the PSRAM grain indicated by the PSRAM target address at the optimal write phase.

Step S142: When the operation type is a read operation, the internal bus module sends a read request to the PSRAM target address, so that the PSRAM particle indicated by the PSRAM target address responds to the read request and returns a second data transmission signal to the corresponding single-particle channel module. After the second data transmission signal is delayed by the LUT sampling delay module and transmitted by the read data channel, the data to be read in the second data transmission signal is read by the internal bus module at the optimal read phase.

Specifically, during the process of writing data, the read-write controller also splits the data to be written according to the PSRAM target address and stores it in the storage unit to be written into the corresponding PSRAM particles.

Specifically, in the process of reading data, the read-write controller also samples the read-back data according to the PSRAM target address, and stores it in the storage unit after splicing and reorganization, thereby restoring it to normal data.

Through step S141 to step S142, the read/write controller of the internal bus module can access the PSRAM particle indicated by the PSRAM target address through the corresponding single-particle channel module based on the type of operation determined by arbitration, thereby achieving independent data read/write control.

In the third aspect, an embodiment of the present application provides an electronic device, including an FPGA system based on PSRAM particles provided in the embodiment of the first aspect; it is capable of implementing a delay function with a certain degree of universality in the FPGA system based on a LUT lookup table, and can realize independent multi-channel communication between a PSRAM controller and multiple PSRAM particles, thereby reducing data congestion and improving data processing efficiency and bandwidth utilization.

In summary, the embodiments of the present application have the following beneficial effects: First, a PSRAM-based FPGA prototype verification system is proposed, which provides the FPGA verification system with low cost but higher bandwidth; second, a LUT delay structure is used to sample data at the center of the current cycle and latch it for later transmission, thereby reducing the consumption of the number of data sampling clock cycles. Third, the FPGA system does not use the DLL or DELAY logic resources of the FPGA chip to achieve a universal delay function; fourth, the read and write controllers of multiple PSRAM particles are independent, eliminating the impact of asynchronous return of dual PSRAM data due to PSRAM particle self-refresh, thereby improving system bandwidth utilization.

The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the above-mentioned implementation mode. Technical personnel familiar with the field can also make various equivalent deformations or substitutions without violating the spirit of the present application. These equivalent deformations or substitutions are all included in the scope defined by the present application.

Claims (10)

1. A PSRAM particle-based FPGA system, comprising: The PSRAM controller comprises: an internal bus module, an automatic training module communicatively connected to the internal bus module, and at least two single-grain channel modules; The single particle channel module includes: an IO interface module, a write data channel and a LUT output delay module connected in sequence between the internal bus module and the IO interface module, and a read data channel and a LUT sampling delay module connected in sequence between the internal bus module and the IO interface module; At least two PSRAM particles, each of which is correspondingly connected to one of the IO interface modules for communication; the number of the PSRAM particles is equal to the number of the single-particle channel modules; The PSRAM controller is used to: The automatic training module is started to perform phase coarse adjustment processing and phase fine adjustment processing to determine the target sampling phase; after the phase training is completed, the internal bus module responds to the received data read and write request, and determines the PSRAM target address of at least one PSRAM particle to be accessed from the data read and write request; the data read and write request is subjected to read and write arbitration to determine the type of operation performed on the PSRAM particle to be accessed; the type of operation includes: read operation and write operation; according to the type of operation, the PSRAM particle indicated by the PSRAM target address is operated with the target sampling phase through the delay processing of the corresponding single-particle channel module; the delay processing includes: the output delay processing performed by the LUT output delay module in the write operation, and the sampling delay processing performed by the LUT sampling delay module in the read operation. 2. The FPGA system based on PSRAM particles according to claim 1, characterized in that the LUT output delay module comprises: A first D flip-flop, wherein an output end of the first D flip-flop is connected to the IO interface module; A data delay unit, wherein a DQ input end of the data delay unit is connected to the write data channel, and an output end of the data delay unit is connected to a D end of the first D flip-flop; A clock delay unit, wherein a DQS input end of the clock delay unit is connected to the write data channel, and an output end of the clock delay unit is connected to a CLK end of the first D flip-flop. 3. The FPGA system based on PSRAM particles according to claim 1, characterized in that the LUT sampling delay module comprises: A second D flip-flop, wherein an output terminal of the second D flip-flop is connected to the read data channel; A data delay unit, wherein a DQ input end of the data delay unit is connected to the IO interface module, and an output end of the data delay unit is connected to a D end of the second D flip-flop; A clock delay unit, wherein a DQS input end of the clock delay unit is connected to the IO interface module, and an output end of the clock delay unit is connected to a CLK end of the second D flip-flop. 4. The FPGA system based on PSRAM particles according to any one of claims 2 or 3, characterized in that the data delay unit comprises: A first multiplexer, wherein an output terminal of the first multiplexer is connected to a D terminal of a D flip-flop; The N-stage LUT delay structure includes: N-1 LUT lookup tables, the input end of each LUT lookup table and the output end of the last LUT lookup table are connected to the input end of the first multiplexer. 5. The FPGA system based on PSRAM particles according to any one of claims 2 or 3, characterized in that the clock delay unit comprises: A second multiplexer, wherein an output terminal of the second multiplexer is connected to a CLK terminal of the D flip-flop; The M-level LUT clock delay structure includes: M-1 LUT lookup tables, the input end of each LUT lookup table and the output end of the last LUT lookup table are connected to the input end of the second multiplexer. 6. The FPGA system based on PSRAM particles according to claim 1, characterized in that the internal bus module comprises: A plurality of read-write controllers, each of which is communicatively connected to one of the single-particle channel modules; A plurality of storage units, each of the storage units is communicatively connected to one of the read-write controllers. 7. The FPGA system based on PSRAM particles according to claim 1, characterized in that the FPGA system further comprises: a standard bus interface; the PSRAM controller further comprises: a bus conversion module and a register configuration module; One end of the standard bus interface is connected to an external device; the other end of the standard bus interface is connected to the register configuration module via an APB bus and to the bus conversion module via an AXI bus; the bus conversion module is connected to the internal bus module. 8. A control method for an FPGA system based on PSRAM particles, characterized in that it is applied to the FPGA system based on PSRAM particles as described in any one of claims 1 to 7; the FPGA system comprises: a PSRAM controller, comprising: an internal bus module, an automatic training module communicatively connected to the internal bus module, and at least two single-particle channel modules; the single-particle channel module comprises: an IO interface module, a LUT output delay module, and a LUT sampling delay module; at least two PSRAM particles; The control method comprises: Starting the automatic training module to perform phase coarse adjustment processing and phase fine adjustment processing to determine the target sampling phase; After the phase training is completed, the internal bus module responds to the received data read and write request and determines the PSRAM target address of at least one PSRAM particle to be accessed from the data read and write request; Performing read and write arbitration on the data read and write request to determine the type of operation to be performed on the PSRAM particle to be accessed; the type of operation includes: a read operation and a write operation; According to the type of the operation, the PSRAM particle indicated by the PSRAM target address is operated with the target sampling phase through the delay processing of the corresponding single-particle channel module; the delay processing includes: the output delay processing performed by the LUT output delay module in the write operation, and the sampling delay processing performed by the LUT sampling delay module in the read operation. 9. The control method of the FPGA system based on PSRAM particles according to claim 8, characterized in that the target sampling phase includes: an optimal read phase and an optimal write phase; according to the type of the operation, the delay processing of the corresponding single-particle channel module is performed to operate the PSRAM particle indicated by the PSRAM target address with the target sampling phase, comprising: When the type of the operation is a write operation, the internal bus module sends a first data transmission signal to the corresponding single-grain channel module according to the PSRAM target address, and after the first data transmission signal is transmitted by the write data channel and delayed by the LUT output delay module, the data to be written in the first data transmission signal is written into the PSRAM grain indicated by the PSRAM target address at the optimal write phase; When the type of operation is a read operation, the internal bus module sends a read request to the PSRAM target address, so that the PSRAM particle indicated by the PSRAM target address responds to the read request and returns a second data transmission signal to the corresponding single-particle channel module. After the second data transmission signal is delayed by the LUT sampling delay module and transmitted by the read data channel, the data to be read in the second data transmission signal is read by the internal bus module at the optimal read phase. 10. An electronic device, characterized by comprising the FPGA system based on PSRAM particles as claimed in any one of claims 1 to 7.