CN118826720A - A power semiconductor device driving circuit - Google Patents

Abstract

A power semiconductor device driving circuit includes: a driving current generating circuit, a pulling capacity adjusting circuit, and a power semiconductor device, wherein the driving current generating circuit has an input end connected to an external driving voltage, and an output end connected to the gate of the power semiconductor device, to provide a driving current for the power semiconductor device; the pulling capacity adjusting circuit has an input end connected to an external driving voltage and the gate of the power semiconductor device, respectively, and an output end connected to the gate of the power semiconductor device, to enhance the pull-down capability of the gate voltage of the power semiconductor device or/and weaken the pull-up capability of the gate voltage of the power semiconductor device. The power semiconductor device driving circuit of the present application can improve the switching speed of the working state of the power semiconductor device, and can also ensure the stability and reliability of the working state of the power semiconductor device.

Description

A power semiconductor device driving circuit

Technical Field

The present application relates to the technical field of electronic circuits, and in particular to a power semiconductor device driving circuit.

Background Art

In the prior art, power semiconductor devices are used as switching devices in various circuits (such as H-bridge circuits), and the circuit is turned off by turning on and off the power semiconductor devices.

In some circuits, there are certain requirements for the on and off time of power semiconductor devices (the speed of opening and closing the circuit). Some products can usually allow customers to set the opening and closing speed according to actual needs. That is to say, in the power semiconductor device driving circuit, the pull-up circuit and the pull-down circuit are set with a threshold. According to the threshold, the customer can set the opening and closing speed very small or very large. When the customer sets it very small, the power semiconductor device closes very slowly, and the pull-down ability is still very weak even after closing. At this time, if the output of the power semiconductor device is disturbed and a sudden pull-up is generated, the power semiconductor device will be opened and cause a short circuit when the pull-down ability of the driving circuit is very weak, causing safety problems.

Summary of the invention

In order to address the deficiencies in the prior art, the purpose of the present application is to provide a power semiconductor device driving circuit that can automatically adjust the pull-up and pull-down capabilities of the gate of the power semiconductor device, thereby increasing the switching speed of the power semiconductor device and ensuring the reliability of the power semiconductor device in the on or off state.

To achieve the above-mentioned purpose, the present application provides a power semiconductor device driving circuit, comprising: a driving current generating circuit, a pulling capacity adjusting circuit, and a power semiconductor device, wherein:

The driving current generating circuit has an input end connected to an external driving voltage and an output end connected to the gate of the power semiconductor device, so as to provide a driving current for the power semiconductor device;

The pulling capacity adjustment circuit has its input end connected to the external driving voltage and the gate of the power semiconductor device respectively, and its output end connected to the gate of the power semiconductor device, thereby enhancing the pull-down capability of the gate voltage of the power semiconductor device and/or weakening the pull-up capability of the gate voltage of the power semiconductor device.

Furthermore, the pulling capacity adjustment circuit includes: a pull-up adjustment module, wherein the input end of the pull-up adjustment module is respectively connected to the driving voltage from the outside and the gate of the power semiconductor device, and the output end is connected to the gate of the power semiconductor device; after the power semiconductor device is turned on, the pull-up capacity of the gate voltage of the power semiconductor device is weakened.

Furthermore, the pull-up adjustment unit includes: a device conduction detection module, a logic AND gate, and a seventh semiconductor device, wherein:

The device conduction detection module has an input end connected to the gate of the power semiconductor device and an output end connected to an input end of the logic AND gate;

The logic AND gate has another input terminal connected to the driving voltage and an output terminal connected to the gate of the seventh semiconductor device;

The seventh semiconductor device has a source connected to a power source and a drain connected to a gate of the power semiconductor device;

Furthermore, the pull-up adjustment unit includes: a first pulse generating module and a seventh semiconductor device, wherein the input end of the first pulse generating module is connected to the driving voltage, and the output end is connected to the gate of the seventh semiconductor device; the source of the seventh semiconductor device is connected to the power supply, and the drain is connected to the gate of the power semiconductor device.

Further, the pull-down adjustment circuit includes: a pull-down adjustment module, the pull-down adjustment unit, whose input end is respectively connected to the external driving voltage and the gate of the power semiconductor device, and whose output end is connected to the gate of the power semiconductor device; after the power semiconductor device is turned off, the pull-down ability of the gate voltage of the power semiconductor device is enhanced. Further, the pull-down adjustment unit includes: a device turn-off detection module, a logic OR gate, and a twelfth semiconductor device, wherein,

The device cutoff detection module has an input end connected to the gate of the power semiconductor device and an output end connected to an input end of the logic OR gate;

The other input terminal of the logic OR gate is connected to the driving voltage, and the output terminal is connected to the gate of the twelfth semiconductor device; the source of the twelfth semiconductor device is connected to the ground, and the drain is connected to the gate of the power semiconductor device.

Furthermore, the pull-down adjustment unit includes: a second pulse generating module and a twelfth semiconductor device, wherein the input end of the second pulse generating module is connected to the driving voltage, and the output end is connected to the gate of the twelfth semiconductor device; the source of the twelfth semiconductor device is connected to the power supply, and the drain is connected to the gate of the power semiconductor device.

Furthermore, the pull-down adjustment module further comprises: a tenth semiconductor device and an eleventh semiconductor device, wherein:

The tenth semiconductor device has a source connected to the ground, a drain connected to the source of the eleventh semiconductor device, and a gate connected to the gate of the power semiconductor device;

The gate and drain of the eleventh semiconductor device are connected to the driving current generating circuit.

Further, the driving current generating circuit includes: a first semiconductor device, a second semiconductor device, a third semiconductor device, a fourth semiconductor device, a seventh semiconductor device, an eighth semiconductor device, a ninth semiconductor device, a twelfth semiconductor device, a current source, and a switch, wherein:

The switching switch has a common end connected to one end of the current source and a control end connected to a driving voltage;

The other end of the current source is grounded;

The source of the first semiconductor device, the source of the second semiconductor device, the source of the third semiconductor device, and the source of the fourth semiconductor device are connected to a power source;

The source of the eighth semiconductor device and the source of the ninth semiconductor device are grounded;

The drain of the second semiconductor device and the drain of the ninth semiconductor device are connected as the output terminal of the driving current generating circuit.

Furthermore, the driving current generating circuit further comprises: an accelerated shutdown module, the accelerated shutdown module comprises: a fifth semiconductor device and a sixth semiconductor device, wherein:

The gate of the fifth semiconductor device is connected to the drain of the sixth semiconductor device M6, and is respectively connected to the first switch node of the switching switch, the gate and drain of the first semiconductor device, and the gate of the second semiconductor device;

The gate of the sixth semiconductor device is connected to the drain of the fifth semiconductor device, and is respectively connected to the second switch node of the switching switch, the gate of the third semiconductor device, and the gate and drain of the fourth semiconductor device;

A source of the fifth semiconductor device and a source of the sixth semiconductor device are connected to a power source.

Compared with the prior art, the power semiconductor device driving circuit of the present application has the following beneficial effects: through the pulling capacity adjustment circuit, the pull-up capacity and the pull-down capacity can be automatically adjusted according to the gate voltage of the power semiconductor device, so that the power semiconductor device can stably operate in the on or off state, which can ensure the stability and reliability of the working state of the power semiconductor device, and at the same time ensure the reliability of the circuit.

Other features and advantages of the present application will be set forth in the following description, and in part will become apparent from the description, or may be understood by practicing the present application.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are used to provide a further understanding of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the present application and do not constitute a limitation of the present application. In the accompanying drawings:

FIG1 is a principle block diagram of a power semiconductor device driving circuit according to the present application;

FIG2 is a schematic diagram of a power semiconductor device driving circuit according to Embodiment 1 of the present application;

FIG3 is an input and output waveform diagram of the device conduction detection module according to the present application when the gate voltage Vg increases;

FIG4 is an input and output waveform diagram of the device cut-off detection module according to the present application when the gate voltage Vg decreases;

FIG5 is a schematic diagram of a power semiconductor device driving circuit according to Embodiment 2 of the present application;

FIG6 is a diagram showing input and output waveforms of the first pulse generating module according to the present application when the gate voltage Vg is increased.

FIG. 7 is a diagram showing input and output waveforms of the second pulse generating module according to the present application when the gate voltage Vg is pulled low.

DETAILED DESCRIPTION

The embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be construed as being limited to the embodiments described herein. Instead, these embodiments are provided to provide a more thorough and complete understanding of the present application. It should be understood that the drawings and embodiments of the present application are only for exemplary purposes and are not intended to limit the scope of protection of the present application.

It should be understood that the various steps described in the method implementation of the present application can be performed in different orders and/or performed in parallel. In addition, the method implementation may include additional steps and/or omit the steps shown. The scope of the present application is not limited in this respect.

The term "including" and its variations used herein are open inclusions, i.e., "including but not limited to". The term "based on" means "based at least in part on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The relevant definitions of other terms will be given in the following description.

It should be noted that the modifications of "one" and "plurality" mentioned in this application are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, it should be understood as "one or more". "Plurality" should be understood as two or more.

It should be noted that the "pull-up" mentioned in this application refers to pulling the voltage up, and "pull-down" refers to pulling the voltage down. The "pull-up capability" mentioned in this application refers to the ability to pull the level up, and the stronger the pull-up capability, the higher the voltage can be pulled. The "pull-down capability" mentioned in this application refers to the ability to pull the level down, and the stronger the pull-down capability, the lower the voltage can be pulled.

In an embodiment of the present application, a power semiconductor device driving circuit includes: a driving current generating circuit, a pulling capacity adjusting circuit, and a power semiconductor device, wherein:

The driving current generating circuit has an input end connected to an external driving voltage and an output end connected to the gate of the power semiconductor device, so as to provide a driving current for the power semiconductor device;

The pulling capacity adjustment circuit has its input end connected to the external driving voltage and the gate of the power semiconductor device respectively, and its output end connected to the gate of the power semiconductor device, thereby enhancing the pull-down capability of the gate voltage of the power semiconductor device and/or weakening the pull-up capability of the gate voltage of the power semiconductor device.

Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings.

Example 1

An embodiment of the present application provides a power semiconductor device driving circuit for controlling a power semiconductor device to operate in an on or off state.

Figure 1 is a principle block diagram of a power semiconductor device driving circuit according to the present application. As shown in Figure 1, the power semiconductor device driving circuit of Example 1 of the present application includes: a driving current generating circuit 1, a pulling capacity adjustment circuit 2, and a power semiconductor device Np, wherein the driving current generating circuit 1 receives a driving voltage from the outside, sends the generated driving current signal to the power semiconductor device Np, and controls the conduction or cutoff of the power semiconductor device Np.

In the embodiment of the present application, the output end of the driving current generating circuit 1 is connected to the gate of the power semiconductor device Np to provide a driving current for the power semiconductor device Np.

The pulling capacity adjustment circuit 2 receives the driving voltage from the outside and the gate voltage from the power semiconductor device Np, respectively, generates a gate voltage control signal, weakens the pull-up capability of the driving current generating circuit 1 on the gate voltage of the power semiconductor device Np, or enhances the pull-down capability of the driving current generating circuit 1 on the gate voltage of the power semiconductor device Np.

In the embodiment of the present application, the pulling capacity adjustment circuit 2 is respectively connected to the external driving voltage, the gate of the power semiconductor device Np, and the pulling enhancement input terminal of the driving current generating circuit 1.

The gate of the power semiconductor device Np is respectively connected to the output end of the driving current generating circuit 1 and the control output end of the pulling capacity adjusting circuit 2, and is in an on or off working state under the control of the driving current generating circuit 1 and the pulling capacity adjusting circuit 2.

Example 2

Figure 2 is a schematic diagram of a power semiconductor device driving circuit according to Example 1 of the present application. As shown in Figure 2, the power semiconductor device driving circuit of Example 1 of the present application includes: a driving current generating circuit 1, a pulling capacity adjustment circuit 2, and a power semiconductor device Np, wherein the driving current generating circuit 1 includes a first semiconductor device M1, a second semiconductor device M2, a third semiconductor device M3, a fourth semiconductor device M4, an eighth semiconductor device M8, a ninth semiconductor device M9, a current source Ictl, and a switching switch K, wherein the third semiconductor device M3 has a gate connected to the gate and drain of the fourth semiconductor device M4 and the second switch node n2 of the switching switch K, and a drain connected to the gate and drain of the eighth semiconductor device M8 and the gate of the ninth semiconductor device M9.

A source of the third semiconductor device M3 and a source of the fourth semiconductor device M4 are respectively connected to a power source VDD.

The second semiconductor device M2 has a gate connected to the gate and drain of the first semiconductor device M1 and the first switch node n1 of the switch K, and a drain connected to the drain of the ninth semiconductor device M9 and the gate of the power semiconductor device Np.

The source of the first semiconductor device M1 and the source of the second semiconductor device M2 are respectively connected to a power source VDD.

The source of the eighth semiconductor device M8 and the source of the ninth semiconductor device M9 are grounded.

The common end of the switch K is connected to one end of the current source Ictl, and the other end of the current source Ictl is grounded.

In the embodiment of the present application, the second semiconductor device M2 generates a pull-up signal at the gate of the power semiconductor device Np, and the ninth semiconductor device M9 generates a pull-down signal at the gate of the power semiconductor device Np.

In the embodiment of the present application, the driving current generating circuit 1 further includes an accelerating closing module 11.

The first output terminal of the accelerated closing module 11 is respectively connected to the first switch node n1 of the switching switch K, the gate and drain of the first semiconductor device M1, and the gate of the second semiconductor device M2;

The second output terminal of the accelerated closing module 11 is respectively connected to the second switch node n2 of the switch K, the gate of the third semiconductor device M3, and the gate and drain of the fourth semiconductor device M4.

In the embodiment of the present application, the accelerated shutdown module 11 includes a fifth semiconductor device M5 and a sixth semiconductor device M6, wherein:

The gate of the fifth semiconductor device M5 is connected to the drain of the sixth semiconductor device M6, serving as the first output terminal of the accelerated shutdown module 11;

The gate of the sixth semiconductor device M6 is connected to the drain of the fifth semiconductor device M5, serving as the second output terminal of the accelerated shutdown module 11;

A source of the fifth semiconductor device M5 and a source of the sixth semiconductor device M6 are connected to a power source.

In the embodiment of the present application, the fifth semiconductor device M5 is used to accelerate the closing of the third semiconductor device M3, and the sixth semiconductor device M6 is used to accelerate the closing of the second semiconductor device M2. When the driving voltage Vdrv of the control node n4 of the switching switch K switches the control current Ictl to the first switch node n2, the first switch node n2 will be pulled down, causing the sixth semiconductor device M6 to open, and the charge can be discharged to the first switch node n1 faster, thereby closing the second semiconductor device M2, and the positive feedback loop composed of the fifth semiconductor device M5/sixth semiconductor device M6 will accelerate this process; conversely, when the driving voltage Vdrv of the control node n4 of the switching switch K switches the control current Ictl to the first switch node n1, the first switch node n1 will be pulled down, causing the fifth semiconductor device M5 to open, and the charge can be discharged to the second switch node n2 faster, thereby closing the third semiconductor device M3, and the positive feedback loop composed of the fifth semiconductor device M5/sixth semiconductor device M6 will accelerate this process.

In the embodiment of the present application, the pull-up capability adjustment circuit 2 includes a pull-up adjustment unit 20 and a pull-down adjustment unit (30, 40), wherein the pull-up adjustment unit 20 has an input end connected to an external driving voltage Vdrv and a gate of a power semiconductor device Np, respectively, and an output end connected to the gate of the power semiconductor device Np. After the power semiconductor device Np is turned on, the pull-up capability of the driving current generating circuit 10 on the gate voltage of the power semiconductor device Np is weakened to ensure that the power semiconductor device Np stably works in a turned-on working state.

In the embodiment of the present application, the pull-up adjustment unit 20 includes: a device conduction detection module 21, a logic AND gate 22, and a seventh semiconductor device M7, wherein the device conduction detection module 21 has an input end connected to the gate of the power semiconductor device Np, and an output end connected to an input end of the logic AND gate 22;

Another input terminal of the logic AND gate 22 is connected to the driving voltage Vdrv, and an output terminal is connected to the gate of the seventh semiconductor device M7; the source of the seventh semiconductor device M7 is connected to the power supply, and the drain is connected to the gate of the power semiconductor device Np.

Figure 3 is an input and output waveform diagram of the device conduction detection module according to the present application when the gate voltage Vg increases. As shown in Figure 3, the device conduction detection module 21 is connected to the gate of the power semiconductor device Np. After the power semiconductor device Np is turned on, when the gate voltage Vg increases to the preset threshold value Vth2, its output voltage increases from a low level (VSS) to a high level (VDD). At this time, the other input terminal of the logic AND gate 22 is connected to the driving voltage Vdrv as a low level, the device conduction detection module 21 outputs a high level, the seventh semiconductor device M7 is cut off, and the pull-up ability of the gate voltage Vg of the power semiconductor device Np is reduced.

In the embodiment of the present application, the pull-down adjustment unit 30 includes: a device cut-off detection module 31, a logic OR gate 32, and a twelfth semiconductor device M12, wherein:

The input end of the device cutoff detection module 31 is connected to the gate of the power semiconductor device Np, and the output end is connected to an input end of the logic OR gate 32;

Another input terminal of the logic OR gate 32 is connected to the driving voltage Vdrv, and an output terminal is connected to the gate of the twelfth semiconductor device M12;

The source of the twelfth semiconductor device M12 is grounded, and the drain is connected to the gate of the power semiconductor device Np.

Figure 4 is an input and output waveform diagram of the device cut-off detection module according to the present application when the gate voltage Vg is reduced. As shown in Figure 4, the input end of the device cut-off detection module 31 is connected. When the gate voltage Vg of the power semiconductor device Np is reduced to the preset threshold value Vth1, the output end of the device cut-off detection module 31 changes from a low level (VSS) to a high level (VDD). At this time, the output of the logic OR gate 32 is a high level (VDD), so that the twelfth semiconductor device M12 is turned on, thereby enhancing the pull-down capability of the gate voltage Vg of the power semiconductor device Np.

In the embodiment of the present application, the pull-down adjustment unit 40 includes a tenth semiconductor device M10 and an eleventh semiconductor device M11, wherein the gate of the tenth semiconductor device M10 is connected to the gate of the power semiconductor device Np, so as to obtain the on or off working state of the power semiconductor device Np;

The drain of the tenth semiconductor device M10 is connected to the source of the eleventh semiconductor device M11.

The source of the tenth semiconductor device M10 is grounded;

The gate and drain of the eleventh semiconductor device M11 are connected and connected to the drain of the third semiconductor device M3 .

When the power semiconductor device Np is turned off, the driving voltage Vdrv of the control node n4 of the switching switch K switches the control current Ictl to the second switch node n2, and the current passes through the current mirror composed of the fourth semiconductor device M4 and the third semiconductor device M3, and then passes through the current mirror composed of the eighth semiconductor device M8 and the ninth semiconductor device M9, and pulls down the gate voltage Vg, so that the power semiconductor device Np is in the cut-off state; when the power semiconductor device Np is turned on, the driving voltage Vdrv of the control node n4 of the switching switch K switches the control current Ictl to the first switch node n1, and the current passes through the current mirror composed of the first semiconductor device M1 and the second semiconductor device M2, and pulls up the gate voltage Vg, so that the power semiconductor device Np is in the on state.

In the embodiment of the present application, the tenth semiconductor device M10 and the eleventh semiconductor device M11 are used to increase the pull-down capability of the ninth semiconductor device M9 after the power semiconductor device Np is in the cut-off state, wherein the tenth semiconductor device M10 is used for switching, and the threshold of the tenth semiconductor device M10 is less than the threshold of the power semiconductor device Np, so when the power semiconductor device Np is cut off, the tenth semiconductor device M10 is turned off. At this time, the current originally flowing through the eleventh semiconductor device M11 can only flow through the eighth semiconductor device M8, resulting in an increase in the current flowing through the eighth semiconductor device M8 and an increase in the voltage of the node n3. Therefore, after the power semiconductor device Np is turned off, the pull-down capability of the ninth semiconductor device M9 is increased.

Example 3

Figure 5 is a schematic diagram of a power semiconductor device driving circuit according to Example 2 of the present application. As shown in Figure 5, the power semiconductor device driving circuit of Example 2 of the present application is different from the power semiconductor device driving circuit described in Example 1 in that: the pull-up adjustment unit 20 of the embodiment of the present application includes: a first pulse generating module 51 and a seventh semiconductor device M7, wherein the first pulse generating module 51 has an input end connected to the driving voltage Vdrv and an output end connected to the gate of the seventh semiconductor device M7; the seventh semiconductor device M7 has a source connected to the power supply and a drain connected to the gate of the power semiconductor device Np.

The pull-down adjustment unit 30 of the embodiment of the present application includes: a second pulse generating module 52 and a twelfth semiconductor device M12, wherein the second pulse generating module 52 has an input end connected to the driving voltage Vdrv and an output end connected to the gate of the twelfth semiconductor device M12;

The twelfth semiconductor device M12 has a source connected to the power supply, and a drain connected to the gate of the power semiconductor device Np.

FIG6 is an input and output waveform diagram of the first pulse generating module according to the present application when the gate voltage Vg is pulled high. As shown in FIG6 , the driving voltage Vdrv is pulled low to generate a signal to turn on the power semiconductor device Np. The driving voltage Vdrv is also the input signal of the first pulse generating module 51. The gate voltage Vg of the power semiconductor device Np increases, so that after the power semiconductor device Np is turned on, the output V1 of the first pulse generating module 51 is pulled low to turn off the seventh semiconductor device M7. The pulse delay time Tpulse generated by the first pulse generating module 51 can ensure that the seventh semiconductor device M7 is turned off after the power semiconductor device Np is fully turned on, thereby weakening the pull-up capability of Vg. In FIG6 , after the gate voltage Vg of the power semiconductor device Np is pulled high to a high level (VDD), the output voltage V1 of the first pulse generating module 51 is pulled high, which is a situation in which the seventh semiconductor device M7 is turned off after the power semiconductor device Np is turned on.

FIG7 is an input and output waveform diagram of the second pulse generating module according to the present application when the gate voltage Vg is pulled low. As shown in FIG7 , the driving voltage Vdrv is pulled high to generate a signal to turn off the power semiconductor device Np. The driving voltage Vdrv is also the input signal of the second pulse generating module 52. The gate voltage Vg of the power semiconductor device Np is reduced, so that after the power semiconductor device Np is turned off, the output V2 of the second pulse generating module 52 is pulled high to turn on the twelfth semiconductor device M12. The pulse delay time Tdelay output by the second pulse generating module 52 can ensure that the twelfth semiconductor device M12 is turned on after the power semiconductor device Np is turned off, thereby enhancing the pull-down capability of Vg. In FIG7 , after the gate voltage Vg of the power semiconductor device Np is pulled low to a low level (VSS), the output voltage V2 of the second pulse generating module 52 is pulled high, which is a situation in which the twelfth semiconductor device M12 is turned on after the power semiconductor device Np is turned off.

In the above embodiments of the present application, the pull capability adjustment circuit 2 may include a pull-up adjustment unit 20 , a pull-down adjustment unit 30 , or one or more of the pull-down adjustment units 30 .

The above description is only a partial embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of disclosure involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosed concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other to form a technical solution.

In addition, although each operation is described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. Under certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although some specific implementation details are included in the above discussion, these should not be construed as limiting the scope of the application. Some features described in the context of a separate embodiment can also be implemented in a single embodiment in combination. On the contrary, the various features described in the context of a single embodiment can also be implemented in multiple embodiments individually or in any suitable sub-combination mode.

Although the subject matter has been described in language specific to structural features and/or methodological logical actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. On the contrary, the specific features and actions described above are merely example forms of implementing the claims.

Claims (10)

1. A power semiconductor device driving circuit, characterized in that it comprises: a driving current generating circuit, a pulling capacity adjusting circuit, and a power semiconductor device, wherein: The driving current generating circuit has an input end connected to an external driving voltage and an output end connected to the gate of the power semiconductor device, so as to provide a driving current for the power semiconductor device; The pulling capacity adjustment circuit has its input end connected to the external driving voltage and the gate of the power semiconductor device respectively, and its output end connected to the gate of the power semiconductor device, thereby enhancing the pull-down capability of the gate voltage of the power semiconductor device and/or weakening the pull-up capability of the gate voltage of the power semiconductor device. 2. The power semiconductor device driving circuit according to claim 1, characterized in that the pull-up capability adjustment circuit comprises: a pull-up adjustment module, The pull-up adjustment module has an input end connected to an external driving voltage and a gate of the power semiconductor device, and an output end connected to the gate of the power semiconductor device; after the power semiconductor device is turned on, the pull-up capability of the gate voltage of the power semiconductor device is weakened. 3. The power semiconductor device driving circuit according to claim 2, characterized in that The pull-up adjustment unit includes: a device conduction detection module, a logic AND gate, and a seventh semiconductor device, wherein: The device conduction detection module has an input end connected to the gate of the power semiconductor device and an output end connected to an input end of the logic AND gate; The logic AND gate has another input terminal connected to the driving voltage and an output terminal connected to the gate of the seventh semiconductor device; The seventh semiconductor device has a source connected to a power source, and a drain connected to the gate of the power semiconductor device. 4. The power semiconductor device driving circuit according to claim 2, characterized in that The pull-up adjustment unit includes: a first pulse generating module and a seventh semiconductor device, wherein: The first pulse generating module has an input end connected to a driving voltage and an output end connected to the gate of the seventh semiconductor device; the seventh semiconductor device has a source connected to a power source and a drain connected to the gate of the power semiconductor device. 5. The power semiconductor device driving circuit according to claim 1, characterized in that the pull-up capability adjustment circuit comprises: a pull-down adjustment unit, The pull-down adjustment unit has an input end connected to an external driving voltage and a gate of the power semiconductor device, and an output end connected to the gate of the power semiconductor device. After the power semiconductor device is turned off, the pull-down capability of the gate voltage of the power semiconductor device is enhanced. 6. The power semiconductor device driving circuit according to claim 5, characterized in that The pull-down adjustment unit comprises: a device cut-off detection module, a logic OR gate, and a twelfth semiconductor device, wherein the device cut-off detection module has an input end connected to the gate of the power semiconductor device and an output end connected to an input end of the logic OR gate; The other input terminal of the logic OR gate is connected to the driving voltage, and the output terminal is connected to the gate of the twelfth semiconductor device; the source of the twelfth semiconductor device is connected to the ground, and the drain is connected to the gate of the power semiconductor device. 7. The power semiconductor device driving circuit according to claim 5, characterized in that The pull-down adjustment unit includes: a second pulse generating module and a twelfth semiconductor device, wherein: The second pulse generating module has an input end connected to a driving voltage and an output end connected to the gate of the twelfth semiconductor device; the twelfth semiconductor device has a source connected to a power source and a drain connected to the gate of the power semiconductor device. 8. The power semiconductor device driving circuit according to claim 5, characterized in that the pull-down adjustment module further comprises: a tenth semiconductor device and an eleventh semiconductor device, wherein: The tenth semiconductor device has a source connected to the ground, a drain connected to the source of the eleventh semiconductor device, and a gate connected to the gate of the power semiconductor device; The gate and drain of the eleventh semiconductor device are connected to the driving current generating circuit. 9. The power semiconductor device driving circuit according to claim 1, characterized in that the driving current generating circuit comprises: a first semiconductor device, a second semiconductor device, a third semiconductor device, a fourth semiconductor device, a seventh semiconductor device, an eighth semiconductor device, a ninth semiconductor device, a twelfth semiconductor device, a current source, and a switch, wherein: The switching switch has a common end connected to one end of the current source and a control end connected to a driving voltage; The other end of the current source is grounded; The source of the first semiconductor device, the source of the second semiconductor device, the source of the third semiconductor device, and the source of the fourth semiconductor device are connected to a power source; The source of the eighth semiconductor device and the source of the ninth semiconductor device are grounded; The drain of the second semiconductor device and the drain of the ninth semiconductor device are connected as the output terminal of the driving current generating circuit. 10. The power semiconductor device driving circuit according to claim 9, characterized in that the driving current generating circuit further comprises: an accelerated shutdown module, The accelerated shutdown module includes: a fifth semiconductor device and a sixth semiconductor device, wherein: The gate of the fifth semiconductor device is connected to the drain of the sixth semiconductor device M6, and is respectively connected to the first switch node of the switching switch, the gate and drain of the first semiconductor device, and the gate of the second semiconductor device; the gate of the sixth semiconductor device is connected to the drain of the fifth semiconductor device, and is respectively connected to the second switch node of the switching switch, the gate of the third semiconductor device, and the gate and drain of the fourth semiconductor device; A source of the fifth semiconductor device and a source of the sixth semiconductor device are connected to a power source.