CN118824155A - Display device - Google Patents

Abstract

The embodiment of the application provides a display device, which comprises a display panel, wherein a gate line, a data line and a plurality of sub-pixel circuits are arranged on the display panel, each sub-pixel circuit comprises a pixel driving circuit and a light emitting element, an edge improving circuit is configured to acquire a pulse width modulation signal, a compensation control signal is output according to the signal, a light emitting threshold compensating circuit is electrically connected with the edge improving circuit and is configured to acquire driving data and a compensation control signal, in the display stage of each display period, when the edge improving circuit does not output the compensation control signal, the driving data compensated by the threshold voltage of a driving transistor is utilized to generate the driving signal, when the edge improving circuit outputs the compensation control signal, the light emitting element is not influenced by the drift of the threshold voltage in the light emitting process, and the light emitting intensity is only influenced by the driving data under the condition that the light emitting time length is consistent, so that the uniformity of the light emitting element in the display process is ensured.

Description

Display device

Technical Field

Embodiments of the present application relate to the field of display technology, and in particular, to a display device.

Background Art

In recent years, due to the advantages of micro-LEDs over AMOLEDs (Active-matrix organic light emitting diodes), such as smaller device size, faster response speed, higher luminous efficiency, stronger stability and longer service life, the display application field based on micro-LEDs has developed rapidly and has become a research hotspot for display devices.

The pixel driving circuit of the micro LED can drive the micro LED to emit light through pulse width modulation (PWM) + pulse amplitude modulation (PAM), that is, the pixel driving circuit obtains the PWM signal, determines the time when the pixel driving circuit generates the driving signal according to the PWM signal, so as to determine the light-emitting time of the micro transistor in each frame display cycle, and then determines the current value in the driving signal according to the PAM signal to determine the light intensity of the micro transistor during the light-emitting process, thereby determining the brightness of the micro LED in each frame display cycle.

However, the driving transistor that generates the driving signal in the pixel driving circuit is affected by the uniformity of the manufacturing process. During use, the threshold voltage value of the transistor will drift, resulting in changes in the current value of the driving signal generated by the pixel driving circuit under the same PAM signal drive, which ultimately causes uneven brightness of the micro LED display panel, poor display, and affected image quality.

Summary of the invention

The present application provides a display device to solve the technical problem of poor uniformity of light emission of micro LEDs based on PWM and PAM driving.

In a first aspect, an embodiment of the present application provides a display device, including:

A display panel, on which a plurality of gate lines, a plurality of data lines and a plurality of sub-pixel circuits are arranged;

Each of the sub-pixel circuits includes a pixel driving circuit and a light-emitting element;

The pixel driving circuit includes a light emitting threshold compensation circuit and an edge improvement circuit, and the light emitting threshold compensation circuit includes a driving transistor;

The edge improvement circuit is electrically connected to the gate line and is configured to obtain a pulse width modulation signal and output a compensation control signal according to the pulse width modulation signal during a display phase of each display cycle;

The light-emitting threshold compensation circuit is electrically connected to the edge improvement circuit and the data line, and is configured to obtain the driving data and the compensation control signal, and in the display phase of each display cycle, when the edge improvement circuit does not output the compensation control signal, generate a corresponding driving signal using the driving data after the threshold voltage of the driving transistor is compensated; when the edge improvement circuit outputs the compensation control signal, stop generating the driving signal;

The light emitting element is electrically connected to the light emitting threshold compensation circuit and is configured to emit light according to the driving signal.

In the above technical solution, a pixel driving circuit is provided, including a light-emitting threshold compensation circuit and an edge improvement circuit. The edge improvement circuit generates a compensation control signal according to the pulse modulation signal, and controls the driving time of the driving transistor in the light-emitting threshold compensation circuit to the light-emitting element including the micro-LED by adjusting the duration of generating the compensation control signal in the display stage. During the operation of the driving transistor, the light-emitting threshold compensation circuit compensates the driving data using the threshold voltage of the driving transistor, so that the light-emitting element is not affected by the drift of the threshold voltage during the light-emitting process, and the light-emitting intensity is only affected by the driving data when the light-emitting duration is consistent, thereby ensuring the uniformity of the light-emitting element during the display process.

In a feasible implementation manner, the light emission threshold compensation circuit is also electrically connected to the gate line, and is configured to obtain the first driving data and the scanning signal during the non-display phase of the display cycle, compensate the first driving data using the threshold voltage of the driving transistor, and generate and store the second driving data;

In the light-emitting phase of the display phase, a corresponding driving signal is generated according to the second driving data and outputted from the output end thereof;

In the non-light-emitting stage of the display stage, the compensation control signal is acquired, and the generation of the driving signal is stopped according to the compensation control signal.

In the above technical solution, the luminous threshold compensation circuit obtains the first driving data in the non-display stage, and compensates the first driving data using the threshold voltage, so that the generated second driving data is the driving data that takes into account the drift influence of the threshold voltage. In the display stage, the luminous threshold compensation circuit calculates the current value of the driving signal using the compensated driving data to offset the threshold voltage so that the current value of the driving signal is no longer affected by the threshold voltage, thereby ensuring the uniformity of the light-emitting element during the display process.

In a feasible implementation manner, the display panel is further provided with a power line; the light emission threshold compensation circuit further comprises: a data input transistor, a threshold compensation transistor and a third capacitor;

The data input transistor has a first end electrically connected to the data line, a second end electrically connected to the first end of the driving transistor, and a control end electrically connected to the gate line, and is configured such that the first end thereof obtains the first driving data from the data line, the control end thereof obtains the scanning signal from the gate line, and the conducting state thereof is controlled by the scanning signal, and the first driving data is transmitted to the first end of the driving transistor when the transistor is conducting;

The threshold compensation transistor has a first end electrically connected to the second end of the driving transistor, a second end electrically connected to the control end of the driving transistor, and a control end electrically connected to the gate line, and is configured such that its control end obtains the scanning signal from the gate line, and its conduction state is controlled by the scanning signal;

The driving transistor is configured to determine second driving data from its control terminal according to the first driving data and a threshold voltage when the threshold compensation transistor is turned on;

The third capacitor has a first end electrically connected to the control end of the driving transistor and a second end electrically connected to the power line, and is configured to store the electrical signal obtained by the first end.

In the above technical solution, based on the circuit structure composed of the threshold compensation transistor and the driving transistor, when the threshold compensation transistor is turned on, a diode structure is formed, and the potential value of the control end of the driving transistor is the second driving data considering the threshold voltage of the driving transistor and the first driving data. The third capacitor stores the electrical signal related to the threshold voltage, so that when the driving transistor works in the subsequent display stage, the threshold voltage is offset when the current value of the driving signal is determined according to the voltage stored in the third capacitor, the threshold voltage and the voltage value of its first end. The current value of the driving signal is only affected by the first driving data, thereby increasing the display uniformity of the light-emitting element.

In a feasible implementation manner, the light emission threshold compensation circuit further includes: a first conduction control transistor and a second conduction control transistor;

The first conduction control transistor has a first end electrically connected to the power line, a second end electrically connected to the first end of the driving transistor, and a control end electrically connected to the gate line, and is configured such that the first end thereof obtains a first power signal from the power line, and the control end thereof obtains a first light emission control signal from the gate line, and the conduction state thereof is controlled by the light emission control signal;

The second conduction control transistor has a first end electrically connected to the second end of the driving transistor, a second end electrically connected to the first end of the light-emitting element, and a control end electrically connected to the gate line. The second conduction control transistor is configured such that its control end obtains the light-emitting control signal from the gate line, and its conduction state is controlled by the first light-emitting control signal.

In the above technical solution, a first conduction control transistor and a second conduction control transistor are provided in the light-emitting threshold compensation circuit to construct a light-emitting circuit consisting of a driving transistor, the two conduction control transistors and a light-emitting element. The conduction states of the two conduction control transistors are controlled by a light-emitting control signal so that the driving transistor blocks the influence of the first power supply signal when generating the second driving data according to the first driving data, thereby ensuring the accuracy of the light-emitting element in controlling its light intensity in the subsequent display stage.

In a feasible implementation manner, within a display cycle, the display phase is the next phase of the non-display phase;

The non-display phase includes a reset phase and a data writing phase in sequence;

In the non-display stage, the edge improvement circuit is in a turned-off state and does not output the compensation control signal;

The light emission threshold compensation circuit generates and stores the second driving data, and does not generate a driving signal;

The light emitting element does not emit light.

In a feasible implementation manner, in the reset stage, the reset signal and the second power supply signal are at a first level, and the scan signal, the first light-emitting control signal, and the second light-emitting control signal are at a second level;

The edge improvement circuit is turned off according to the second light emitting control signal and does not output the compensation control signal;

The first reset transistor is turned on according to the reset signal, and transmits the second power supply signal obtained at its first end to the first end of the third capacitor and the control end of the driving transistor;

The third capacitor stores the second power signal;

The driving transistor is turned on according to the second power signal.

In a feasible implementation manner, in the data writing phase, the scanning signal is at a first level, and the reset signal, the first light emitting control signal and the second light emitting control signal are at a second level;

The edge improvement circuit is turned off according to the second light emitting control signal and does not output the compensation control signal;

The data input transistor is turned on according to the scanning signal, and transmits the first driving data obtained at the first end thereof to the first end of the driving transistor;

The threshold compensation transistor is turned on according to the scanning signal to short-circuit the control terminal and the second terminal of the driving transistor;

The driving transistor remains in an on state, and determines the voltage value of its control terminal to be the second driving data according to its threshold voltage and the first driving data;

The third capacitor stores the second driving data.

In the above technical solution, the luminous threshold compensation circuit uses the first reset transistor to transmit and store the second power supply signal in the non-display stage, so that the driving transistor is always kept in the on state in the non-display stage, so that the data writing circuit composed of the driving transistor, the threshold compensation transistor, the driving transistor and the third capacitor is turned on in the data writing stage, and the first driving data obtained by the circuit is used to generate and store the second driving data, so that the luminous threshold compensation circuit uses the second driving data to generate a driving signal that is independent of the threshold voltage in the subsequent luminous stage.

In a feasible implementation manner, the display stage includes a light-emitting stage and a non-light-emitting stage in sequence;

In the light-emitting phase, the edge improvement circuit is in an off state and does not output the compensation control signal, and the light-emitting threshold compensation circuit generates a driving signal to control the light-emitting element to emit light;

In the non-luminescent stage, the edge improvement circuit is in the on state and outputs the compensation control signal. The luminescent threshold compensation circuit does not generate a driving signal when obtaining the compensation control signal, and controls the light-emitting element to stop emitting light.

In a feasible implementation manner, the light-emitting stage includes a first light-emitting stage, a second light-emitting stage and a third light-emitting stage.

In the first light-emitting stage, the first light-emitting control signal is at a first level, and the reset signal, the scan signal, the pulse width modulation signal, the second light-emitting control signal and the first power supply signal are at a second level;

In the second light-emitting stage, the first light-emitting control signal and the second light-emitting control signal are at a first level, and the pulse width modulation signal, the reset signal, the scanning signal and the first power supply signal are at a second level;

In the third light-emitting stage, the first light-emitting control signal, the second light-emitting control signal and the pulse width modulation signal are at a first level, and the reset signal and the scan signal are at a second level.

In a feasible implementation manner, during the light emitting phase,

The edge improvement circuit is turned off according to the second light emitting control signal and the pulse width modulation signal, and does not output the compensation control signal;

The first conduction control transistor is turned on according to the first light emitting control signal, and transmits the first power supply signal obtained at its first end to the first end of the driving transistor;

The driving transistor remains in an on state, and outputs a driving signal that is independent of the threshold voltage from its second terminal according to the first power signal, the second driving data and the threshold voltage;

The second conduction control transistor is turned on according to the first light emitting control signal, and transmits the driving signal obtained at its first end to the first end of the light emitting element;

The light emitting element emits light according to the driving signal.

In a feasible implementation manner, in the non-light-emitting stage, the first light-emitting control signal, the second light-emitting control signal and the pulse width modulation signal are at a first level, and the reset signal and the scanning signal are at a second level;

The edge improvement circuit is turned on according to the second light emitting control signal and the pulse width modulation signal, and outputs the compensation control signal;

The first conduction control transistor and the second conduction control transistor remain in a conduction state, the driving transistor is turned off according to the compensation control signal, stops generating the driving signal, and the second conduction transistor stops transmitting the driving signal;

The light emitting element stops emitting light.

In the above technical solution, the light-emitting threshold compensation circuit controls the light-emitting duration of the light-emitting element according to the compensation control signal obtained during the light-emitting stage. During the light-emitting process, the light-emitting circuit is turned on, and the on-transistor determines the current value flowing through the light-emitting circuit through the first power supply signal obtained and the second drive data stored in the data writing stage, as well as the threshold voltage, thereby determining the light-emitting intensity of the light-emitting element. Since the second drive data is compensated by the threshold voltage when it is generated, the above current is no longer affected by the threshold voltage, thereby ensuring the display uniformity of the light-emitting element.

The display device provided in the embodiment of the present application includes a display panel, on which a plurality of gate lines, a plurality of data lines and a plurality of sub-pixel circuits are arranged, each sub-pixel circuit includes a pixel driving circuit and a light-emitting element, in the pixel driving circuit, an edge improvement circuit is electrically connected to the gate line, and is configured to obtain a pulse width modulation signal, and output a compensation control signal according to the pulse width modulation signal, a light-emitting threshold compensation circuit is electrically connected to the edge improvement circuit and the data line, and is configured to obtain driving data and a compensation control signal, in the display phase of each display cycle, when the edge improvement circuit does not output the compensation control signal, a corresponding driving signal is generated using the driving data compensated by the threshold voltage of the driving transistor, when the edge improvement circuit outputs the compensation control signal, the generation of the driving signal is stopped, the light-emitting element is not affected by the drift of the threshold voltage during the light-emitting process, and the light-emitting intensity is only affected by the driving data when the light-emitting duration is consistent, thereby ensuring the uniformity of the light-emitting element during the display process.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

FIG1 is a schematic structural diagram of a display device provided by the present application according to an exemplary embodiment;

FIG2 is a schematic structural diagram of a display device provided according to another exemplary embodiment of the present application;

FIG3 is a circuit structure diagram of a conventional pixel driving circuit provided by the present application according to an exemplary embodiment;

FIG4 is a schematic structural diagram of an N-type pixel driving circuit provided in accordance with an exemplary embodiment of the present application;

FIG5 is a driving signal timing diagram of an N-type pixel driving circuit provided in accordance with an exemplary embodiment of the present application;

FIG6 is a schematic structural diagram of a P-type pixel driving circuit provided in accordance with an exemplary embodiment of the present application;

FIG. 7 is a driving signal timing diagram of a P-type pixel driving circuit provided in accordance with an exemplary embodiment of the present application.

The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments.

DETAILED DESCRIPTION

Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

It should be noted that, in this article, the term "include", "comprise" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, the elements defined by the sentence "include one..." do not exclude the existence of other identical elements in the process, method, article or device including the element. In addition, the parts, features, and elements with the same names in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context in the specific embodiment. It should be further understood that the terms "include", "comprise" indicate the existence of features, steps, operations, elements, components, projects, types, and/or groups, but do not exclude the existence, occurrence or addition of one or more other features, steps, operations, elements, components, projects, types, and/or groups.

In the description of the present disclosure, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the feature. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

In recent years, due to the advantages of micro-LEDs over AMOLEDs (Active-matrix organic light emitting diodes), such as smaller device size, faster response speed, higher luminous efficiency, stronger stability and longer service life, the display application field based on micro-LEDs has developed rapidly and has become a research hotspot for display devices.

The structural schematic diagram of the display device is shown in Figures 1 and 2, and includes a control circuit 10, a data driving circuit 20, a gate driving circuit 30, a display panel 40, and a power circuit 70. The control circuit 10 is electrically connected to the data driving circuit 20 and the gate driving circuit 30, respectively, and the display panel 40 is electrically connected to the data driving circuit 20, the gate driving circuit 30, and the power circuit 70.

The display panel 40 includes an active area AA where a plurality of pixel circuits 403 are disposed and a non-active area NA outside the active area.

In the active area AA, there are power lines 80 , multiple gate lines 60 , multiple data lines 50 , and multiple pixel circuits 403 are distributed in an array, each pixel circuit 403 is located in the area where the gate line 60 and the data line 50 intersect.

Each pixel circuit 403 includes a pixel driving circuit 4032 and a light emitting element 4033 . The pixel driving circuit 4032 is electrically connected to the light emitting element 4033 and is configured to drive the light emitting element 4033 to emit light.

The gate drive circuit 30 is electrically connected to the gate line 60 and is configured to obtain a clock signal and a trigger signal from the control circuit 10, generate a gate drive signal, and transmit the gate drive signal to the corresponding pixel circuit 403 through the gate line 60 to control the conduction of the transistor therein.

The gate drive circuit 30 may be connected to the display panel 40 through a gate driver integrated circuit (GDIC), or may be implemented through a gate-in-panel GIP method and directly arranged on the display panel 40. In some cases, each GDIC may be integrated and arranged on the display panel 40 through a chip on glass COG method; in other cases, each GDIC may be implemented through a chip-on-film COF method in which components are connected to a film of the display panel 40 through a flexible printed circuit (FPC).

More specifically, according to the signal type required by the pixel driving circuit 4032, the signal provided by the gate driving circuit 30 includes a driving signal, a scanning signal, and a light emitting control signal.

The driving signal is a signal generated by the control circuit 10 or obtained from the outside, which is transmitted from the control circuit 10 to the gate driving circuit 30, and forwarded to the pixel circuit 403 through the first gate line 601 via the gate driving circuit 30. It includes but is not limited to a start pulse signal, a clock signal, and an enable signal.

The scanning signal is a successive shift signal generated by the gate driving circuit 30 .

More specifically, the gate drive circuit 30 includes a scan signal generating circuit 301, which includes a plurality of scan signal generating sub-circuits connected in series, each of which is configured to obtain a clock signal from the control circuit 10, obtain a scan signal from the output end of the previous scan signal generating sub-circuit, or obtain a trigger signal from the control circuit 10, generate a scan signal corresponding to the current scan signal generating sub-circuit, and transmit the scan signal to the corresponding pixel driving circuit through the corresponding second gate line 602, so as to control the pixel driving circuit to obtain display data in a timely manner. The phase of the output signal of each scan signal generating sub-circuit lags behind the phase of the input signal.

The pixel circuit 403 electrically connected to the scanning signal generating circuit 301 may be electrically connected to the scanning signal generating circuit 301 through at least one second gate line 602 to obtain a scanning signal of at least one phase.

The light emitting control signal may be a global signal provided by the control circuit 10 or a signal generated by the gate driving circuit 30 , which is not specifically limited here.

When the light emitting control signal is a global signal generated by the control circuit 10 , the gate driving circuit 30 obtains the global signal from the control circuit 10 and transmits the global signal to the corresponding pixel driving circuit through the first gate line 601 .

When the light-emitting control signal is a signal generated by the gate driving circuit 30, the light-emitting control signal generating circuit 302 in the gate driving circuit 30 can be used to generate a successive shift signal, and the light-emitting control signal is transmitted to the corresponding pixel driving circuit through the third gate line 603. The process of generating the light-emitting control signal by the light-emitting control signal generating circuit 302 is the same as the process of generating the scanning signal by the scanning signal generating circuit 301, and will not be repeated here.

The data driving circuit 20 is configured to obtain display data from the control circuit 10 and convert it into an analog data voltage, which is transmitted to the corresponding pixel circuit 403 through the data line 50 so that the light-emitting element in the pixel circuit 403 emits light according to the analog data voltage.

The data driving circuit 20 may include one or more source driver integrated circuits (SDICs), each of which may include a shift register, a latch circuit, a digital-to-analog converter, an output buffer, and the like.

The power circuit 70 is a circuit for providing stable electrical signals, and is configured to provide corresponding required power signals to the display panel 40 , the control circuit 10 , the data driving circuit 20 , and the gate driving circuit 30 .

Each pixel circuit 403 includes a plurality of sub-pixel circuits 4031 integrated in a corresponding pixel region. Each sub-pixel circuit 4031 includes a pixel driving circuit 4032 and a light-emitting element 4033. The pixel driving circuit 4032 generates a corresponding current signal according to the driving data obtained, so that the light-emitting element 4033 provides a corresponding brightness.

In one case, each pixel circuit 403 includes three sub-pixel circuits 4031, which are respectively used to display red light, blue light, and green light; in another case, each pixel circuit 403 includes four sub-pixel circuits 4031, which are respectively used to display red light, blue light, green light, and white light. No specific limitation is made here.

The luminous color of each pixel circuit 403 is determined by the properties of the luminous element 4033. The luminous element 4033 can be any luminous device, including but not limited to OLED and micro LED.

Micro LED refers to a micro light emitting body made of inorganic semiconductor layers. Micro LEDs can generally include a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer. The structure of such micro LEDs can be diverse, such as vertical, horizontal, flip-chip, etc., and is not particularly limited to a specific structure.

When driving the light-emitting element to emit light, the pixel driving circuit 4032 can obtain the gate driving signal through the gate line 60, obtain the driving data through the data line, and obtain the power signal through the power line 80, and generate a current signal corresponding to the driving data according to the level state of the driving signal to drive the light-emitting element to emit light.

3 is a circuit structure diagram of a conventional pixel driving circuit provided in accordance with an exemplary embodiment of the present application, including a seventh transistor T7, an eighth transistor T8, a second capacitor C2, a third capacitor C3, a ninth transistor T9 and a tenth transistor T10.

The circuit structure and principle of the conventional pixel driving circuit are explained below on the assumption that all transistors in the conventional pixel driving circuit are N-type transistors.

The first end of the eighth transistor T8 is electrically connected to the power line 80, and the control end is electrically connected to the gate line 60. The eighth transistor T8 is configured such that its first end obtains the first power signal REF from the power line 80, and its control end obtains the second conduction control signal EM2 from the gate line 60. The eighth transistor T8 is turned on when the second conduction control signal EM2 is at a high level, and outputs the first power signal REF from its second end.

A first terminal of the seventh transistor T7 is electrically connected to a second terminal of the eighth transistor T8 , and a control terminal thereof is electrically connected to an output terminal of the PWM signal generating circuit in one case, and is electrically connected to the gate line 60 in another case.

The seventh transistor T7 is configured to obtain a PWM signal from its control terminal and control its conduction state according to the PWM signal, that is, to be turned on when the PWM signal is at a high level and to be turned off when the PWM signal is at a low level. The PWM signal is a square wave signal in the display phase of each display cycle, no signal in the reset phase, and a data signal in the data writing phase.

The first terminal of the second capacitor C2 is electrically connected to the control terminal of the seventh transistor T7, and is configured such that the level of the first terminal changes with the charging/discharging of the second capacitor C2. The waveform corresponding to the level change of the first terminal of the fourth capacitor C4 in each display cycle is a square wave.

Based on this, the edge steepness of the PWM signal obtained by the control terminal voltage of the seventh transistor T7 is relatively slow, which will affect the driving accuracy when directly applied to the transistor driving process.

When the seventh transistor T7 is turned on, when its first end obtains the first power signal REF transmitted by the eighth transistor T8, the first power signal REF is transmitted to point C, and the level conversion edge steepness of point C is greater than the signal edge steepness of its control end.

The first end of the ninth transistor T9 is electrically connected to point C, and its control end is electrically connected to the gate line 60. It is configured to obtain a scan signal from the gate line 60, and to be turned on when the scan signal is at a high level. When it is turned on, the PAMD signal obtained at its first end is transmitted to point C.

The first end of the third capacitor C3 is electrically connected to point C, and the second end is electrically connected to the power line 80, and is configured to store the electrical signal at point C, that is, after the ninth transistor T9 transmits the PAMD signal to point C, the PAMD signal is stored, and after the ninth transistor T9 is turned off, the PAMD signal can still be provided to point C.

The control end of the tenth transistor T10 is electrically connected to point C, the first end thereof is electrically connected to the second end of the third capacitor C3 and the first end of the eighth transistor T8, the second end thereof is electrically connected to the first end of the light-emitting element LED, and is configured to generate a driving signal according to the electrical signal stored in the third capacitor C3, and transmit the driving signal to the light-emitting element LED to control the LED to emit light.

When the tenth transistor T10 generates a driving signal, the current value of the driving signal is I _T10 =k(V _GS -V _th ), wherein V _GS =V _PAMD -V _REF , and k is the current amplification factor of the transistor, which is determined by the characteristics of the transistor itself.

However, the tenth transistor that generates the driving signal in the pixel driving circuit is affected by the uniformity of the manufacturing process. During use, the threshold voltage value of the tenth transistor will drift, resulting in a change in the current value of the driving signal generated by the pixel driving circuit under the same PAMD signal drive, which ultimately causes uneven brightness of the micro LED display panel, poor display, and affects the picture quality.

In order to solve the above problems, the present application provides a display device to solve the technical problem of poor uniformity of micro-LED light emission based on PWM and PAM driving. The technical concept of the present application is to provide a display device, including a display panel, on which a plurality of gate lines 60, a plurality of data lines and a plurality of sub-pixel circuits are arranged, each sub-pixel circuit includes a pixel driving circuit and a light-emitting element, in the pixel driving circuit, an edge improvement circuit obtains a pulse width modulation signal, and outputs a compensation control signal according to the pulse width modulation signal, and a light-emitting threshold compensation circuit is electrically connected to the edge improvement circuit and the data line to obtain driving data and compensation control signals, and in the display phase of each display cycle, when the edge improvement circuit does not output the compensation control signal, the driving data after the threshold voltage of the driving transistor is used to generate a corresponding driving signal, and when the edge improvement circuit outputs the compensation control signal, the generation of the driving signal is stopped, and the light-emitting element is not affected by the drift of the threshold voltage during the light-emitting process, and the light-emitting intensity is only affected by the driving data when the light-emitting duration is consistent, thereby ensuring the uniformity of the light-emitting element during the display process.

The pixel driving circuit proposed in the present application is explained in detail below. FIG4 is a schematic diagram of the structure of a pixel driving circuit provided by the present application according to an exemplary embodiment. As shown in FIG4 , the pixel driving circuit 4032 provided by the present application includes an edge improvement circuit 901 and a light emission threshold compensation circuit 902.

The control end of the edge improvement circuit 901 is electrically connected to the gate line 60, and its input end is electrically connected to the power line 80 through point B. It is configured to obtain a pulse width modulation signal PWM from its control end, obtain a first power signal REF from its input end, and control its conduction state according to the pulse width modulation signal PWM and the first power signal REF. When it is turned on, it outputs a compensation control signal and transmits the compensation control signal from its output end to point C.

Among them, when the edge improvement circuit 901 is turned on according to the potential value of the input end of the input pulse width modulation signal, the first power supply signal REF is output from its output end, and the first power supply signal REF is determined as the compensation control signal; when the edge improvement circuit 901 is turned off according to the pulse width modulation signal PWM, the output end does not output the compensation control signal.

The first input terminal of the light emission threshold compensation circuit 902 is electrically connected to the power line 80 through point B, the second input terminal is electrically connected to the data line 50 through point A, and the control terminal is electrically connected to point C. The light emission threshold compensation circuit 902 includes a driving transistor T10.

The luminous threshold compensation circuit 902 is configured to obtain the first power supply signal REF from its first input terminal and the driving data from its second input terminal during the display stage of each display cycle, and when no compensation control signal is obtained from its control terminal, generate a corresponding driving signal using the driving data compensated for the threshold voltage of the driving transistor T10, and transmit the driving signal to point D from its output terminal.

More specifically, the third input terminal of the light emitting threshold compensation circuit 902 is electrically connected to the gate line 60, and is configured to obtain the first driving data PAMD from its second input terminal and the scanning signal SN from its third input terminal during the non-display phase of the display cycle, and under the control of the scanning signal SN, the first driving data PAMD is compensated by the threshold voltage of the driving transistor T10 to generate and store the second driving data;

In the display stage, when point C does not obtain the compensation control signal generated by the edge improvement circuit 901, the light emitting threshold compensation circuit 902 generates and outputs a corresponding driving signal from its output terminal according to the second driving data and the first power supply signal REF.

The first end of the light emitting element LED is electrically connected to the point D, and is configured to obtain a driving signal and emit light according to the driving signal.

Since the driving data has been compensated by the light-emitting threshold, the driving transistor offsets the threshold voltage compensated in the driving data with the threshold voltage of the driving transistor when generating a driving signal, so that the current value of the generated signal is independent of the threshold voltage. The light-emitting element is not affected by the drift of the threshold voltage during the light-emitting process, and the light-emitting intensity is only affected by the driving data when the light-emitting duration is consistent, thereby ensuring the uniformity of the light-emitting element during the display process.

The specific circuit structures of the edge improvement circuit 901 and the threshold compensation circuit 902 shown in Fig. 4 are explained below. Among them, the transistors in the circuit structure shown in Fig. 4 are all N-type transistors.

The edge improvement circuit 901 includes a seventh transistor T7, an eighth transistor T8 and a second capacitor C2.

The first end of the eighth transistor T8 serves as the input end of the edge improvement circuit 901 and is electrically connected to point B. The second end thereof is electrically connected to the first end of the seventh transistor T7. The control end thereof serves as the control end of the edge improvement circuit 901 and is electrically connected to the gate line 60. The eighth transistor T8 is configured to obtain the first power supply signal REF from the first end thereof and the second light-emitting control signal EM2 from the control end thereof, and the conduction state thereof is controlled by the second light-emitting control signal EM2.

More specifically, the eighth transistor T8 is configured to be turned on when the second light-emitting control signal EM2 is at a high level, transmitting the first power signal REF to the seventh transistor T7; and to be turned off when the second light-emitting control signal EM2 is at a low level, stopping transmitting the first power signal REF to the seventh transistor T7.

The control end of the seventh transistor T7 serves as the control end of the edge improvement circuit 901, and is electrically connected to the gate line 60 and the first end of the second capacitor C2. The second end of the seventh transistor T7 serves as the output end of the edge improvement circuit 901, and is electrically connected to point C. The transistor T7 is configured to obtain a pulse width modulation signal PWM from its control end, adjust the potential value of its control end according to the pulse width modulation signal PWM, and control its conduction state according to the potential value of its control end.

More specifically, the seventh transistor T7 is configured to be turned on when the potential of its control terminal is at a high level, and when the first power supply signal REF is obtained at its first terminal, the first power supply signal REF is transmitted to point C as a compensation control signal, and when the first power supply signal REF is not obtained at its first terminal, no signal is transmitted, and point C cannot obtain the compensation control signal from its second terminal; when the potential of its control terminal is at a low level, the seventh transistor T7 is turned off, no electrical signal is transmitted, and point C cannot obtain the compensation control signal from its second terminal.

The second end of the second capacitor C2 is electrically connected to the power line 80 , and is configured to obtain a pulse width modulation signal PWM from its first end, and adjust the voltage value of its first end according to the pulse width modulation signal PWM.

The light emitting threshold compensation circuit 902 includes a data input transistor T9, a driving transistor T10, a threshold compensation transistor T11 and a third capacitor C3.

The first end of the data input transistor T9 serves as the second input end of the light emitting threshold compensation circuit 902 , and is electrically connected to the data line 50 through point A. The second end thereof is electrically connected to the first end of the driving transistor T10 , and the control end thereof is electrically connected to the gate line 60 .

The data input transistor T9 is configured such that a first terminal thereof obtains the first driving data V _PAMD from the data line 50 , and a control terminal thereof obtains the scanning signal SN from the gate line 60 , and a conduction state thereof is controlled by the scanning signal SN.

More specifically, the data input transistor T9 is configured to be turned on when the scan signal SN is at a high level, and transmit the first drive data V _PAMD obtained at its first end to the drive transistor T10 ; and to be turned off when the scan signal SN is at a low level, and stop transmitting the first drive data V _PAMD .

The first end of the threshold compensation transistor T11 is electrically connected to the second end of the driving transistor T10 , and the second end is electrically connected to the control end of the driving transistor T10 . The control end serves as the third input end of the threshold compensation circuit 902 and is electrically connected to the gate line 60 .

The threshold compensation transistor T11 is configured such that its control terminal obtains the scanning signal SN from the gate line 60, and its conduction state is controlled by the scanning signal SN. When the scanning signal SN is at a high level, the threshold compensation transistor T11 is turned on, and the second terminal and the control terminal of the driving transistor T10 are short-circuited; when the scanning signal SN is at a low level, the threshold compensation transistor T11 is turned off, and the circuit structure between the second terminal and the control terminal of the driving transistor T10 is disconnected.

The control end of the driving transistor T10, as the control end of the threshold compensation circuit 902, and the second end of the threshold compensation transistor T11 are electrically connected to point C, and are configured to obtain the potential value of the point from point C, and control its conduction state by the voltage value of point C and the voltage value of its first end.

More specifically, the driving transistor T10 is configured to be turned on when the potential value of point C is a high level and the difference between the potential value of point C and the potential value of its first end is greater than or equal to the threshold voltage of the driving transistor T10, and transmit the electrical signal obtained by its first end to its second end; and to be turned off when the potential value of point C is a low level and/or the difference between the potential value of point C and the potential value of its first end is less than the threshold voltage of the driving transistor T10, and stop the transmission of the electrical signal between its first end and the second end.

Based on the circuit structure composed of the driving transistor T10 and the threshold compensation transistor T11, when the threshold compensation transistor T11 and the driving transistor T10 are both turned on, they form a diode structure, and the potential value of the control end of the driving transistor T10 is adjusted following the electrical signal obtained by its first end, and the potential value of point C is adjusted according to the potential value of its control end.

When the first terminal of the driving transistor T10 obtains the first driving data V _PAMD transmitted by the data input transistor T9 , the control terminal thereof generates the second driving data according to the first driving data V _PAMD .

More specifically, when the first driving data is V _PAMD , the second driving data is V _PAMD +V _th10 , wherein V _th10 is the threshold voltage of the driving transistor T10 .

The first end of the third capacitor C3 is electrically connected to point C, and the second end thereof serves as the first input end of the luminous threshold compensation circuit 902, and is electrically connected to the power line 80 through point B. The second end thereof is configured to obtain the first power signal REF from the data line 80 as a stable power reference, and the first end thereof obtains an electrical signal from point C, and adjusts the potential value of the first end thereof according to the electrical signal, and provides the potential value of the first end thereof to point C when no electrical signal is generated at point C, so as to maintain the potential value of point C.

The light emission threshold compensation circuit 902 further includes a first conduction control transistor T13 and a second conduction control transistor T14.

The first end of the first conduction control transistor T13 is electrically connected to the power line 80 as the first input end of the threshold compensation circuit 902 , the second end thereof is electrically connected to the first end of the driving transistor T10 , and the control end thereof is electrically connected to the gate line 60 .

The first conduction control transistor T13 is configured such that a first terminal thereof obtains a first power signal REF from the power line 80 , and a control terminal thereof obtains a first light emission control signal EM1 from the gate line 60 , and a conduction state thereof is controlled by the first light emission control signal EM1 .

More specifically, the first conduction control transistor T13 is configured to be turned on when the first light emitting control signal EM1 is at a high level, transmitting the first power signal REF to the driving transistor T10; and to be turned off when the first light emitting control signal EM1 is at a low level, stopping the transmission of the first power signal REF.

The driving transistor T10 is also configured such that its control end obtains the second driving data from the third capacitor C3, and its first end obtains the first power supply signal REF transmitted by the first conduction control transistor T1, and when the difference between the second driving data and the first power supply signal REF is greater than or equal to the threshold voltage of the driving transistor T10, and the threshold compensation transistor T11 is turned off, a driving signal is generated according to the second driving data and the first power supply signal REF.

The current value of the driving signal is I _T10 =k(V _GS -V _th10 ), wherein V _GS =V _PAMD +V _th10 -V _REF , then I _T10 =k(V _PAMD -V _REF ), and the current value is independent of the threshold voltage V _th10 of the driving transistor T10, so the current is no longer affected by the threshold voltage drift.

A first end of the second conduction control transistor T14 is electrically connected to the second end of the driving transistor T10 , a second end thereof is electrically connected to the point D, and a control end thereof is electrically connected to the gate line 60 .

The second conduction control transistor T14 is configured such that a control terminal thereof obtains the first light emitting control signal EM1 from the gate line 60 , and a conduction state thereof is controlled by the first light emitting control signal EM1 .

More specifically, the second conduction control transistor T14 is configured to be turned on when the first light-emitting control signal EM1 is at a high level, and when its first end obtains the driving signal transmitted by the driving transistor T10, it transmits the driving signal to point D; and to be turned off when the first light-emitting control signal EM1 is at a low level, and stop its first end from transmitting the electrical signal to point D.

The first end of the light emitting element LED is electrically connected to point D, and the second end is electrically connected to the power line 80. The second end of the light emitting element LED is configured to obtain the second power signal VDD from the power line 80, and the first end of the light emitting element LED obtains the driving signal from point D, and emits light under the driving of the driving signal. The light intensity of the light emitting element LED is related to the current value of the driving signal.

With the same luminous time and luminous efficiency, the greater the current value, the stronger the light intensity of the light-emitting element LED.

The light emission threshold compensation circuit 902 further includes a first reset transistor T12.

The first end of the first reset transistor T12 is electrically connected to the power line 80, the second end thereof is electrically connected to point C, and the control end thereof is electrically connected to the gate line 60. The first reset transistor T12 is configured such that its first end obtains the second power signal VDD from the power line 80, and its control end obtains the reset signal RESET from the gate line 60, and its conduction state is controlled by the reset signal RESET.

More specifically, the first reset transistor T12 is configured to be turned on when the reset signal RESET is at a high level, transmitting the second power signal VDD obtained by its first end to point C; and to be turned off when the reset signal RESET is at a low level, stopping its first end from transmitting electrical signals to point C.

In the circuit structure corresponding to this embodiment, the first end of the transistor is the source, the second end is the drain, and the control end is the gate.

The circuit structure shown in FIG. 4 is driven by the driving signal timing diagram shown in FIG. 5 .

The operation process of the circuit structure shown in FIG4 is explained below.

The circuit operation in a display cycle is explained below. A display cycle T includes a non-display phase and a display phase in sequence. The non-display phase includes a reset phase T1 and a data writing phase T2 in sequence. The display phase includes a light-emitting phase T3 and a non-light-emitting phase T4.

In the period corresponding to the reset phase T1 in the driving signal timing diagram, the reset signal RESET is at a high level, the scan signal SN is at a low level, the first light emitting control signal EM1 is at a low level, and the second light emitting control signal EM2 is at a low level.

Since the second light emitting control signal EM2 is at a low level, the eighth transistor T8 is turned off, so the eighth transistor T8 cannot transmit the first power signal REF to the seventh transistor T7.

When the current display cycle is the first display cycle, the first end of the second capacitor C2 is at a low level, the seventh transistor T7 is turned off, and no electrical signal is transmitted.

When the current display cycle is not the first display cycle, the first terminal of the second capacitor C2 is at a high level, that is, the potential at point S is at a high level, and the seventh transistor T7 is turned on. The potential value of the first terminal of the second capacitor C2 is determined by the previous display cycle.

Since the first end of the seventh transistor T7 does not obtain the first power signal REF, the second end thereof cannot transmit the first power signal REF either. Therefore, the second end thereof does not transmit the compensation control signal to point C and does not change the potential value of point C.

Since the reset signal RESET is at a high level, the first reset transistor T12 is turned on, so that the second terminal thereof can transmit the second power signal VDD to the point C.

Therefore, the first end of the third capacitor C3 obtains the second power signal VDD, and adjusts the potential value of the first end thereof to a corresponding potential value to store the second power signal VDD.

Since the first light emitting control signal EM1 is at a low level, the first conduction control transistor T13 is turned off and cannot transmit the first power signal REF to the driving transistor T10 . Therefore, the driving transistor T10 cannot generate a driving signal according to the first power signal.

Since the scan signal SN is at a low level, the data input transistor T9 cannot transmit the first driving data V _PAMD to the driving transistor T10 , and thus the driving transistor T10 cannot generate a driving signal according to the first driving data V _PAMD .

Therefore, the point D cannot obtain the driving signal, and the light emitting element LED does not emit light without the driving signal.

In the period corresponding to the data writing phase T2 in the driving signal timing diagram, the scanning signal SN is at a high level, the reset signal RESET is at a low level, the first light emitting control signal EM1 is at a low level, and the second light emitting control signal EM2 is at a low level.

Since the level state of the second light emitting control signal EM2 is consistent with the level state of the reset stage T1, the state of the eighth transistor T8 remains unchanged, and thus, point C does not obtain the compensation control signal.

The potential at point S shown in the figure is at a high level.

Since the reset signal RESET is at a low level, the first reset transistor T12 is turned off, and the potential value of the point C is no longer adjusted following the potential value of the second power signal VDD.

Since the first light emitting control signal EM1 is at a low level, the first conduction control transistor T13 remains in the off state, and therefore, the first end of the driving transistor T10 does not obtain the first power supply signal REF.

Since the scan signal SN is at a high level, the data input transistor T9 is turned on, and the first driving data V _PAMD obtained at the first end thereof is transmitted to the first end of the driving transistor T10 .

Since the scanning signal SN is at a high level, the threshold compensation transistor T11 is turned on, and the control terminal and the second terminal of the driving transistor T10 are short-circuited.

Since the control terminal and the second terminal of the driving transistor T10 are short-circuited, it forms a diode structure with the threshold compensation transistor T11 , and the difference between the potential values of the control terminal and the second terminal is the threshold voltage of the driving transistor T10 .

Since the potential value of the first terminal of the driving transistor T10 is the first driving data V _PAMD , the voltage value of the control terminal thereof is the second driving data, and the second driving data is V _PAMD +V _th10 .

Since the potential value of the control terminal of the driving transistor T10 changes, the potential values of the point C and the first terminal of the third capacitor C3 change accordingly and are also adjusted to the same potential value. The third capacitor C3 then stores the second driving data.

Since the first light emitting control signal EM1 is at a low level, the second conduction control transistor T14 remains in the off state and cannot transmit an electrical signal. Therefore, the point D still does not obtain a driving signal.

In the above technical solution, the luminous threshold compensation circuit uses the first reset transistor to transmit and store the second power supply signal in the non-display stage, so that the driving transistor is always kept in the on state in the non-display stage, so that the data writing circuit composed of the driving transistor, the threshold compensation transistor, the driving transistor and the third capacitor is turned on in the data writing stage, and the first driving data obtained by the circuit is used to generate and store the second driving data, so that the luminous threshold compensation circuit uses the second driving data to generate a driving signal that is independent of the threshold voltage in the subsequent luminous stage.

The time period corresponding to the light-emitting stage T3 in the driving signal timing diagram includes a first light-emitting stage T31 , a second light-emitting stage T32 and a third light-emitting stage T33 .

In the first light-emitting stage T31, the first light-emitting control signal EM1 is at a high level, the reset signal RESET is at a low level, the scanning signal SN is at a low level, the pulse width modulation signal PWM is at a low level, the second light-emitting control signal EM2 is at a low level, and the first power supply signal REF is at a low level;

Since the second light emitting control signal EM2 is at a low level, the eighth transistor T8 is turned off, so the eighth transistor T8 cannot transmit the first power signal REF to the seventh transistor T7.

Since the pulse width modulation signal PWM is adjusted from a high level to a low level at the beginning of the first light-emitting stage T31, the second capacitor C2 is discharged, and the potential value of the first end of the second capacitor C2 gradually decreases. However, the potential of the point S is still at a high level in this stage.

In the first light emitting stage T31 , the potential value of the first end of the second capacitor C2 can still keep the seventh transistor T7 turned on.

Since the eighth transistor T8 is turned off, the seventh transistor T7 still cannot transmit the first power signal REF to point C. Therefore, the second end thereof does not transmit the compensation control signal to point C and does not change the potential value of point C.

The duration of the first light emitting stage T31 is greater than or equal to the duration of the voltage value of the first end of the second capacitor C2 being discharged to the voltage value that turns off the seventh transistor T7.

Since the scan signal SN is at a low level, the data input transistor T9 is turned off, and stops transmitting the first driving data V _PAMD to the driving transistor T10 .

Since the first light emitting control signal EM1 is at a high level, the first conduction control transistor T13 is turned on to transmit the first power signal REF to the first end of the driving transistor T10.

Since the scanning signal SN is at a low level, the threshold compensation transistor T11 is turned off, and the potential values of the control terminal and the second terminal of the driving transistor T10 are irrelevant.

Since the control terminal of the driving transistor T10 can obtain the second driving data from the first terminal of the third capacitor C3 and the difference between the second driving data and the first power signal REF is greater than the threshold voltage, the driving transistor T10 is turned on.

The driving transistor T10 generates a driving signal according to the second driving data and the first power signal REF, and transmits the driving signal to the second conduction control transistor T14.

The current value of the driving signal is k( _VPAMD + _Vth10 - _VREF - _Vth10 ), that is, k( _VPAMD - _VREF ). The current value is independent of the threshold voltage and is no longer affected by the voltage drift.

Since the first light emitting control signal EM1 is at a high level, the second conduction control transistor T14 is turned on to transmit the driving signal to the point D.

The light emitting element LED emits light under the drive of the driving signal, and the light intensity is related to the current value.

It should be noted that, in this embodiment, the current direction of the driving signal is from the second terminal to the first terminal of the transistor.

In the second light-emitting stage T32, the first light-emitting control signal EM1 is high, the second light-emitting control signal EM2 is high, the pulse width modulation signal PWM is low, the reset signal RESET is low, the scanning signal SN is low, and the first power supply signal REF is low;

Since the second light emitting control signal EM2 is at a high level, the eighth transistor T8 is turned on to transmit the first power signal REF to the seventh transistor T7.

Since the potential at the point S is adjusted to a low level according to the pulse width modulation signal PWM, the seventh transistor T7 is turned off, and the first power signal REF cannot be transmitted to the point C, and no compensation control signal is output.

Since the level states of other signals are the same as the level states of corresponding signals in the first light-emitting stage T31, the states of corresponding devices remain unchanged, and point D still transmits the driving signal to the light-emitting element LED, and the light-emitting element LED emits light according to the driving signal.

In the third light emitting stage T33 , the first light emitting control signal EM1 is at a high level, the second light emitting control signal EM2 is at a high level, the pulse width modulation signal PWM is at a high level, the reset signal RESET is at a low level, and the scanning signal SN is at a low level.

Since the second light emitting control signal EM2 is at a high level, the eighth transistor T8 is turned on, and thus the eighth transistor T8 transmits the first power signal REF to the seventh transistor T7.

Since the pulse width modulation signal PWM is adjusted from a low level to a high level at the beginning of the third light-emitting stage T33, the second capacitor C2 is charged, and the potential value of the first end of the second capacitor C2 gradually increases, but the potential of the point S is still at a low level.

In the third light emitting stage T33 , the potential value of the first end of the second capacitor C2 can still keep the seventh transistor T7 turned off.

Since the seventh transistor T8 is turned off, the seventh transistor T7 still cannot transmit the first power signal REF to point C. Therefore, the second end thereof does not output the compensation control signal to point C, and the potential value of point C does not change.

The duration of the third light emitting stage T33 is greater than or equal to the duration of the voltage value of the first end of the second capacitor C2 being charged to the voltage value that turns on the seventh transistor T7.

Since the level states of other signals are the same as the level states of corresponding signals in the second light-emitting stage T32, the states of corresponding devices remain unchanged, and point D still transmits the driving signal to the light-emitting element LED, and the light-emitting element LED emits light according to the driving signal.

In the period corresponding to the non-luminous phase T4 in the driving signal timing diagram, the first luminous control signal EM1 is high, the second luminous control signal EM2 is high, the pulse width modulation signal PWM is high, the reset signal RESET is low, and the scanning signal SN is low.

Since the second light emitting control signal EM2 is at a high level, the eighth transistor T8 is turned on to transmit the first power signal REF to the seventh transistor T7.

Since the pulse width modulation signal PWM is at a high level, the point S follows the charging of the second capacitor C2 and is adjusted to a high level. The seventh transistor T7 is turned on to transmit the first power signal REF to the point C.

Point C outputs the compensation control signal.

Since the compensation control signal transmitted at point C is the first power signal REF, the potential value of the first end of the third capacitor C3 is adjusted following the potential value of the first power signal REF.

Since the first light emitting control signal EM1 is at a high level, the first conduction control transistor T13 is turned on to transmit the first power signal REF to the first end of the driving transistor T10.

Since the electric signal obtained by the control terminal of the driving transistor T10 is also the first power supply signal REF, the difference between the potential value of the control terminal and the potential value of the first terminal is smaller than the threshold voltage, the driving transistor T10 is turned off and stops generating the driving signal.

Although the first light emitting control signal EM1 is at a high level and the second conduction control transistor T14 is turned on, the first end thereof no longer obtains the driving signal, and thus the driving signal cannot be transmitted to the point D.

Since the light emitting element LED no longer receives the driving signal, the light emitting element LED stops emitting light.

In the above technical solution, the light-emitting threshold compensation circuit controls the light-emitting duration of the light-emitting element according to the compensation control signal obtained during the light-emitting stage. During the light-emitting process, the light-emitting circuit composed of the first conduction control transistor, the driving transistor and the first conduction control transistor is turned on. The conduction transistor determines the current value flowing through the light-emitting circuit through the first power supply signal obtained and the second driving data stored in the data writing stage, as well as the threshold voltage, thereby determining the light-emitting intensity of the light-emitting element. Since the second driving data is compensated by the threshold voltage when it is generated, the above current is no longer affected by the threshold voltage, thereby ensuring the display uniformity of the light-emitting element.

Fig. 6 is a circuit structure diagram of a pixel driving circuit provided by the present application according to another exemplary embodiment. The circuit structure shown in Fig. 6 includes an edge improvement circuit 901 and a threshold compensation circuit 902, and the edge improvement circuit 901 and the threshold compensation circuit 902 are composed of P-type transistors.

The control end of the edge improvement circuit 901 is electrically connected to the gate line 60, and its input end is electrically connected to the power line 80 through point B. It is configured to obtain a pulse width modulation signal PWM from its control end, obtain a first power supply signal VDD from its input end, and generate a compensation control signal based on the pulse width modulation signal PWM and the first power supply signal VDD, and transmit the compensation control signal from its output end to point C.

Among them, when the edge improvement circuit 901 is turned on according to the pulse width modulation signal PWM, the first power supply signal VDD is output from its output end, and the first power supply signal VDD is determined as the compensation control signal; when the edge improvement circuit 901 is turned off according to the pulse width modulation signal PWM, the compensation control signal is not output from its output end.

The first input terminal of the light emission threshold compensation circuit 902 is electrically connected to the power line 80 through point B, the second input terminal is electrically connected to the data line 50 through point A, and the control terminal is electrically connected to point C. The light emission threshold compensation circuit 902 includes a driving transistor T10.

The light-emitting threshold compensation circuit 902 is configured to obtain the first power supply signal VDD from its first input terminal and the driving data from its second input terminal during the light-emitting phase of the display phase, and the control terminal thereof does not obtain the compensation control signal, and generates a corresponding driving signal using the driving data compensated by the threshold voltage of the driving transistor T10, and transmits the driving signal to point D from its output terminal. In the non-light-emitting phase of the display phase, the compensation control signal is obtained, and the generation of the driving signal is stopped according to the compensation control signal.

More specifically, the third input terminal of the light emitting threshold compensation circuit 902 is electrically connected to the gate line 60, and is configured to obtain the first driving data PAMD from its second input terminal and the scanning signal SN from its third input terminal during the non-display phase of the display cycle, and under the control of the scanning signal SN, the first driving data PAMD is compensated by the threshold voltage of the driving transistor T10 to generate and store the second driving data;

In the display stage, when the point C does not transmit the compensation control signal, a corresponding driving signal is generated according to the second driving data and the first power signal VDD and output from its output terminal.

The first end of the light emitting element LED is electrically connected to the point D, and is configured to obtain a driving signal and emit light according to the driving signal.

The edge improvement circuit 901 includes a seventh transistor T7, an eighth transistor T8 and a second capacitor C2.

The first end of the eighth transistor T8 serves as the input end of the edge improvement circuit 901 and is electrically connected to point B, the second end thereof is electrically connected to the first end of the seventh transistor T7, the control end thereof serves as the control end of the edge improvement circuit 901 and is electrically connected to the gate line 60, and is configured to obtain the first power supply signal VDD from the first end thereof and the second light-emitting control signal EM2 from the control end thereof, and the conduction state thereof is controlled by the second light-emitting control signal EM2.

More specifically, the eighth transistor T8 is configured to be turned on when the second light-emitting control signal EM2 is at a low level, transmitting the first power signal VDD to the seventh transistor T7; and to be turned off when the second light-emitting control signal EM2 is at a high level, stopping transmitting the first power signal REF to the seventh transistor T7.

The control end of the seventh transistor T7 serves as the control end of the edge improvement circuit 901, and is electrically connected to the gate line 60 and the first end of the second capacitor C2. The second end of the seventh transistor T7 serves as the output end of the edge improvement circuit 901, and is electrically connected to point C. The transistor T7 is configured to obtain a pulse width modulation signal PWM from its control end, and its conduction state is controlled by the pulse width modulation signal PWM.

More specifically, the seventh transistor T7 is configured to be turned on when the potential of its control terminal is at a low level, and when the first power signal VDD is obtained at its first terminal, the first power signal VDD is transmitted to point C as a compensation control signal, and when the first power signal VDD is not obtained at its first terminal, no signal is transmitted, and point C will not obtain the compensation control signal from its second terminal; when the potential of its control terminal is at a high level, the seventh transistor T7 is turned off, no electrical signal is transmitted, and point C will not obtain the compensation control signal from its second terminal.

The second end of the second capacitor C2 is electrically connected to the power line 80 , and is configured to obtain a pulse width modulation signal PWM from its first end, and adjust the voltage value of its first end according to the pulse width modulation signal PWM.

The light emission threshold compensation circuit 902 includes a data input transistor T9, a driving transistor T10, a threshold compensation transistor T11 and a third capacitor C3.

The first end of the data input transistor T9 serves as the second input end of the light emitting threshold compensation circuit 902 , and is electrically connected to the data line 50 through point A. The second end thereof is electrically connected to the first end of the driving transistor T10 , and the control end thereof is electrically connected to the gate line 60 .

The data input transistor T9 is configured such that a first terminal thereof obtains the first driving data V _PAMD from the data line 50 , and a control terminal thereof obtains the scanning signal SN from the gate line 60 , and a conduction state thereof is controlled by the scanning signal SN.

More specifically, the data input transistor T9 is configured to be turned on when the scan signal SN is at a low level, and transmit the first driving data V _PAMD obtained at its first end to the driving transistor T10 ; and to be turned off when the scan signal SN is at a high level, and stop transmitting the first driving data V _PAMD .

The first end of the threshold compensation transistor T11 is electrically connected to the second end of the driving transistor T10 , and the second end is electrically connected to the control end of the driving transistor T10 . The control end serves as the third input end of the threshold compensation circuit 902 and is electrically connected to the gate line 60 .

The threshold compensation transistor T11 is configured such that its control terminal obtains the scanning signal SN from the gate line 60, and its conduction state is controlled by the scanning signal SN. When the scanning signal SN is at a low level, the threshold compensation transistor T11 is turned on, and the second terminal and the control terminal of the driving transistor T10 are short-circuited; when the scanning signal SN is at a high level, the threshold compensation transistor T11 is turned off, and the circuit structure between the second terminal and the control terminal of the driving transistor T10 is disconnected.

The control end of the driving transistor T10, as the control end of the threshold compensation circuit 902, and the second end of the threshold compensation transistor T11 are electrically connected to point C, and are configured to obtain the potential value of the point from point C, and control its conduction state by the voltage value of point C and the voltage value of its first end.

More specifically, the driving transistor T10 is configured to be turned on when the potential value of point C is a low level and the difference between the potential value of point C and the potential value of its first end is greater than or equal to the threshold voltage of the driving transistor T10, and transmit the electrical signal obtained by its first end to its second end; and to be turned off when the potential value of point C is a high level and/or the difference between the potential value of point C and the potential value of its first end is less than the threshold voltage of the driving transistor T10, and stop the transmission of the electrical signal between its first end and the second end.

Based on the circuit structure composed of the driving transistor T10 and the threshold compensation transistor T11, when the threshold compensation transistor T11 and the driving transistor T10 are both turned on, they form a diode structure, and the potential value of the control end of the driving transistor T10 is adjusted following the electrical signal obtained by its first end, and the potential value of point C is adjusted according to the potential value of its control end. Among them, the potential value of the control end of the driving transistor T10.

When the first terminal of the driving transistor T10 obtains the first driving data V _PAMD transmitted by the data input transistor T9 , the control terminal thereof generates the second driving data according to the first driving data V _PAMD .

More specifically, when the first driving data is V _PAMD , the second driving data is V _PAMD +V _th10 , wherein V _th10 is the threshold voltage of the driving transistor T10 .

The first end of the third capacitor C3 is electrically connected to point C, and the second end thereof serves as the first input end of the luminous threshold compensation circuit 902, and is electrically connected to the power line 80 through point B. The third capacitor C3 is configured such that its second end obtains the first power signal VDD from the data line 80 as a stable power reference, and its first end obtains an electrical signal from point C, and adjusts the potential value of its first end according to the electrical signal, and provides the potential value of its first end to point C when no electrical signal is generated at point C to maintain the potential value of point C.

The light emission threshold compensation circuit 902 further includes a first conduction control transistor T13 and a second conduction control transistor T14.

The first end of the first conduction control transistor T13 is electrically connected to the power line 80 as the first input end of the threshold compensation circuit 902 , the second end thereof is electrically connected to the first end of the driving transistor T10 , and the control end thereof is electrically connected to the gate line 60 .

The first conduction control transistor T13 is configured such that a first terminal thereof obtains a first power signal VDD from the power line 80 , and a control terminal thereof obtains a first light emission control signal EM1 from the gate line 60 , and a conduction state thereof is controlled by the first light emission control signal EM1 .

More specifically, the first conduction control transistor T13 is configured to be turned on when the first light emitting control signal EM1 is at a low level, transmitting the first power supply signal VDD to the driving transistor T10; and to be turned off when the first light emitting control signal EM1 is at a high level, stopping the transmission of the first power supply signal VDD.

The driving transistor T10 is also configured such that its control end obtains the second driving data from the third capacitor C3, and its first end obtains the first power supply signal VDD transmitted by the first conduction control transistor T1, and when the difference between the second driving data and the first power supply signal VDD is greater than or equal to the threshold voltage of the driving transistor T10, and the threshold compensation transistor T11 is turned off, a driving signal is generated according to the second driving data and the first power supply signal VDD.

The current value of the driving signal is I _T10 =k(V _GS -V _th10 ), wherein V _GS =V _PAMD +V _th10 -V _VDD , then I _T10 =k(V _PAMD -V _VDD ), and the current value is independent of the threshold voltage V _th10 of the driving transistor T10, so the current is no longer affected by the threshold voltage drift.

A first end of the second conduction control transistor T14 is electrically connected to the second end of the driving transistor T10 , a second end thereof is electrically connected to the point D, and a control end thereof is electrically connected to the gate line 60 .

The second conduction control transistor T14 is configured such that a control terminal thereof obtains the first light emitting control signal EM1 from the gate line 60 , and a conduction state thereof is controlled by the first light emitting control signal EM1 .

More specifically, the second conduction control transistor T14 is configured to be turned on when the first light-emitting control signal EM1 is at a low level, and when its first end obtains the driving signal transmitted by the driving transistor T10, it transmits the driving signal to point D; and to be turned off when the first light-emitting control signal EM1 is at a high level, and stop its first end from transmitting the electrical signal to point D.

The first end of the light emitting element LED is electrically connected to point D, and the second end is electrically connected to the power line 80. The second end is configured to obtain the second power signal REF from the power line 80, and the first end is configured to obtain the driving signal from point D, and emit light under the driving of the driving signal. The light intensity of the light emitting element LED is related to the current value of the driving signal.

With the same luminous time and luminous efficiency, the greater the current value, the stronger the light intensity of the light-emitting element LED.

The light emission threshold compensation circuit 902 further includes a first reset transistor T12.

The first end of the first reset transistor T12 is electrically connected to the power line 80, the second end thereof is electrically connected to point C, and the control end thereof is electrically connected to the gate line 60. The first reset transistor T12 is configured such that its first end obtains the second power signal REF from the power line 80, and its control end obtains the reset signal RESET from the gate line 60, and its conduction state is controlled by the reset signal RESET.

More specifically, the first reset transistor T12 is configured to be turned on when the reset signal RESET is at a low level, transmitting the second power signal REF obtained by its first end to point C; and to be turned off when the reset signal RESET is at a high level, stopping its first end from transmitting the electrical signal to point C.

In the circuit structure corresponding to this embodiment, the first end of the transistor is the source, the second end is the drain, and the control end is the gate.

The circuit structure shown in FIG. 7 is driven by the driving signal timing diagram shown in FIG. 6 .

The operation process of the circuit structure shown in FIG. 7 is explained below.

The circuit operation in a display cycle is explained below. A display cycle T includes a non-display phase and a display phase in sequence. The non-display phase includes a reset phase T1 and a data writing phase T2 in sequence. The display phase includes a light-emitting phase T3 and a non-light-emitting phase T4.

In the period corresponding to the reset phase T1 in the driving signal timing diagram, the reset signal RESET is at a low level, the scanning signal SN is at a high level, the first light emitting control signal EM1 is at a high level, and the second light emitting control signal EM2 is at a high level.

Since the second light emitting control signal EM2 is at a high level, the eighth transistor T8 is turned off, so the eighth transistor T8 cannot transmit the first power signal VDD to the seventh transistor T7.

Since the first end of the second capacitor C2 is at a low level, that is, the potential at the point S shown in the figure is at a low level, the seventh transistor T7 is turned off and does not transmit an electrical signal.

Since the first end of the seventh transistor T7 does not obtain the first power signal VDD, the second end thereof cannot transmit the first power signal VDD either. Therefore, the second end thereof does not transmit the compensation control signal to point C and does not change the potential value of point C.

Since the reset signal RESET is at a low level, the first reset transistor T12 is turned on, so that the second terminal thereof can transmit the second power signal REF to the point C.

Therefore, the first end of the third capacitor C3 obtains the second power signal REF, and adjusts the potential value of the first end thereof to a corresponding potential value to store the second power signal REF.

Since the first light emitting control signal EM1 is at a high level, the first conduction control transistor T13 is turned off and cannot transmit the first power signal VDD to the driving transistor T10 . Therefore, the driving transistor T10 cannot generate a driving signal according to the first power signal.

Since the scan signal SN is at a high level, the data input transistor T9 cannot transmit the first driving data V _PAMD to the driving transistor T10 , and thus the driving transistor T10 cannot generate a driving signal according to the first driving data V _PAMD .

Therefore, the point D cannot obtain the driving signal, and the light emitting element LED does not emit light without the driving signal.

In the period corresponding to the data writing phase T2 in the driving signal timing diagram, the scanning signal SN is at a low level, the reset signal RESET is at a high level, the first light emitting control signal EM1 is at a high level, and the second light emitting control signal EM2 is at a high level.

Since the level state of the second light emitting control signal EM2 is consistent with the level state of the reset stage T1, the state of the eighth transistor T8 remains unchanged, and thus, point C still does not obtain the compensation control signal.

The potential at point S shown in the figure is at a low level.

Since the reset signal RESET is at a high level, the first reset transistor T12 is turned off, and the potential value of the point C is no longer adjusted following the potential value of the second power signal REF.

Since the first light emitting control signal EM1 is at a high level, the first conduction control transistor T13 remains in the off state, and therefore, the first end of the driving transistor T10 does not obtain the first power signal VDD.

Since the scan signal SN is at a low level, the data input transistor T9 is turned on, and the first driving data V _PAMD obtained at the first end thereof is transmitted to the first end of the driving transistor T10 .

Since the scanning signal SN is at a low level, the threshold compensation transistor T11 is turned on, and the control terminal and the second terminal of the driving transistor T10 are short-circuited.

Since the control terminal and the second terminal of the driving transistor T10 are short-circuited, it forms a diode structure with the threshold compensation transistor T11 , and the difference between the potential values of the control terminal and the second terminal is the threshold voltage of the driving transistor T10 .

Since the potential value of the first terminal of the driving transistor T10 is the first driving data V _PAMD , the voltage value of the control terminal thereof is the second driving data, and the second driving data is V _PAMD +V _th10 .

Since the potential value of the control terminal of the driving transistor T10 changes, the potential values of the point C and the first terminal of the third capacitor C3 change accordingly and are also adjusted to the same potential value. The third capacitor C3 then stores the second driving data.

Since the first light emitting control signal EM1 is at a high level, the second conduction control transistor T14 remains in the off state and cannot transmit an electrical signal. Therefore, the point D still does not obtain a driving signal.

In the above technical solution, the luminous threshold compensation circuit uses the first reset transistor to transmit and store the second power supply signal in the non-display stage, so that the driving transistor is always kept in the on state in the non-display stage, so that the data writing circuit composed of the driving transistor, the threshold compensation transistor, the driving transistor and the third capacitor is turned on in the data writing stage, and the first driving data obtained by the circuit is used to generate and store the second driving data, so that the luminous threshold compensation circuit uses the second driving data to generate a driving signal that is independent of the threshold voltage in the subsequent luminous stage.

The time period corresponding to the light-emitting stage T3 in the driving signal timing diagram includes a first light-emitting stage T31 , a second light-emitting stage T32 and a third light-emitting stage T33 .

In the first light-emitting stage T31, the first light-emitting control signal EM1 is at a low level, the reset signal RESET is at a high level, the scanning signal SN is at a high level, the pulse width modulation signal PWM is at a high level, the second light-emitting control signal EM2 is at a high level, and the first power supply signal VDD is at a high level;

Since the second light emitting control signal EM2 is at a high level, the eighth transistor T8 is turned off, so the eighth transistor T8 cannot transmit the first power signal VDD to the seventh transistor T7.

Since the pulse width modulation signal PWM is adjusted from a low level to a high level at the beginning of the first light-emitting stage T31, the second capacitor C2 is discharged, and the potential value of the first end of the second capacitor C2 gradually decreases. However, the potential of the point S is still at a low level in this stage.

In the first light emitting stage T31 , the potential value of the first end of the second capacitor C2 can still keep the seventh transistor T7 turned on.

Since the eighth transistor T8 is turned off, the seventh transistor T7 still cannot transmit the first power signal VDD to point C. Therefore, the second end thereof does not transmit the compensation control signal to point C and does not change the potential value of point C.

The duration of the first light emitting stage T31 is greater than or equal to the duration of the voltage value of the first end of the second capacitor C2 being discharged to the voltage value that turns off the seventh transistor T7.

Since the scan signal SN is at a high level, the data input transistor T9 is turned off, and stops transmitting the first driving data V _PAMD to the driving transistor T10 .

Since the first light emitting control signal EM1 is at a low level, the first conduction control transistor T13 is turned on to transmit the first power signal VDD to the first end of the driving transistor T10.

Since the scanning signal SN is at a high level, the threshold compensation transistor T11 is turned off, and the potential values of the control terminal and the second terminal of the driving transistor T10 are irrelevant.

Since the control end of the driving transistor T10 can obtain the second driving data from the first end of the third capacitor C3 and the difference between the second driving data and the first power signal VDD is greater than the threshold voltage, the driving transistor T10 is turned on.

The driving transistor T10 generates a driving signal according to the second driving data and the first power signal VDD, and transmits the driving signal to the second conduction control transistor T14.

The current value of the driving signal is k( _VPAMD + _Vth10 - _VVDD - _Vth10 ), that is, k( _VPAMD - _VVDD ). The current value is independent of the threshold voltage and is no longer affected by the voltage drift.

Since the first light emitting control signal EM1 is at a low level, the second conduction control transistor T14 is turned on to transmit the driving signal to the point D.

The light emitting element LED emits light under the drive of the driving signal, and the light intensity is related to the current value.

It should be noted that, in this embodiment, the current direction of the driving signal is from the second terminal to the first terminal of the transistor.

In the second light-emitting stage T32, the first light-emitting control signal EM1 is at a low level, the second light-emitting control signal EM2 is at a low level, the pulse width modulation signal PWM is at a high level, the reset signal RESET is at a high level, the scanning signal SN is at a high level, and the first power supply signal VDD is at a high level;

Since the second light emitting control signal EM2 is at a low level, the eighth transistor T8 is turned on to transmit the first power signal VDD to the seventh transistor T7.

Since the potential at point S is adjusted to a high level according to the pulse width modulation signal PWM, the seventh transistor T7 is turned off and the first power signal VDD cannot be transmitted to point C, and no compensation control signal is output.

Since the level states of other signals are the same as the level states of corresponding signals in the first light-emitting stage T31, the states of corresponding devices remain unchanged, and point D still transmits the driving signal to the light-emitting element LED, and the light-emitting element LED emits light according to the driving signal.

In the third light emitting stage T33 , the first light emitting control signal EM1 is at a low level, the second light emitting control signal EM2 is at a low level, the pulse width modulation signal PWM is at a low level, the reset signal RESET is at a high level, and the scanning signal SN is at a high level.

Since the second light emitting control signal EM2 is at a low level, the eighth transistor T8 is turned on, and thus the eighth transistor T8 transmits the first power signal VDD to the seventh transistor T7.

Since the pulse width modulation signal PWM is adjusted from a high level to a low level at the beginning of the third light-emitting stage T33, the second capacitor C2 is discharged, and the potential value of the first end of the second capacitor C2 gradually decreases. However, the potential of the point S is still at a high level.

In the third light emitting stage T33 , the potential value of the first end of the second capacitor C2 can still keep the seventh transistor T7 turned off.

Since the seventh transistor T8 is turned off, the seventh transistor T7 still cannot transmit the first power signal VDD to point C. Therefore, the second end thereof does not transmit the compensation control signal to point C and does not change the potential value of point C.

The duration of the third light emitting stage T33 is greater than or equal to the duration of the voltage value of the first end of the second capacitor C2 being charged to the voltage value that turns on the seventh transistor T7.

Since the level states of other signals are the same as the level states of corresponding signals in the second light-emitting stage T32, the states of corresponding devices remain unchanged, and point D still transmits the driving signal to the light-emitting element LED, and the light-emitting element LED emits light according to the driving signal.

In the period corresponding to the non-luminous phase T4 in the driving signal timing diagram, the first luminous control signal EM1 is low, the second luminous control signal EM2 is low, the pulse width modulation signal PWM is low, the reset signal RESET is high, and the scanning signal SN is high.

Since the second light emitting control signal EM2 is at a low level, the eighth transistor T8 is turned on to transmit the first power signal VDD to the seventh transistor T7.

Since the pulse width modulation signal PWM is at a low level, the point S follows the discharge of the second capacitor C2 and is adjusted to a low level. The seventh transistor T7 is turned on to transmit the first power signal VDD to the point C.

Point C outputs the compensation control signal.

Since the compensation control signal transmitted at point C is the first power signal VDD, the potential value of the first end of the third capacitor C3 is adjusted following the potential value of the first power signal VDD.

Since the first light emitting control signal EM1 is at a low level, the first conduction control transistor T13 is turned on to transmit the first power signal VDD to the first end of the driving transistor T10.

Since the electric signal obtained by the control terminal of the driving transistor T10 is also the first power supply signal VDD, the difference between the potential value of the control terminal and the potential value of the first terminal is smaller than the threshold voltage, the driving transistor T10 is turned off and stops generating the driving signal.

Although the first light emitting control signal EM1 is at a low level and the second conduction control transistor T14 is turned on, the first end thereof no longer obtains the driving signal, and thus the driving signal cannot be transmitted to the point D.

Since the light emitting element LED no longer receives the driving signal, the light emitting element LED stops emitting light.

In the above technical solution, the light-emitting threshold compensation circuit controls the light-emitting duration of the light-emitting element according to the compensation control signal obtained during the light-emitting stage. During the light-emitting process, the light-emitting circuit composed of the first conduction control transistor, the driving transistor and the first conduction control transistor is turned on. The conduction transistor determines the current value flowing through the light-emitting circuit through the first power supply signal obtained and the second driving data stored in the data writing stage, as well as the threshold voltage, thereby determining the light-emitting intensity of the light-emitting element. Since the second driving data is compensated by the threshold voltage when it is generated, the above current is no longer affected by the threshold voltage, thereby ensuring the display uniformity of the light-emitting element.

Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims (13)

1. A display device, comprising:

a display panel on which a plurality of gate lines, a plurality of data lines, and a plurality of sub-pixel circuits are disposed;

Each of the sub-pixel circuits includes a pixel driving circuit and a light emitting element;

The pixel driving circuit is characterized by comprising a light-emitting threshold compensation circuit and an edge improvement circuit, wherein the light-emitting threshold compensation circuit comprises a driving transistor;

The edge improvement circuit is electrically connected with the grid line and is configured to acquire a pulse width modulation signal and output a compensation control signal according to the pulse width modulation signal in a display stage of each display period;

The light-emitting threshold compensation circuit is electrically connected with the edge improvement circuit and the data line and is configured to acquire driving data and the compensation control signal, and generate a corresponding driving signal by using the driving data compensated by the threshold voltage of the driving transistor when the compensation control signal is not output by the edge improvement circuit in the display stage of each display period; stopping generating the driving signal when the edge improvement circuit outputs the compensation control signal;

the light emitting element is electrically connected to the light emission threshold compensation circuit and configured to emit light according to the drive signal.

2. The display device according to claim 1, wherein the light emission threshold compensation circuit is further electrically connected to the gate line, and is configured to acquire first driving data and a scanning signal during a non-display phase of the display period, compensate the first driving data with a threshold voltage of the driving transistor, and generate and store second driving data;

In a light emitting stage in the display stage, generating and outputting a corresponding driving signal from an output end thereof according to the second driving data;

and in a non-light-emitting stage of the display stage, acquiring the compensation control signal, and stopping generating the driving signal according to the compensation control signal.

3. The display device according to claim 2, wherein a power line is further provided on the display panel; the light emission threshold compensation circuit further includes: a data input transistor, a threshold compensation transistor, and a third capacitance;

The data input transistor has a first end electrically connected to the data line, a second end electrically connected to the first end of the driving transistor, a control end electrically connected to the gate line, and configured to acquire the first driving data from the data line at the first end, acquire the scanning signal from the gate line at the control end, control a conductive state thereof by the scanning signal, and transmit the first driving data to the first end of the driving transistor when being conductive;

The first end of the threshold compensation transistor is electrically connected with the second end of the driving transistor, the second end of the threshold compensation transistor is electrically connected with the control end of the driving transistor, the control end of the threshold compensation transistor is electrically connected with the grid line, the threshold compensation transistor is configured to obtain the scanning signal from the grid line, and the conduction state of the threshold compensation transistor is controlled by the scanning signal;

The driving transistor is configured to determine second driving data from a control end of the driving transistor according to the first driving data and the threshold voltage when the threshold compensation transistor is turned on;

And a third capacitor having a first terminal electrically connected to the control terminal of the driving transistor, a second terminal electrically connected to the power line, and configured to store an electric signal obtained at the first terminal.

4. A display device according to claim 3, wherein the light emission threshold compensation circuit further comprises: a first conduction control transistor and a second conduction control transistor;

The first conduction control transistor is electrically connected with the power line at a first end, is electrically connected with the first end of the driving transistor at a second end, is electrically connected with the grid line at a control end, and is configured to acquire a first power supply signal from the power line at the first end, acquire a first light-emitting control signal from the grid line at the control end and control the conduction state of the first conduction control transistor by the light-emitting control signal;

The second turn-on control transistor has a first end electrically connected to the second end of the driving transistor, a second end electrically connected to the first end of the light emitting element, a control end electrically connected to the gate line, and a control end configured to obtain the light emission control signal from the gate line, and a turn-on state controlled by the first light emission control signal.

5. The display device according to claim 4, wherein the light emission threshold compensation circuit further comprises:

And the first end of the first reset transistor is electrically connected with the power line, the second end of the first reset transistor is electrically connected with the control end of the driving transistor, the control end of the first reset transistor is electrically connected with the grid line, the first end of the first reset transistor is configured to acquire a second power signal from the power line, the control end of the first reset transistor acquires a reset signal from the grid line, the reset signal controls the on state of the first reset transistor, and the second power signal is transmitted to the control end of the driving transistor when the first reset transistor is turned on to reset the control end of the driving transistor.

6. The display device according to claim 5, wherein the edge improvement circuit is configured to acquire a second light emission control signal, the pulse width modulation signal, and the first power supply signal, and to control a conduction state thereof by the second light emission control signal and the pulse width modulation signal;

And when the power supply is in a conducting state, outputting the first power supply signal as the compensation control signal.

7. The display device of claim 6, wherein the display phase is a next phase of the non-display phase during a display period; the non-display stage sequentially comprises a reset stage and a data writing stage;

In the non-display stage, the edge improvement circuit is in an off state and does not output the compensation control signal;

The light-emitting threshold compensation circuit generates and stores the second driving data without generating a driving signal;

the light emitting element does not emit light.

8. The display device according to claim 7, wherein in the reset period, the reset signal and the second power signal are at a first level, and the scan signal, the first light emission control signal and the second light emission control signal are at a second level;

the edge improvement circuit is turned off according to the second light-emitting control signal and does not output the compensation control signal;

The first reset transistor is conducted according to the reset signal, and transmits a second power signal obtained from the first end of the first reset transistor to the first end of the third capacitor and the control end of the driving transistor;

The third capacitor stores the second power supply signal;

the driving transistor is conducted according to the second power supply signal.

9. The display device according to claim 7, wherein in the data writing period, the scan signal is at a first level, and the reset signal, the first light emission control signal, and the second light emission control signal are at a second level;

the edge improvement circuit is turned off according to the second light-emitting control signal and does not output the compensation control signal;

The data input transistor is conducted according to the scanning signal, and first driving data obtained from the first end of the data input transistor are transmitted to the first end of the driving transistor;

the threshold compensation transistor is conducted according to the scanning signal, and the control end and the second end of the driving transistor are short-circuited;

the driving transistor is kept in a conducting state, and the voltage value of the control end of the driving transistor is determined to be second driving data according to the threshold voltage of the driving transistor and the first driving data;

the third capacitor stores the second driving data.

10. The display device according to claim 7, wherein the display stage sequentially includes a light-emitting stage and a non-light-emitting stage;

In the light-emitting stage, the edge improving circuit is in an off state and does not output the compensation control signal, and the light-emitting threshold compensation circuit generates a driving signal to control the light-emitting element to emit light;

And in the non-light-emitting stage, the edge improvement circuit is in a conducting state and outputs the compensation control signal, and the light-emitting threshold compensation circuit does not generate a driving signal when the compensation control signal is obtained and controls the light-emitting element to stop light emission.

11. The display device of claim 10, wherein the light-emitting phases include a first light-emitting phase, a second light-emitting phase, and a third light-emitting phase,

In the first light-emitting stage, the first light-emitting control signal is at a first level, and the reset signal, the scan signal, the pulse width modulation signal, the second light-emitting control signal and the first power signal are at a second level;

In the second light-emitting stage, the first light-emitting control signal and the second light-emitting control signal are at a first level, and the pulse width modulation signal, the reset signal, the scanning signal and the first power signal are at a second level;

In the third light emitting stage, the first light emitting control signal, the second light emitting control signal and the pulse width modulation signal are at a first level, and the reset signal and the scan signal are at a second level.

12. The display device of claim 11, wherein, during the lighting phase,

The edge improvement circuit is turned off according to the second light-emitting control signal and the pulse width modulation signal, and does not output the compensation control signal;

The first conduction control transistor is conducted according to the first light-emitting control signal, and transmits the first power signal obtained by the first end of the first conduction control transistor to the first end of the driving transistor;

the driving transistor is kept in a conducting state, and a driving signal irrelevant to the threshold voltage is output from a second end of the driving transistor according to the first power supply signal, the second driving data and the threshold voltage;

The second conduction control transistor is conducted according to the first light-emitting control signal and transmits the driving signal obtained by the first end of the second conduction control transistor to the first end of the light-emitting element;

The light emitting element emits light according to the driving signal.

13. The display device according to claim 11, wherein in the non-light-emitting period, the first light-emitting control signal, the second light-emitting control signal, and the pulse width modulation signal are at a first level, and the reset signal and the scan signal are at a second level;

The edge improvement circuit is conducted according to the second light-emitting control signal and the pulse width modulation signal and outputs the compensation control signal;

The first conduction control transistor and the second conduction control transistor are kept in a conduction state, the driving transistor is turned off according to the compensation control signal to stop generating the driving signal, and the second conduction transistor stops transmitting the driving signal;

The light emitting element stops emitting light.