CN118819385A - Data receiving method - Google Patents

Abstract

A data receiving method is used on a first electronic device and a second electronic device, comprising: step a of generating a plurality of count values using a counter; step b of receiving alignment data stored in the second electronic device using the first electronic device; step c of sampling the alignment data using a sampler in the first electronic device to generate a plurality of sampling values; step d of determining a sampling point and a sampling period of the sampler based on the sampling values and the count values; and step e of causing the sampler to sample other data transmitted by the second electronic device using the sampling point and the sampling period.

Description

Data receiving method

Technical Field

The invention relates to a data receiving method, and more particularly to a data receiving method capable of automatically setting a clock signal frequency to compensate for a signal delay.

Background Art

Flash memory is a common component in modern technology. However, data request instructions and data transmission may be delayed due to various factors, which limits circuit design and makes it difficult to set a better sampling clock signal.

Therefore, a novel data receiving method is needed to improve this problem.

Summary of the invention

An object of the present invention is to provide a data receiving method capable of compensating for signal delay.

One embodiment of the present invention discloses a data receiving method for use in a first electronic device and a second electronic device, comprising: (a) generating a plurality of count values using a counter; (b) receiving alignment data stored in the second electronic device using the first electronic device; (c) sampling the alignment data using a sampler in the first electronic device to generate a plurality of sampling values; (d) determining a sampling point and a sampling period of the sampler based on the sampling values and the count values; and (e) enabling the sampler to sample other data transmitted by the second electronic device using the sampling point and the sampling period.

According to the aforementioned embodiment, no matter what the delay condition between the flash memory controller and the flash memory is, the signal delay can be compensated by setting a better sampling point and sampling period, so that data can be received more accurately.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a block diagram of a flash memory controller and a flash memory according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a detailed structure of a flash memory controller according to an embodiment of the present invention.

FIG. 3 and FIG. 4 are schematic diagrams showing the operation of a flash memory controller according to different embodiments of the present invention.

FIG. 5 shows a flow chart of a data receiving method according to an embodiment of the present invention.

DETAILED DESCRIPTION

The present invention will be described below with multiple embodiments. Please note that the "first", "second" and similar descriptions in the following description are only used to define different elements, parameters, data, signals or steps, and are not used to limit their order. For example, the first device and the second device may have the same structure but are different devices.

FIG. 1 shows a block diagram of a flash memory controller and a flash memory according to an embodiment of the present invention. Please also note that the number of components and the configuration shown in FIG. 1 are for illustration only and are not intended to limit the scope of the present invention. In the embodiment of FIG. 1 , when the flash memory controller 101 wants to receive data from the flash memory 103, the flash memory controller 101 will first issue a data request instruction to the flash memory 103, and then the flash memory 103 will respond to the data request instruction and transmit the data to the flash memory controller 101. After receiving the data, the flash memory controller 101 will sample the data. However, the transmission of the data request instruction and the transmission of the data may be delayed, which may cause difficulties in sampling.

Taking FIG. 1 as an example, in one embodiment, the flash memory controller 101 is located in an IC (Integrated Circuit) 105, and the IC 105 further includes logic circuits LC_1, LC_2, LC_3, LC_4 and connection pads Pd_1 and Pd_2. The logic circuits LC_1, LC_2, LC_3, and LC_4 are connected in series between the connection pad Pd_1 and the flash memory controller 101, and between the connection pad Pd_2 and the flash memory 101 controller, respectively, thus causing delays D_1, D_2, D_3, D_6, D_7, and D_8. In addition, delays D_4 and D_5 are caused between the connection pads Pd_1, Pd_2 and the flash memory 103, respectively, and the flash memory 105 itself also causes delays. The aforementioned delays may vary due to differences in the layout of the circuit, the number of logic circuits, or the structure of the flash memory itself, which may make it difficult for the flash memory controller 101 to select the frequency of the sampling clock signal used for sampling when sampling. Even if the overall delay is calculated and the sampling clock signal frequency is set before the IC leaves the factory, the overall delay is fixed and cannot be changed. This will cause a lot of inconvenience when the delay changes due to circuit aging or other factors or when the flash memory 101 is to be changed. Therefore, the present invention provides a compensation mechanism in the following embodiments to automatically detect the delay and set a more appropriate sampling point and sampling period accordingly, that is, to set the sampling clock signal frequency.

FIG2 is a block diagram showing a detailed structure of a flash memory controller according to an embodiment of the present invention. As shown in FIG2 , the flash memory controller 101 includes a sampler 201, a judger 203, and a counter 205. The sampler 201, the judger 203, or the counter 205 can be implemented by writing a program in the flash memory controller 101, but can also be an independent circuit. In addition, the judger 203 or the counter 205 can also be set outside the flash memory controller 101, and is not limited to being set inside the flash memory controller 101.

In the embodiment of FIG. 2 , the flash memory 103 stores alignment data AD. In one embodiment, the alignment data AD is N-bit data and is stored in the initial N bits of the flash memory 103, where N is a positive integer greater than or equal to 2. For example, if the alignment data AD is 8-bit data, it will be stored in the 1st bit to the 8th bit of the flash memory 103. When the sampling clock signal is to be set, the counter 205 will continuously generate a plurality of count values CV_1, CV_2…. The flash memory controller 101 will receive the alignment data AD, and then the sampler 201 will sample the alignment data AD to generate a plurality of sampling values SV_1, SV_2…. The determiner 203 will determine a sampling point and a sampling cycle of the sampler 201 according to the sampling values SV_1, SV_2… and the count values CV_1, CV_2…, that is, determine the sampling time and sampling frequency at which the sampling clock signal starts sampling. After the sampling point and the sampling period are determined, the sampler 201 samples the other data subsequently transmitted by the flash memory controller 101 at the sampling point and the sampling period determined by the determiner 203. However, the alignment data AD is not limited to being stored in the initial N bits of the flash memory 103, and it can also be stored in the flash memory 103 in other ways. For example, the alignment data AD can be stored in the flash memory 103 periodically, such as 12 to 19 bits, 24 bits to 31 bits. As long as the flash memory controller 101 obtains the location where the alignment data AD is stored in advance or can determine that it has received the alignment data AD, the flash memory controller 101 can operate normally.

The following will explain how to determine the sampling point and sampling period based on the sampling values SV_1, SV_2... and the counting values CV_1, CV_2. However, please note that the following description is only for example and is not intended to limit the scope of the present invention. Figures 3 and 4 show schematic diagrams of the operation of a flash memory controller according to different embodiments of the present invention. In the embodiment of Figure 3, the signal CLK_C is the clock signal used by the flash memory controller 101, and the signal CLK_F is the clock signal used by the flash memory controller 101. In the embodiment of Figure 3, the frequency of the signal CLK_C is five times that of the signal CLK_F, but it is not intended to limit the present invention. The signal CLK_C is used as a sampling clock signal in the embodiment of Figure 3.

In the embodiment of FIG. 3 , the alignment data AD is 8-bit data 01010101 with different logic values. When the flash memory controller 101 issues a data receiving instruction to the flash memory 103 or after the data receiving instruction is issued, the counter 205 starts counting. When the count value is 0 to 31, since the flash memory controller 101 has not received any data, the sampled value is 0 or other meaningless values. When the counter counts to 27, the flash memory controller 101 starts to receive the alignment data AD. When the count value is 27 to 31, the sampler 201 samples the first bit 0 of the alignment data AD, but because 0 is also sampled when no data is received in the example of FIG. 3 , it is impossible to determine whether the alignment data AD is received. When the count value is 32 to 36, the sampler 201 samples the second bit 1 in the alignment data AD, and when the count value is 37 to 41, the sampler 201 samples the third bit 0 in the alignment data AD. According to such distribution, the middle time point of the first group of consecutive identical sampled values that can be identified is the sampling point, and then the sampling period is calculated based on this sampling point and the middle time point of the next group of consecutive identical sampled values. Taking the embodiment of FIG. 3 as an example, when the count value is 32 to 36, the first group of consecutive sampled values 1 that can be identified is obtained, and the middle time point is when the count value is 34. Therefore, the time point when the count value is 34 can be used as the sampling point. When the count value is 37 to 41, the second group of consecutive sampled values 0 is obtained, and the middle time point is 39. Therefore, the sampling period can be calculated from the sampling point and the time point when the count value is 39. In the example of FIG. 3, since the count value 34 and the count value 39 differ by 5 time periods of the signal CLK_C, the calculated sampling period is 5 time periods of the signal CLK_C.

In the embodiment of FIG. 3 , the number of consecutive identical sample values is an odd number (5), but the example shown in FIG. 3 can also be applied to the case where the number of consecutive identical sample values is an even number. In the example of FIG. 4 , when the count value is 0 to 31, since the flash memory controller 101 has not received any data, the sample value is 0 or other meaningless values. When the counter counts to 28, the flash memory controller 101 begins to receive the alignment data AD. When the count value is 28 to 31, the first bit 0 of the alignment data AD is sampled, but because 0 is also sampled when no data is received in the example of FIG. 4 , it is impossible to determine whether the alignment data AD is received. When the count value is 32 to 35, the sampler 201 samples the second bit 1 in the alignment data AD, and when the count value is 36 to 39, the sampler 201 samples the third bit 0 in the alignment data AD. According to such distribution, as in FIG. 3 , the middle time point of the first identifiable group of consecutive identical sampling values is used as the sampling point, and then the sampling period is calculated based on this sampling point and the middle time point of the next group of consecutive identical sampling values.

However, in the embodiment of FIG. 4 , because the number of continuous sampling values is an even number (4), there are two time points in the middle time point. In such a case, any one of the middle time points can be used to calculate the sampling point and the sampling period. Specifically, taking the embodiment of FIG. 3 as an example, when the count value is 32 to 35, the first group of continuous sampling values 1 is obtained, and the middle time point is when the count value is 33 or 34. Therefore, the time point when the count value is 33 or 34 can be used as the sampling point. When the count value is 36 to 39, the second group of continuous sampling values 0 is obtained, and the middle time point is when the count value is 37 or 38, so the sampling point and the time point when the count value is 37 or 38 can be used to calculate the sampling period. In one embodiment, if the number of continuous sampling values measured is an even number, the flash memory controller 101 can adjust the speed of the counter so that the sampling point and the sampling period are determined when the number of continuous sampling values is an odd number.

The examples of FIG. 3 and FIG. 4 can be briefly illustrated as follows: if the sampled values include a plurality of consecutive first sampled values having a first logic value (such as the sampled value 1 when the count value is 32 to 36 in FIG. 3) and a plurality of consecutive second sampled values having a second logic value (such as the sampled value 0 when the count value is 37 to 41 in FIG. 3), the sampling point is determined according to the first sampling time of at least one intermediate first sampled value, and the sampling period is determined according to a time difference between the first sampling time and the second sampling time of at least one intermediate second sampled value. The intermediate first sampled value is a first sampled value with a sampling time in the middle among the first sampled values. The intermediate second sampled value is a second sampled value with a sampling time in the middle among the second sampled values. In the example of FIG. 3, the intermediate first sampled value is the sampled value 1 when the count value is 34, and the intermediate second sampled value is the sampled value 0 when the count value is 39. In the example of FIG. 4, the intermediate first sampled value is the sampled value 1 when the count value is 33 or 34, and the intermediate second sampled value is the sampled value 0 when the count value is 37 or 38.

The aforementioned action of setting the sampling clock signal can be automatically performed by the flash memory controller 101 before the flash memory controller 101 changes from being unpowered to being powered on and before any access action to the flash memory 103 is performed. As mentioned above, the flash memory controller 101 can be set in an IC 105. In this case, when the IC 105 changes from being unpowered (not receiving power) to being powered on (receiving power), the flash memory controller 101 changes from being unpowered to being powered on and automatically performs the aforementioned action of setting the sampling clock signal. In another embodiment, the flash memory controller 101 and the flash memory 103 are both located in an electronic system. The electronic system can be any form of electronic device, such as a computer, a mobile phone, or a wearable device. In this case, the aforementioned action of setting the sampling clock signal can be automatically performed after the electronic system changes from being unpowered to being powered on and before any access action to the flash memory 103 is performed. However, the aforementioned action of setting the sampling clock signal can also be automatically performed periodically or non-periodically to ensure the accuracy of data access. Alternatively, the flash memory controller 101 can also automatically perform the action of setting the sampling clock signal after the flash memory controller 101 receives a test instruction.

Although the above embodiment uses the flash memory controller 101 and the flash memory 103, they can also be replaced by other electronic devices. Therefore, according to the above embodiment, the data receiving method shown in FIG. 5 can be obtained, which includes the following steps.

Figure 5 contains the following steps:

Step 501

A counter is used to generate a plurality of count values (eg, the counter 205 in FIG. 2 ).

Step 503

A first electronic device (eg, flash memory controller 101) receives alignment data (eg, alignment data AD) stored in a second electronic device (eg, flash memory 103). The first electronic device can be regarded as a data receiving device, and the second electronic device can be regarded as a target device.

Step 505

A sampler (eg, sampler 201 ) in the first electronic device samples the alignment data to generate a plurality of sample values.

Step 507

A sampling point and a sampling period of the sampler are determined according to the sampling value and the counting value.

Step 509

The sampler is enabled to sample other data transmitted by the second electronic device using a sampling point and a sampling period.

According to the aforementioned embodiment, no matter what the delay condition between the flash memory controller and the flash memory is, the signal delay can be compensated by setting a better sampling point and sampling period, so that data can be received more accurately.

The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

【Explanation of symbols】

101 Flash Memory Controller

103 Flash memory

105IC

201 Sampler

203 Judgement

205 Counter

AD Alignment Data

CLK_C, CLK_F signals

CV_1, CV_2 count values

D_1, D_2, D_3, D_4, D_5, D_6, D_7, D_8 delay

LC_1, LC_2, LC_3, LC_4 logic circuit

Pd_1, Pd_2 connection pads

SV_1, SV_2 sampling values.

Claims (10)

1. A data receiving method, used on a first electronic device and a second electronic device, includes:

Step a, generating a plurality of count values by a counter;

Step b, receiving the alignment data stored in the second electronic device by the first electronic device;

step c, sampling the alignment data by a sampler in the first electronic device to generate a plurality of sampling values;

step d, determining a sampling point and a sampling period of the sampler according to the plurality of sampling values and the plurality of count values; and

Step e, the sampler samples other data transmitted by the second electronic device with the sampling point and the sampling period.

2. The data receiving method of claim 1, wherein the first electronic device is located in an IC and the counter is located in the IC.

3. The data receiving method as claimed in claim 2, wherein the first electronic device is a flash memory controller and the second electronic device is a flash memory.

4. The data receiving method as claimed in claim 3, wherein the alignment data is N-bit data and is stored in the first N bits of the flash memory or is periodically stored in the flash memory.

5. The data receiving method of claim 1,

If the plurality of sampling values includes a plurality of consecutive first sampling values having a first logic value and a plurality of consecutive second sampling values having a second logic value, the step d determines the sampling point according to a first sampling time of at least one intermediate first sampling value, and determines the sampling period according to a time difference between the first sampling time and a second sampling time of at least one intermediate second sampling value;

the middle first sampling value is the first sampling value with the sampling time in the middle in the plurality of first sampling values;

the intermediate second sample value is the second sample value with the sampling time in the middle among the plurality of second sample values.

6. The data receiving method of claim 1, wherein the alignment data is a plurality of bit data having a plurality of logic values.

7. The data receiving method of claim 6, wherein the alignment data is data having logical values of 1 and 0.

8. The data receiving method of claim 7, wherein the alignment data is 01010101.

9. The method of claim 1, wherein the steps a, b, c, d and e are performed before the first electronic device has never been started to be started and any access to the second electronic device has not been performed.

10. The method of claim 1, wherein the first electronic device and the second electronic device are located in an electronic system, wherein the steps a, b, c, d and e are performed after the electronic system is turned on from a non-powered-on state and before any access to the second electronic device is performed.